void s3c_i2c3_cfg_gpio(struct platform_device *dev)
{
#ifndef CONFIG_TARGET_LOCALE_EUR
s3c_gpio_cfgpin(S5PV310_GPA1(2), S3C_GPIO_SFN(3));
s3c_gpio_setpull(S5PV310_GPA1(2), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S5PV310_GPA1(3), S3C_GPIO_SFN(3));
s3c_gpio_setpull(S5PV310_GPA1(3), S3C_GPIO_PULL_UP);
#endif
}
static void s3c_gibgpio_init(struct bit_data *gpio)
{
GIB_DBG;
gpio->gpa4= S5PV310_GPA1(4);
gpio->gpa5= S5PV310_GPA1(5);
s3c_gpio_cfgpin(gpio->gpa4, S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(gpio->gpa5, S3C_GPIO_SFN(2));
gpio->gps_bb_sync= S5PV310_GPL0(0);
gpio->gps_isign= S5PV310_GPL0(1);
gpio->gps_imag= S5PV310_GPL0(2);
gpio->gps_qsign = S5PV310_GPL0(3);
gpio->gps_qmag= S5PV310_GPL0(4);
gpio->gps_bb_mclk= S5PV310_GPL0(5);
gpio->rf_reset= S5PV310_GPL0(6);
gpio->clkreq= S5PV310_GPL0(7);
gpio->bb_scl= S5PV310_GPL1(0);
gpio->bb_sda= S5PV310_GPL1(1);
gpio->gps_bb_epoch= S5PV310_GPL1(2);
gpio->gps_gpio0 = S5PV310_GPL2(0);
gpio->gps_gpio1 = S5PV310_GPL2(1);
gpio->gps_gpio2 = S5PV310_GPL2(2);
gpio->gps_gpio3 = S5PV310_GPL2(3);
gpio->gps_gpio4 = S5PV310_GPL2(4);
gpio->gps_gpio5 = S5PV310_GPL2(5);
gpio->gps_gpio6 = S5PV310_GPL2(6);
gpio->gps_gpio7 = S5PV310_GPL2(7);
s3c_gpio_cfgpin(gpio->gps_bb_sync, S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(gpio->gps_isign, S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(gpio->gps_imag, S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(gpio->gps_qsign, S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(gpio->gps_qmag, S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(gpio->gps_bb_mclk, S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(gpio->rf_reset, S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(gpio->clkreq, S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(gpio->bb_scl, S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(gpio->bb_sda, S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(gpio->gps_bb_epoch, S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(gpio->gps_gpio0, S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(gpio->gps_gpio1, S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(gpio->gps_gpio2, S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(gpio->gps_gpio3, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio->gps_bb_sync, 0x1);
s3c_gpio_setpull(gpio->gps_isign, 0x1);
s3c_gpio_setpull(gpio->gps_imag, 0x1);
s3c_gpio_setpull(gpio->gps_qsign, 0x1);
s3c_gpio_setpull(gpio->gps_qmag, 0x1);
s3c_gpio_setpull(gpio->gps_bb_mclk, 0x1);
s3c_gpio_setpull(gpio->rf_reset, 0x1);
s3c_gpio_setpull(gpio->clkreq, 0x1);
s3c_gpio_setpull(gpio->bb_scl, 0x1);
s3c_gpio_setpull(gpio->bb_sda, 0x1);
s3c_gpio_setpull(gpio->gps_bb_epoch, 0x1);
}
* structure gpio_cfg in the init function below.
*
* The 'base' member is also initialized in the init function below.
* Note: The initialization of 'base' member of s3c_gpio_chip structure
* uses the above macro and depends on the banks being listed in order here.
*/
static struct s3c_gpio_chip s5pv310_gpio_part1_4bit[] = {
{
.chip = {
.base = S5PV310_GPA0(0),
.ngpio = S5PV310_GPIO_A0_NR,
.label = "GPA0",
},
}, {
.chip = {
.base = S5PV310_GPA1(0),
.ngpio = S5PV310_GPIO_A1_NR,
.label = "GPA1",
},
}, {
.chip = {
.base = S5PV310_GPB(0),
.ngpio = S5PV310_GPIO_B_NR,
.label = "GPB",
},
}, {
.chip = {
.base = S5PV310_GPC0(0),
.ngpio = S5PV310_GPIO_C0_NR,
.label = "GPC0",
},