C++ (Cpp) S5P_MIPI_DPHY_CONTROLの例

コード例 #1

ファイル: setup-dsim.c プロジェクト: 123good/ninphetamine3

static void s5p_dsim_enable_dsi_master(unsigned char enable)
{
	unsigned int reg;

	reg = (readl(S5P_MIPI_DPHY_CONTROL(0))) & ~(1 << 2);
	reg |= (enable << 2);
	writel(reg, S5P_MIPI_DPHY_CONTROL(0));
}

コード例 #2

ファイル: setup-dsim.c プロジェクト: 123good/ninphetamine3

static void s5p_dsim_enable_d_phy(unsigned char enable)
{
	unsigned int reg;

	reg = readl(S5P_MIPI_DPHY_CONTROL(0));
	if (enable)
		reg |= S5P_MIPI_DPHY_ENABLE;
	else if (!(reg & S5P_MIPI_DPHY_SRESETN))
		reg &= ~S5P_MIPI_DPHY_ENABLE;
	writel(reg, S5P_MIPI_DPHY_CONTROL(0));
}

コード例 #3

ファイル: setup-mipidsim.c プロジェクト: elixirflash/dm-keepfast

int s5p_dsim_part_reset(struct mipi_dsim_device *dsim)
{
#if defined(CONFIG_ARCH_EXYNOS5)
	if (dsim->id == 0)
		writel(S5P_MIPI_M_RESETN, S5P_MIPI_DPHY_CONTROL(1));
#else
	if (dsim->id == 0)
		writel(S5P_MIPI_M_RESETN, S5P_MIPI_DPHY_CONTROL(0));
#endif
	return 0;
}

コード例 #4

ファイル: setup-mipidsim.c プロジェクト: Biktorgj/Android_b2_Kernel

static int s5p_dsim_enable_d_phy(struct mipi_dsim_device *dsim,
		unsigned int enable)
{
	unsigned int reg;
#if defined(CONFIG_ARCH_EXYNOS5)
#ifdef CONFIG_S5P_DEV_MIPI_DSIM0
	reg = readl(S5P_MIPI_DPHY_CONTROL(0)) & ~(1 << 0);
	/*TODO: enable bit is shared by DSI and CSI,
	 *      to use runtime PM or reference count*/
	reg |= (enable << 0);
	writel(reg, S5P_MIPI_DPHY_CONTROL(0));
#else
#if defined CONFIG_SOC_EXYNOS5260
	reg = readl(S5P_MIPI_DPHY_CONTROL(0)) & ~(1 << 0);
	/*
         * TODO: enable bit is shared by DSI and CSI,
         *      to use runtime PM or reference count.
         *      and now it cannot be disable.
         */
	if ((reg & S5P_MIPI_DPHY_SRESETN))
		reg |= (1 << 0);
	else
		reg |= (enable << 0);
	writel(reg, S5P_MIPI_DPHY_CONTROL(0));
#else
	reg = readl(S5P_MIPI_DPHY_CONTROL(1)) & ~(1 << 0);
	reg |= (enable << 0);
	writel(reg, S5P_MIPI_DPHY_CONTROL(1));
#endif
#endif
#else
#if defined CONFIG_SOC_EXYNOS3470
	reg = readl(S5P_MIPI_DPHY_CONTROL(0)) & ~(1 << 0);
	/*
         * TODO: enable bit is shared by DSI and CSI,
         *      to use runtime PM or reference count.
         *      and now it cannot be disable.
         */
	if ((reg & S5P_MIPI_DPHY_SRESETN))
		reg |= (1 << 0);
	else
		reg |= (enable << 0);
	writel(reg, S5P_MIPI_DPHY_CONTROL(0));
#else
	reg = readl(S5P_MIPI_DPHY_CONTROL(0)) & ~(1 << 0);
	reg |= (enable << 0);
	writel(reg, S5P_MIPI_DPHY_CONTROL(0));
#endif
#endif
	return 0;
}

コード例 #5

ファイル: setup-mipidsim.c プロジェクト: Biktorgj/Android_b2_Kernel

static int s5p_dsim_enable_dsi_master(struct mipi_dsim_device *dsim,
	unsigned int enable)
{
	unsigned int reg;
#if defined(CONFIG_ARCH_EXYNOS5)
#ifdef CONFIG_S5P_DEV_MIPI_DSIM0
	reg = readl(S5P_MIPI_DPHY_CONTROL(0)) & ~(1 << 2);
	reg |= (enable << 2);
	writel(reg, S5P_MIPI_DPHY_CONTROL(0));
#else
#if defined CONFIG_SOC_EXYNOS5260
	reg = readl(S5P_MIPI_DPHY_CONTROL(0)) & ~(1 << 2);
	reg |= (enable << 2);
	writel(reg, S5P_MIPI_DPHY_CONTROL(0));
#else
	reg = readl(S5P_MIPI_DPHY_CONTROL(1)) & ~(1 << 2);
	reg |= (enable << 2);
	writel(reg, S5P_MIPI_DPHY_CONTROL(1));

#endif
#endif
#else
	reg = readl(S5P_MIPI_DPHY_CONTROL(0)) & ~(1 << 2);
	reg |= (enable << 2);
	writel(reg, S5P_MIPI_DPHY_CONTROL(0));
#endif
	return 0;
}

コード例 #6

ファイル: setup-mipidsim.c プロジェクト: elixirflash/dm-keepfast

static int s5p_dsim_enable_d_phy(struct mipi_dsim_device *dsim,
		unsigned int enable)
{
	unsigned int reg;
#if defined(CONFIG_ARCH_EXYNOS5)
	reg = readl(S5P_MIPI_DPHY_CONTROL(1)) & ~(1 << 0);
	/*TODO: enable bit is shared by DSI and CSI,
	 *      to use runtime PM or reference count*/
	reg |= (1 << 0);
	writel(reg, S5P_MIPI_DPHY_CONTROL(1));
#else
	reg = readl(S5P_MIPI_DPHY_CONTROL(0)) & ~(1 << 0);
	reg |= (enable << 0);
	writel(reg, S5P_MIPI_DPHY_CONTROL(0));
#endif
	return 0;
}

コード例 #7

ファイル: setup-exynos5-mipiphy.c プロジェクト: 4pao/android_kernel_hardkernel_odroidxu3

static int __exynos5_mipi_phy_control(int id, bool on, u32 reset)
{
	void __iomem *addr_phy;
	u32 cfg;

	addr_phy = S5P_MIPI_DPHY_CONTROL(id);

	cfg = __raw_readl(addr_phy);
	cfg = (cfg | S5P_MIPI_DPHY_SRESETN);
	__raw_writel(cfg, addr_phy);

	if (1) {
		cfg |= S5P_MIPI_DPHY_ENABLE;
	} else if (!(cfg & (S5P_MIPI_DPHY_SRESETN | S5P_MIPI_DPHY_MRESETN)
			& (~S5P_MIPI_DPHY_SRESETN))) {
		cfg &= ~S5P_MIPI_DPHY_ENABLE;
	}

	__raw_writel(cfg, addr_phy);

	return 0;
}

コード例 #8

ファイル: setup-exynos-mipiphy.c プロジェクト: cm-3470/android_kernel_samsung_degaslte

static int __exynos_mipi_phy_control(int id, bool on, u32 reset)
{
    static DEFINE_SPINLOCK(lock);
    void __iomem *addr;
    unsigned long flags;
    u32 cfg;

    if (id != 0 && id != 1 && id != 2) {
        pr_err("id(%d) is invalid", id);
        return -EINVAL;
    }

    addr = S5P_MIPI_DPHY_CONTROL(id);

    spin_lock_irqsave(&lock, flags);

#if defined(CONFIG_SOC_EXYNOS5430)
    if (reset == S5P_MIPI_DPHY_SRESETN) {
        pr_err("id(%d) should be implement", id);
        /* __exynos_mipi_cam_phy_control(id, on, reset); */
    }
#else
    cfg = __raw_readl(addr);
    cfg = on ? (cfg | reset) : (cfg & ~reset);
    __raw_writel(cfg, addr);

    if (on) {
        cfg |= S5P_MIPI_DPHY_ENABLE;
    } else if (!(cfg & (S5P_MIPI_DPHY_SRESETN |
                        S5P_MIPI_DPHY_MRESETN) & ~reset)) {
        cfg &= ~S5P_MIPI_DPHY_ENABLE;
    }

    __raw_writel(cfg, addr);
#endif
    spin_unlock_irqrestore(&lock, flags);

    return 0;
}

コード例 #9

ファイル: setup-mipiphy.c プロジェクト: DijonLin/meizu-m9-kernel

static int __s5p_mipi_phy_control(struct platform_device *pdev,
				  bool on, u32 reset)
{
	static DEFINE_SPINLOCK(lock);
	void __iomem *addr;
	unsigned long flags;
	int pid;
	u32 cfg;

	if (!pdev)
		return -EINVAL;

	pid = (pdev->id == -1) ? 0 : pdev->id;

	if (pid != 0 && pid != 1)
		return -EINVAL;

	addr = S5P_MIPI_DPHY_CONTROL(pid);

	spin_lock_irqsave(&lock, flags);

	cfg = __raw_readl(addr);
	cfg = on ? (cfg | reset) : (cfg & ~reset);
	__raw_writel(cfg, addr);

	if (on) {
		cfg |= S5P_MIPI_DPHY_ENABLE;
	} else if (!(cfg & (S5P_MIPI_DPHY_SRESETN |
			    S5P_MIPI_DPHY_MRESETN) & ~reset)) {
		cfg &= ~S5P_MIPI_DPHY_ENABLE;
	}

	__raw_writel(cfg, addr);
	spin_unlock_irqrestore(&lock, flags);

	return 0;
}

コード例 #10

ファイル: setup-exynos5-mipiphy.c プロジェクト: 4pao/android_kernel_hardkernel_odroidxu3

static int __exynos5_mipi_phy_control(int id, bool on, u32 reset)
{
	static DEFINE_SPINLOCK(lock);
	void __iomem *addr_phy;
	void __iomem *addr_reset;
	unsigned long flags;
	u32 cfg;
	u32 csi_reset = 0;
	u32 dsi_reset = 0;

	addr_phy = S5P_MIPI_DPHY_CONTROL(id);

	spin_lock_irqsave(&lock, flags);

	/* PHY reset */
	switch(id) {
	case 0:
		if (reset == S5P_MIPI_DPHY_SRESETN) {
			if (readl(S5P_VA_PMU + 0x4024) & 0x1) {
				addr_reset = S5P_VA_SYSREG_CAM0 + 0x0014;
				cfg = __raw_readl(addr_reset);
				cfg = on ? (cfg | MIPI_PHY_BIT0) : (cfg & ~MIPI_PHY_BIT0);
				__raw_writel(cfg, addr_reset);
			}
		} else {
			if (readl(S5P_VA_PMU + 0x4084) & 0x1) {
				addr_reset = S5P_VA_SYSREG_DISP + 0x000c;
				cfg = __raw_readl(addr_reset);
				cfg = on ? (cfg | MIPI_PHY_BIT0) : (cfg & ~MIPI_PHY_BIT0);
				__raw_writel(cfg, addr_reset);
			}
		}
		break;
	case 1:
		if (readl(S5P_VA_PMU + 0x4024) & 0x1) {
			addr_reset = S5P_VA_SYSREG_CAM0 + 0x0014;
			cfg = __raw_readl(addr_reset);
			cfg = on ? (cfg | MIPI_PHY_BIT1) : (cfg & ~MIPI_PHY_BIT1);
			__raw_writel(cfg, addr_reset);
		}
		break;
	case 2:
		if (readl(S5P_VA_PMU + 0x40A4) & 0x1) {
			addr_reset = S5P_VA_SYSREG_CAM1 + 0x0020;
			cfg = __raw_readl(addr_reset);
			cfg = on ? (cfg | MIPI_PHY_BIT0) : (cfg & ~MIPI_PHY_BIT0);
			__raw_writel(cfg, addr_reset);
		}
		break;
	default:
		pr_err("id(%d) is invalid", id);
		return -EINVAL;
	}

	/* CHECK CMA0 PD STATUS */
	if (readl(S5P_VA_PMU + 0x4024) & 0x1) {
		addr_reset = S5P_VA_SYSREG_CAM0 + 0x0014;
		csi_reset = __raw_readl(addr_reset);
	}

	/* CHECK DISP PD STATUS */
	if (readl(S5P_VA_PMU + 0x4084) & 0x1) {
		addr_reset = S5P_VA_SYSREG_DISP + 0x000c;
		dsi_reset = __raw_readl(addr_reset);
	}

	/* PHY PMU enable */
	cfg = __raw_readl(addr_phy);

	if (on)
		cfg |= S5P_MIPI_DPHY_ENABLE;
	else {
		if (id == 0) {
			if(!((csi_reset | dsi_reset) & MIPI_PHY_BIT0))
				cfg &= ~S5P_MIPI_DPHY_ENABLE;
		} else {
			cfg &= ~S5P_MIPI_DPHY_ENABLE;
		}
	}

	__raw_writel(cfg, addr_phy);
	spin_unlock_irqrestore(&lock, flags);

	return 0;
}

コード例 #11

ファイル: setup-exynos5-mipiphy.c プロジェクト: MukeshMM/android_kernel_samsung_j2lte

static int __exynos5_mipi_phy_control(int id, bool on, u32 reset)
{
	static DEFINE_SPINLOCK(lock);
	void __iomem *addr_phy;
	void __iomem *addr_reset;
	unsigned long flags;
	u32 cfg;

	addr_phy = S5P_MIPI_DPHY_CONTROL(id);

	spin_lock_irqsave(&lock, flags);

	/* PHY PMU enable */
	if (on) {
		cfg = __raw_readl(addr_phy);
		cfg |= S5P_MIPI_DPHY_ENABLE;
		__raw_writel(cfg, addr_phy);
	}

	/* PHY reset */
	switch (id) {
	case 0:
		if (reset == S5P_MIPI_DPHY_SRESETN) {
			if (readl(EXYNOS5430_CAM0_STATUS) & 0x1) {
				addr_reset = S5P_VA_SYSREG_CAM0 + 0x1014;
				cfg = __raw_readl(addr_reset);
				cfg = on ? (cfg | MIPI_PHY_BIT0) : (cfg & ~MIPI_PHY_BIT0);
				__raw_writel(cfg, addr_reset);
			}
		} else {
			if (readl(EXYNOS5430_DISP_STATUS) & 0x1) {
				addr_reset = S5P_VA_SYSREG_DISP + 0x000c;
				cfg = __raw_readl(addr_reset);

				/* 0: enable reset, 1: release reset */
				cfg = (cfg & ~MIPI_PHY_BIT0);
				__raw_writel(cfg, addr_reset);
				cfg = (cfg | MIPI_PHY_BIT0);
				__raw_writel(cfg, addr_reset);
			}
		}
		break;
	case 1:
		if (readl(EXYNOS5430_CAM0_STATUS) & 0x1) {
			addr_reset = S5P_VA_SYSREG_CAM0 + 0x1014;
			cfg = __raw_readl(addr_reset);
			cfg = on ? (cfg | MIPI_PHY_BIT1) : (cfg & ~MIPI_PHY_BIT1);
			__raw_writel(cfg, addr_reset);
		}
		break;
	case 2:
		if (readl(EXYNOS5430_CAM1_STATUS) & 0x1) {
			addr_reset = S5P_VA_SYSREG_CAM1 + 0x1020;
			cfg = __raw_readl(addr_reset);
			cfg = on ? (cfg | MIPI_PHY_BIT0) : (cfg & ~MIPI_PHY_BIT0);
			__raw_writel(cfg, addr_reset);
		}
		break;
	default:
		pr_err("id(%d) is invalid", id);
		spin_unlock_irqrestore(&lock, flags);
		return -EINVAL;
	}

	/* PHY PMU disable */
	if (!on) {
		cfg = __raw_readl(addr_phy);
		if (id == 0) {
			if (!exynos5_phy0_is_running(reset))
				cfg &= ~S5P_MIPI_DPHY_ENABLE;
		} else {
			cfg &= ~S5P_MIPI_DPHY_ENABLE;
		}
		__raw_writel(cfg, addr_phy);
	}

	spin_unlock_irqrestore(&lock, flags);

	return 0;
}

コード例 #12

ファイル: setup-dsim.c プロジェクト: 123good/ninphetamine3

void s5p_dsim_part_reset(void)
{
	writel(S5P_MIPI_M_RESETN, S5P_MIPI_DPHY_CONTROL(0));
}