static int qcom_ipq806x_sata_phy_init(struct phy *generic_phy) { struct qcom_ipq806x_sata_phy *phy = phy_get_drvdata(generic_phy); u32 reg; /* Setting SSC_EN to 1 */ reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3); reg = reg | SATA_PHY_SSC_EN; writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3); reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) & ~(SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK | SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK | SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK); reg |= SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(0xf); writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0); reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM1) & ~(SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK | SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK | SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK); reg |= SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(0x55) | SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(0x55) | SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(0x55); writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM1); reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM2) & ~SATA_PHY_P0_PARAM2_RX_EQ_MASK; reg |= SATA_PHY_P0_PARAM2_RX_EQ(0x3); writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM2); /* Setting PHY_RESET to 1 */ reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); reg = reg | SATA_PHY_RESET; writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4); /* Setting REF_SSP_EN to 1 */ reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); reg = reg | SATA_PHY_REF_SSP_EN | SATA_PHY_RESET; writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4); /* make sure all changes complete before we let the PHY out of reset */ mb(); /* sleep for max. 50us more to combine processor wakeups */ usleep_range(20, 20 + 50); /* Clearing PHY_RESET to 0 */ reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); reg = reg & ~SATA_PHY_RESET; writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4); return 0; }
static int msm_sata_phy_init(struct device *dev) { /* Synopsys PHY specific Power Up Sequence */ u32 reg = 0; struct platform_device *pdev = to_platform_device(dev); struct msm_sata_hba *hba = dev_get_drvdata(dev); struct resource *mem; mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_mem"); if (!mem) { dev_err(dev, "no mmio space\n"); return -EINVAL; } hba->phy_base = devm_ioremap(dev, mem->start, resource_size(mem)); if (!hba->phy_base) { dev_err(dev, "failed to allocate memory for SATA PHY\n"); return -ENOMEM; } /* Setting SSC_EN to 1 */ reg = readl_relaxed(hba->phy_base + SATA_PHY_P0_PARAM3); reg = reg | 0x08; writel_relaxed(reg, hba->phy_base + SATA_PHY_P0_PARAM3); reg = readl_relaxed(hba->phy_base + SATA_PHY_P0_PARAM0) & ~(SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK | SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK | SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK); reg |= SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(hba->tx_preemph_gen3); writel_relaxed(reg, hba->phy_base + SATA_PHY_P0_PARAM0); reg = readl_relaxed(hba->phy_base + SATA_PHY_P0_PARAM1) & ~(SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK | SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK | SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK); reg |= SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(0x55) | SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(0x55) | SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(0x55); writel_relaxed(reg, hba->phy_base + SATA_PHY_P0_PARAM1); reg = readl_relaxed(hba->phy_base + SATA_PHY_P0_PARAM2) & ~SATA_PHY_P0_PARAM2_RX_EQ_MASK; reg |= SATA_PHY_P0_PARAM2_RX_EQ(hba->rx_eq); writel_relaxed(reg, hba->phy_base + SATA_PHY_P0_PARAM2); /* Setting PHY_RESET to 1 */ reg = readl_relaxed(hba->phy_base + SATA_PHY_P0_PARAM4); reg = reg | 0x01; writel_relaxed(reg, hba->phy_base + SATA_PHY_P0_PARAM4); /* Setting REF_SSP_EN to 1 */ reg = readl_relaxed(hba->phy_base + SATA_PHY_P0_PARAM4); reg = reg | 0x03; writel_relaxed(reg, hba->phy_base + SATA_PHY_P0_PARAM4); mb(); msm_sata_delay_us(20); /* Clearing PHY_RESET to 0 */ reg = readl_relaxed(hba->phy_base + SATA_PHY_P0_PARAM4); reg = reg & 0xfffffffe; writel_relaxed(reg, hba->phy_base + SATA_PHY_P0_PARAM4); reg = readl_poll_timeout(hba->ahci_base + SATA_CNT_P0_PHYSR, reg, (reg & 1), POLL_PERIOD_US, TIMEOUT_PERIOD_US); if (reg) { dev_err(dev, "poll timeout SATA_CNT_P0_PHYSR\n"); /* power down PHY in case of failure */ msm_sata_phy_deinit(dev); return reg; } /* MPLL setting */ if (hba->mpll) writel_relaxed(hba->mpll, hba->phy_base + SATA_PHY_MPLL); /* Term Offset */ if (hba->term_off) writel_relaxed(hba->term_off, hba->phy_base + SATA_PHY_TX_DRIV_CTRL2); return 0; }