/** * \brief Start ILI9488 DMA transfer . * \param pTxBuffer point to Tx buffer address * \param wTxSize Tx buffer size in byte * \returns 0 if the xDMA configuration successfully; otherwise returns * ILI9488_DMA_ERROR_XXX. */ uint8_t ILI9488DmaTxTransfer( uint16_t *pTxBuffer,uint32_t wTxSize) { _ILI9488DmaUpdateBuffer(pTxBuffer, wTxSize, 0, 0); SCB_CleanInvalidateDCache(); if (XDMAD_StartTransfer( ili9488Dma.xdmaD, ili9488Dma.ili9488DmaTxChannel)) return ILI9488_ERROR_DMA_TRANSFER; while(!ili9488DmaCtl.txDone); ili9488DmaCtl.txDone = 0; return 0; }
/** * \brief Starts a UART master transfer. This is a non blocking function. It * will return as soon as the transfer is started. * * \param pUartd Pointer to a UartDma instance. * \returns 0 if the transfer has been started successfully; otherwise returns * UARTD_ERROR_LOCK is the driver is in use, or UARTD_ERROR if the command is * not valid. */ uint32_t UARTD_RcvData( UartDma *pUartd) { SCB_CleanInvalidateDCache(); pUartd->pRxChannel->sempaphore=0; memory_barrier(); /* Start DMA 0(RX) && 1(TX) */ if (XDMAD_StartTransfer( pUartd->pXdmad, pUartd->pRxChannel->ChNum )) return USARTD_ERROR_LOCK; return 0; }
/** * \brief Start ILI9488 DMA Rx transfer . * \param pRxBuffer point to Rx buffer address * \param wRxSize Rx buffer size in byte * \returns 0 if the xDMA transfer successfully; otherwise returns ILI9488_DMA_ERROR_XXX. */ uint8_t ILI9488DmaRxTransfer(uint32_t *pRxBuffer,uint32_t wRxSize) { uint16_t dummyTxBuffer[5]; _ILI9488DmaUpdateBuffer(dummyTxBuffer, wRxSize, pRxBuffer, wRxSize); SCB_CleanInvalidateDCache(); if (XDMAD_StartTransfer( ili9488Dma.xdmaD, ili9488Dma.ili9488DmaRxChannel)) return ILI9488_ERROR_DMA_TRANSFER; #if !defined(BOARD_LCD_SMC) if (XDMAD_StartTransfer( ili9488Dma.xdmaD, ili9488Dma.ili9488DmaTxChannel)) return ILI9488_ERROR_DMA_TRANSFER; #endif return 0; }
/** * \brief xDMA transfer PWM duty */ static void _PwmDmaTransfer(void) { sXdmadCfg xdmadCfg; uint32_t xdmaCndc; uint32_t i; for(i = 0; i < DUTY_BUFFER_LENGTH; i++){ dmaWriteLinkList[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 | XDMA_UBC_NDE_FETCH_EN | XDMA_UBC_NSEN_UPDATED | XDMAC_CUBC_UBLEN(1); dmaWriteLinkList[i].mbr_sa = (uint32_t)(&dwDutys[i]); dmaWriteLinkList[i].mbr_da = (uint32_t)(&(PWM0->PWM_DMAR)); if ( i == (DUTY_BUFFER_LENGTH - 1 )) { dmaWriteLinkList[i].mbr_nda = (uint32_t)&dmaWriteLinkList[0]; } else { dmaWriteLinkList[i].mbr_nda = (uint32_t)&dmaWriteLinkList[i+1]; } } xdmadCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | XDMAC_CC_MBSIZE_SINGLE | XDMAC_CC_DSYNC_MEM2PER | XDMAC_CC_CSIZE_CHK_1 | XDMAC_CC_DWIDTH_HALFWORD | XDMAC_CC_SIF_AHB_IF0 | XDMAC_CC_DIF_AHB_IF1 | XDMAC_CC_SAM_FIXED_AM | XDMAC_CC_DAM_FIXED_AM | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber(ID_PWM0, XDMAD_TRANSFER_TX )); xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1 | XDMAC_CNDC_NDE_DSCR_FETCH_EN | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED | XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED ; XDMAD_ConfigureTransfer( &dmad, pwmDmaTxChannel, &xdmadCfg, xdmaCndc, (uint32_t)&dmaWriteLinkList[0], XDMAC_CIE_LIE); SCB_CleanInvalidateDCache(); XDMAD_StartTransfer( &dmad, pwmDmaTxChannel); }
/** * \brief Configure the UART Tx DMA mode. * * \param pUartHw Pointer to UART instance * \param pXdmad Pointer to XDMA instance * \param pUsartTx Pointer to Usart Tx channel * \returns 0 if the dma multibuffer configuration successfully; otherwise returns * USARTD_ERROR_XXX. */ static uint8_t _configureUartTxDma(Uart *pUartHw, void *pXdmad, UartChannel *pUartTx) { sXdmadCfg xdmadTxCfg; uint32_t xdmaCndc, xdmaInt; uint32_t uartId, LLI_Size; uint8_t *pBuff = 0, i; if ((unsigned int)pUartHw == (unsigned int)UART0 ) uartId = ID_UART0; if ((unsigned int)pUartHw == (unsigned int)UART1 ) uartId = ID_UART1; if ((unsigned int)pUartHw == (unsigned int)UART2 ) uartId = ID_UART2; if ((unsigned int)pUartHw == (unsigned int)UART3 ) uartId = ID_UART3; if ((unsigned int)pUartHw == (unsigned int)UART4 ) uartId = ID_UART4; /* Setup TX */ if(pUartTx->dmaProgrammingMode < XDMAD_LLI) { xdmadTxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 | XDMA_UBC_NDE_FETCH_DIS| XDMA_UBC_NSEN_UPDATED | pUartTx->BuffSize; xdmadTxCfg.mbr_sa = (uint32_t)pUartTx->pBuff; xdmadTxCfg.mbr_da = (uint32_t)&pUartHw->UART_THR; xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | XDMAC_CC_MBSIZE_SINGLE | XDMAC_CC_DSYNC_MEM2PER | XDMAC_CC_CSIZE_CHK_1 | XDMAC_CC_DWIDTH_BYTE| XDMAC_CC_SIF_AHB_IF0 | XDMAC_CC_DIF_AHB_IF1 | XDMAC_CC_SAM_INCREMENTED_AM | XDMAC_CC_DAM_FIXED_AM | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( uartId, XDMAD_TRANSFER_TX )); xdmadTxCfg.mbr_bc = 0; xdmadTxCfg.mbr_sus = 0; xdmadTxCfg.mbr_dus =0; xdmaCndc = 0; xdmaInt = (XDMAC_CIE_BIE | XDMAC_CIE_DIE | XDMAC_CIE_FIE | XDMAC_CIE_RBIE | XDMAC_CIE_WBIE | XDMAC_CIE_ROIE); } if(pUartTx->dmaProgrammingMode == XDMAD_LLI) { LLI_Size = pUartTx->dmaLLI_Size; pBuff = pUartTx->pBuff; if(pLLIviewTx == NULL) { pLLIviewTx = malloc(sizeof(LinkedListDescriporView1)*LLI_Size); } xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | XDMAC_CC_MBSIZE_SINGLE | XDMAC_CC_DSYNC_MEM2PER | XDMAC_CC_MEMSET_NORMAL_MODE | XDMAC_CC_CSIZE_CHK_1 | XDMAC_CC_DWIDTH_BYTE | XDMAC_CC_SIF_AHB_IF0 | XDMAC_CC_DIF_AHB_IF1 | XDMAC_CC_SAM_INCREMENTED_AM | XDMAC_CC_DAM_FIXED_AM | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( uartId, XDMAD_TRANSFER_TX )); xdmadTxCfg.mbr_bc = 0; for (i = 0; i < LLI_Size; i++) { pLLIviewTx[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 | XDMA_UBC_NSEN_UPDATED | XDMA_UBC_NDEN_UNCHANGED | ((i== LLI_Size- 1)? ( (pUartTx->dmaRingBuffer)? XDMA_UBC_NDE_FETCH_EN : 0): XDMA_UBC_NDE_FETCH_EN) | pUartTx->BuffSize; pLLIviewTx[i].mbr_da = (uint32_t)&pUartHw->UART_THR; pLLIviewTx[i].mbr_sa = (uint32_t)pBuff; pLLIviewTx[i].mbr_nda = (i == ( LLI_Size - 1))? ( (pUartTx->dmaRingBuffer)? (uint32_t)&pLLIviewTx[ 0] : 0 ):(uint32_t)&pLLIviewTx[ i + 1 ]; pBuff += pUartTx->BuffSize; } xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1 | XDMAC_CNDC_NDE_DSCR_FETCH_EN | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED| XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED ; xdmaInt = ((pUartTx->dmaRingBuffer)? XDMAC_CIE_BIE : XDMAC_CIE_LIE); } if (XDMAD_ConfigureTransfer( pXdmad, pUartTx->ChNum, &xdmadTxCfg, xdmaCndc, (uint32_t)&pLLIviewTx[0], xdmaInt)) return USARTD_ERROR; SCB_CleanInvalidateDCache(); return 0; }
/** * \brief Receive and play audio with DMA. */ static void PlayRecording(void) { uint32_t src; uint8_t i; uint32_t xdmaCndc; src = 0x20440000; for(i = 0; i < TOTAL_Buffers; i++){ dmaReadLinkList[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 | XDMA_UBC_NDE_FETCH_EN | XDMA_UBC_NSEN_UPDATED | XDMAC_CUBC_UBLEN(0x1000); dmaReadLinkList[i].mbr_sa = (uint32_t)&(AUDIO_IF->SSC_RHR); dmaReadLinkList[i].mbr_da = (uint32_t)(src ); if ( i == (TOTAL_Buffers - 1)){ dmaReadLinkList[i].mbr_nda = (uint32_t)&dmaReadLinkList[0]; } else { dmaReadLinkList[i].mbr_nda = (uint32_t)&dmaReadLinkList[i + 1]; } src += (0x1000 * (BITS_BY_SLOT/8)); } xdmadCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | XDMAC_CC_MBSIZE_SINGLE | XDMAC_CC_DSYNC_PER2MEM | XDMAC_CC_CSIZE_CHK_1 | XDMAC_CC_DWIDTH_HALFWORD | XDMAC_CC_SIF_AHB_IF1 | XDMAC_CC_DIF_AHB_IF0 | XDMAC_CC_SAM_FIXED_AM | XDMAC_CC_DAM_INCREMENTED_AM | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber(ID_SSC, XDMAD_TRANSFER_RX )); xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1 | XDMAC_CNDC_NDE_DSCR_FETCH_EN | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED | XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED ; XDMAD_ConfigureTransfer( &dmad, sscDmaRxChannel, &xdmadCfg, xdmaCndc, (uint32_t)&dmaReadLinkList[0],XDMAC_CIE_LIE); SCB_CleanInvalidateDCache(); src = 0x20440000; for(i = 0; i < TOTAL_Buffers; i++){ dmaWriteLinkList[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 | XDMA_UBC_NDE_FETCH_EN | XDMA_UBC_NSEN_UPDATED | XDMAC_CUBC_UBLEN(0x1000); dmaWriteLinkList[i].mbr_sa = (uint32_t)(src ); dmaWriteLinkList[i].mbr_da = (uint32_t)&(AUDIO_IF->SSC_THR); if ( i == (TOTAL_Buffers - 1 )) { dmaWriteLinkList[i].mbr_nda = (uint32_t)&dmaWriteLinkList[0]; } else { dmaWriteLinkList[i].mbr_nda = (uint32_t)&dmaWriteLinkList[i+1]; } src += (0x1000 * (BITS_BY_SLOT/8)); } xdmadCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | XDMAC_CC_MBSIZE_SINGLE | XDMAC_CC_DSYNC_MEM2PER | XDMAC_CC_CSIZE_CHK_1 | XDMAC_CC_DWIDTH_HALFWORD | XDMAC_CC_SIF_AHB_IF0 | XDMAC_CC_DIF_AHB_IF1 | XDMAC_CC_SAM_INCREMENTED_AM | XDMAC_CC_DAM_FIXED_AM | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber(ID_SSC, XDMAD_TRANSFER_TX )); xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1 | XDMAC_CNDC_NDE_DSCR_FETCH_EN | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED | XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED ; XDMAD_ConfigureTransfer( &dmad, sscDmaTxChannel, &xdmadCfg, xdmaCndc, (uint32_t)&dmaWriteLinkList[0],XDMAC_CIE_LIE); SCB_CleanInvalidateDCache(); XDMAD_StartTransfer( &dmad, sscDmaRxChannel ); SSC_EnableReceiver(AUDIO_IF); Wait(3000); /* Enable playback(SSC TX) */ SCB_CleanInvalidateDCache(); XDMAD_StartTransfer( &dmad, sscDmaTxChannel); SSC_EnableTransmitter(AUDIO_IF); }