void __init sc8825_init_irq(void)
{
#ifdef CONFIG_NKERNEL
unsigned int val;
extern void nk_ddi_init(void);
nk_ddi_init();
#endif
gic_init(0, 29, (void __iomem *)SC8825_VA_GIC_DIS,
(void __iomem *)SC8825_VA_GIC_CPU);
gic_arch_extn.irq_eoi = sci_irq_eoi;
gic_arch_extn.irq_mask = sci_irq_mask;
gic_arch_extn.irq_unmask = sci_irq_unmask;
gic_arch_extn.irq_set_wake = sci_set_wake;
ana_init_irq();
#ifdef CONFIG_NKERNEL
/*
* gic clock will be stopped after 2 cores enter standby in the same time,
* dsp assert if IRQ_DSP0_INT and IRQ_DSP1_INT are disabled. so enable IRQ_DSP0_INT
* and IRQ_DSP1_INT in INTC0 here.
*/
val = __raw_readl(INTCV0_IRQ_EN);
val |= (SCI_INTC_IRQ_BIT(IRQ_DSP0_INT) | SCI_INTC_IRQ_BIT(IRQ_DSP1_INT) | SCI_INTC_IRQ_BIT(IRQ_EPT_INT));
val |= (SCI_INTC_IRQ_BIT(IRQ_SIM0_INT) | SCI_INTC_IRQ_BIT(IRQ_SIM1_INT) | SCI_INTC_IRQ_BIT(IRQ_SER1_INT));
val |= (SCI_INTC_IRQ_BIT(IRQ_TIMER0_INT));
__raw_writel(val, INTCV0_IRQ_EN);
/*disable legacy interrupt*/
__raw_writel(1<<31, SC8825_VA_GIC_DIS + 0x180);
__raw_writel(1<<28, SC8825_VA_GIC_DIS + 0x180);
#endif
}
static __init void __irq_init(void)
{
/*
* gic clock will be stopped after 2 cores enter standby in the same time,
* dsp assert if IRQ_DSP0_INT and IRQ_DSP1_INT are disabled. so enable IRQ_DSP0_INT
* and IRQ_DSP1_INT in INTC0 here.
*/
u32 val = __raw_readl(SPRD_INTC0_BASE + INTC_IRQ_EN);
val |= (SCI_INTC_IRQ_BIT(IRQ_DSP0_INT) | SCI_INTC_IRQ_BIT(IRQ_DSP1_INT) | SCI_INTC_IRQ_BIT(IRQ_EPT_INT));
val |= (SCI_INTC_IRQ_BIT(IRQ_SIM0_INT) | SCI_INTC_IRQ_BIT(IRQ_SIM1_INT));
val |= (SCI_INTC_IRQ_BIT(IRQ_TIMER0_INT));
__raw_writel(val, SPRD_INTC0_BASE + INTC_IRQ_EN);
}
/* chip sleep*/
int deep_sleep(void)
{
u32 val, ret = 0;
u32 holding;
wait_until_uart1_tx_done();
SAVE_GLOBAL_REG;
disable_audio_module();
disable_apb_module();
disable_ahb_module();
/* for dsp wake-up */
val = __raw_readl(INT0_IRQ_ENB);
val |= SCI_INTC_IRQ_BIT(IRQ_DSP0_INT);
val |= SCI_INTC_IRQ_BIT(IRQ_DSP1_INT);
__raw_writel(val, INT0_IRQ_ENB);
val = __raw_readl(INT0_FIQ_ENB);
val |= SCI_INTC_IRQ_BIT(IRQ_DSP0_INT);
val |= SCI_INTC_IRQ_BIT(IRQ_DSP1_INT);
__raw_writel(val, INT0_FIQ_ENB);
/* prevent uart1 */
__raw_writel(INT0_IRQ_MASK, INT0_IRQ_DIS);
/*L2X0_POWER_CTRL, auto_clock_gate, standby_mode_enable*/
__raw_writel(0x3, SPRD_L2_BASE+0xF80);
#ifdef FORCE_DISABLE_DSP
/* close debug modules, only for fpga or debug */
/*
dbg_module_close();
*/
dsp_and_modem_force_close();
#endif
/*
* pm_debug_set_wakeup_timer();
*/
/* FIXME: enable emc auto gate in final version
val = sci_glb_read(REG_AHB_AHB_CTL1, -1UL);
val |= AHB_CTRL1_EMC_AUTO_GATE_EN;
sci_glb_write(REG_AHB_AHB_CTL1, val, -1UL);
*/
/*go deepsleep when all PD auto poweroff en*/
val = sci_glb_read(REG_AHB_AHB_PAUSE, -1UL);
val &= ~( MCU_CORE_SLEEP | MCU_DEEP_SLEEP_EN | MCU_SYS_SLEEP_EN );
val |= (MCU_SYS_SLEEP_EN | MCU_DEEP_SLEEP_EN);
sci_glb_write(REG_AHB_AHB_PAUSE, val, -1UL);
/* set entry when deepsleep return*/
save_reset_vector();
set_reset_vector();
/* check globle key registers */
pm_debug_save_ahb_glb_regs( );
/* indicate cpu stopped */
holding = sci_glb_read(REG_AHB_HOLDING_PEN, -1UL);
sci_glb_write(REG_AHB_HOLDING_PEN, (holding | AP_ENTER_DEEP_SLEEP) , -1UL );
save_emc_trainig_data(repower_param);
ret = sp_pm_collapse(0, 1);
hard_irq_set();
/*clear dsp fiq, for dsp wakeup*/
__raw_writel(ICLR_DSP_FRQ0_CLR, SPRD_IPI_ICLR);
__raw_writel(ICLR_DSP_FIQ1_CLR, SPRD_IPI_ICLR);
/*disable dsp fiq*/
val = SCI_INTC_IRQ_BIT(IRQ_DSP0_INT) | SCI_INTC_IRQ_BIT(IRQ_DSP1_INT);
__raw_writel(val , INT0_FIQ_DIS);
/*clear the deep sleep status*/
sci_glb_write(REG_AHB_HOLDING_PEN, (holding & ~AP_ENTER_DEEP_SLEEP), -1UL );
/* FIXME: clear emc auto gate in final version
val = sci_glb_read(REG_AHB_AHB_CTL1, -1UL);
val &= ~AHB_CTRL1_EMC_AUTO_GATE_EN;
sci_glb_write(REG_AHB_AHB_CTL1, val, -1UL);
*/
restore_reset_vector();
RESTORE_GLOBAL_REG;
udelay(5);
if (ret) cpu_init();
return ret;
}