//*****************************************************************************
//
// Configures all pins associated with the Extended Peripheral Interface (EPI).
//
// \param eDaughter identifies the attached daughter board (if any).
//
// This function configures all pins forming part of the EPI on the device and
// configures the EPI peripheral appropriately for whichever hardware we
// detect is connected to it. On exit, the EPI peripheral is enabled and all
// pins associated with the interface are configured as EPI signals. Drive
// strength is set to 8mA.
//
//*****************************************************************************
static void
EPIPinConfigSet(tDaughterIDInfo *psInfo)
{
unsigned long ulLoop, ulClk, ulNsPerTick, ulRefresh;
unsigned char pucPins[NUM_GPIO_PORTS];
//
// Enable the EPI peripheral
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
//
// Clear our pin bit mask array.
//
for(ulLoop = 0; ulLoop < NUM_GPIO_PORTS; ulLoop++)
{
pucPins[ulLoop] = 0;
}
//
// Determine the pin bit masks for the EPI pins for each GPIO port.
//
for(ulLoop = 0; ulLoop < NUM_EPI_SIGNALS; ulLoop++)
{
//
// Is this EPI signal required?
//
if(psInfo->ulEPIPins & (1 << ulLoop))
{
//
// Yes - set the appropriate bit in our pin bit mask array.
//
pucPins[g_psEPIPinInfo[ulLoop].ucPortIndex] |=
(1 << g_psEPIPinInfo[ulLoop].ucPin);
}
}
//
// At this point, pucPins contains bit masks for each GPIO port with 1s in
// the positions of every required EPI signal. Now we need to configure
// those pins appropriately. Cycle through each port configuring EPI pins
// in any port which contains them.
//
for(ulLoop = 0; ulLoop < NUM_GPIO_PORTS; ulLoop++)
{
//
// Are there any EPI pins used in this port?
//
if(pucPins[ulLoop])
{
//
// Yes - configure the EPI pins.
//
GPIOPadConfigSet(g_pulGPIOBase[ulLoop], pucPins[ulLoop],
GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU);
GPIODirModeSet(g_pulGPIOBase[ulLoop], pucPins[ulLoop],
GPIO_DIR_MODE_HW);
}
}
//
// Now set the EPI operating mode for the daughter board detected. We need
// to determine some timing information based on the ID block we have and
// also the current system clock.
//
ulClk = SysCtlClockGet();
ulNsPerTick = 1000000000/ulClk;
//
// If the EPI is not disabled (the daughter board may, for example, want
// to use all the pins for GPIO), configure the interface as required.
//
if(psInfo->ucEPIMode != EPI_MODE_DISABLE)
{
//
// Set the EPI clock divider to ensure a basic EPI clock rate no faster
// than defined via the ucRate0nS and ucRate1nS fields in the info
// structure.
//
EPIDividerSet(EPI0_BASE, CalcEPIDivider(psInfo, ulNsPerTick));
//
// Set the basic EPI operating mode based on the value from the info
// structure.
//
EPIModeSet(EPI0_BASE, psInfo->ucEPIMode);
//
// Carry out mode-dependent configuration.
//
switch(psInfo->ucEPIMode)
{
//
// The daughter board must be configured for SDRAM operation.
//
case EPI_MODE_SDRAM:
{
//
// Work out the SDRAM configuration settings based on the
// supplied ID structure and system clock rate.
//
ulLoop = SDRAMConfigGet(psInfo, ulClk, &ulRefresh);
//
// Set the SDRAM configuration.
//
EPIConfigSDRAMSet(EPI0_BASE, ulLoop, ulRefresh);
break;
}
//
// The daughter board must be configured for HostBus8 operation.
//
case EPI_MODE_HB8:
{
//
// Determine the number of read and write wait states required
// to meet the supplied access timing.
//
ulLoop = HB8ConfigGet(psInfo);
//
// Set the HostBus8 configuration.
//
EPIConfigHB8Set(EPI0_BASE, ulLoop, psInfo->ucMaxWait);
break;
}
//
// The daughter board must be configured for Non-Moded/General
// Purpose operation.
//
case EPI_MODE_GENERAL:
{
EPIConfigGPModeSet(EPI0_BASE, psInfo->ulConfigFlags,
psInfo->ucFrameCount, psInfo->ucMaxWait);
break;
}
}
//
// Set the EPI address mapping.
//
EPIAddressMapSet(EPI0_BASE, psInfo->ucAddrMap);
}
}
//*****************************************************************************
//
// Configure EPI0 in SDRAM mode. The EPI memory space is setup using an a
// simple C array. This example shows how to read and write to an SDRAM card
// using the EPI bus in SDRAM mode.
//
//*****************************************************************************
void
sdram_init(void)
{
unsigned long ulClk, ulNsPerTick, ulConfig, ulRefresh;
//
// Display the setup on the console.
//
// UARTprintf("EPI SDRAM Mode ->\n");
// UARTprintf(" Type: SDRAM\n");
// UARTprintf(" Starting Address: 0x6000.0000\n");
// UARTprintf(" End Address: 0x603F.FFFF\n");
// UARTprintf(" Data: 16-bit\n");
// UARTprintf(" Size: 8MB (4Meg x 16bits)\n\n");
//
// The EPI0 peripheral must be enabled for use.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
//
// For this example EPI0 is used with multiple pins on PortC, E, F, G, H,
// and J. The actual port and pins used may be different on your part,
// consult the data sheet for more information.
// TODO: change this to whichever GPIO port you are using.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
//
// This step configures the internal pin muxes to set the EPI pins for use
// with EPI. This step is only required because the default function of
// these pins may not be to function in EPI mode. Please reference the
// datasheet for more information about pin muxing. Note that EPI0S27:20
// are not used for the EPI SDRAM implementation.
// TODO: change this to select the port/pin you are using.
//
GPIOPinConfigure(GPIO_PH3_EPI0S0);
GPIOPinConfigure(GPIO_PH2_EPI0S1);
GPIOPinConfigure(GPIO_PC4_EPI0S2);
GPIOPinConfigure(GPIO_PC5_EPI0S3);
GPIOPinConfigure(GPIO_PC6_EPI0S4);
GPIOPinConfigure(GPIO_PC7_EPI0S5);
GPIOPinConfigure(GPIO_PH0_EPI0S6);
GPIOPinConfigure(GPIO_PH1_EPI0S7);
GPIOPinConfigure(GPIO_PE0_EPI0S8);
GPIOPinConfigure(GPIO_PE1_EPI0S9);
GPIOPinConfigure(GPIO_PH4_EPI0S10);
GPIOPinConfigure(GPIO_PH5_EPI0S11);
GPIOPinConfigure(GPIO_PF4_EPI0S12);
GPIOPinConfigure(GPIO_PG0_EPI0S13);
GPIOPinConfigure(GPIO_PG1_EPI0S14);
GPIOPinConfigure(GPIO_PF5_EPI0S15);
GPIOPinConfigure(GPIO_PJ0_EPI0S16);
GPIOPinConfigure(GPIO_PJ1_EPI0S17);
GPIOPinConfigure(GPIO_PJ2_EPI0S18);
GPIOPinConfigure(GPIO_PJ3_EPI0S19);
GPIOPinConfigure(GPIO_PJ4_EPI0S28);
GPIOPinConfigure(GPIO_PJ5_EPI0S29);
GPIOPinConfigure(GPIO_PJ6_EPI0S30);
GPIOPinConfigure(GPIO_PG7_EPI0S31);
//
// Configure the GPIO pins for EPI mode. All the EPI pins require 8mA
// drive strength in push-pull operation. This step also gives control of
// pins to the EPI module.
// TODO: change this to select the port/pin you are using.
//
GPIOPinTypeEPI(GPIO_PORTC_BASE, EPI_PORTC_PINS);
GPIOPinTypeEPI(GPIO_PORTE_BASE, EPI_PORTE_PINS);
GPIOPinTypeEPI(GPIO_PORTF_BASE, EPI_PORTF_PINS);
GPIOPinTypeEPI(GPIO_PORTG_BASE, EPI_PORTG_PINS);
GPIOPinTypeEPI(GPIO_PORTH_BASE, EPI_PORTH_PINS);
GPIOPinTypeEPI(GPIO_PORTJ_BASE, EPI_PORTJ_PINS);
//
// Now set the EPI operating mode for the daughter board detected. We need
// to determine some timing information based on the ID block we have and
// also the current system clock.
//
ulClk = ROM_SysCtlClockGet();
ulNsPerTick = 1000000000 / ulClk;
//
// Set the EPI clock divider to ensure a basic EPI clock rate no faster
// than defined via the ucRate0nS and ucRate1nS fields in the info
// structure.
//
EPIDividerSet(EPI0_BASE, CalcEPIDivider(ulNsPerTick));
// //
// // Sets the clock divider for the EPI module. In this case set the
// // divider to 0, making the EPIClock = SysClk.
// //
// EPIDividerSet(EPI0_BASE, 0);
//
// Sets the usage mode of the EPI module. For this example we will use
// the SDRAM mode to talk to the external 8MB SDRAM daughter card.
//
EPIModeSet(EPI0_BASE, EPI_MODE_SDRAM);
//
// Configure the SDRAM mode. We configure the SDRAM according to our core
// clock frequency, in this case we are in the 15 MHz < clk <= 30 MHz
// range (i.e 16Mhz crystal). We will use the normal (or full power)
// operating state which means we will not use the low power self-refresh
// state. Set the SDRAM size to 8MB (or 64Mb) with a refresh counter of
// 1024 clock ticks.
// TODO: change this to select the proper clock frequency and SDRAM
// refresh counter.
//
ulRefresh = 0;
ulConfig = SDRAMConfigGet(ulClk, &ulRefresh);
EPIConfigSDRAMSet(EPI0_BASE, ulConfig | EPI_SDRAM_FULL_POWER | EPI_SDRAM_SIZE_64MBIT, 1024);
//
// Set the address map. The EPI0 is mapped from 0x60000000 to 0xCFFFFFFF.
// For this example, we will start from a base address of 0x60000000 with
// a size of 16MB. We use 16MB so we have the ability to access the
// entire 8MB SDRAM daughter card. Since there is no 8MB option, so we
// use the next closest one. If you attempt to access an address higher
// than 4Meg (since SDRAM mode uses 16-bit data, you have 4Meg of
// of addresses by 16-bits of data) a fault will not occur since we
// configured the EPI for 16MB addressability. In the case that you do
// access an address higher than 0x3FFFFF, the MSb of the address gets
// ignored.
//
EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_16MB | EPI_ADDR_RAM_BASE_6);
//
// Wait for the SDRAM wake-up to complete by polling the SDRAM
// initialization sequence bit. This bit is true when the SDRAM interface
// is going through the initialization and false when the SDRAM interface
// it is not in a wake-up period.
//
while(HWREG(EPI0_BASE + EPI_O_STAT) & EPI_STAT_INITSEQ)
{
}
}
