/*
* I2C support
*/
int
radeonfb_i2c_acquire_bus(void *cookie, int flags)
{
struct radeonfb_i2c *ric = (struct radeonfb_i2c *)cookie;
struct radeonfb_softc *sc = ric->ric_softc;
int i;
/*
* Some hardware seems to have hardware/software combined access
* to the DVI I2C. We want to use software.
*/
if (ric->ric_register == RADEON_GPIO_DVI_DDC) {
/* ask for software access to I2C bus */
SET32(sc, ric->ric_register, RADEON_GPIO_SW_USE);
/*
* wait for the chip to give up access. we don't make
* this a hard timeout, because some hardware might
* not implement this negotiation protocol
*/
for (i = RADEON_TIMEOUT; i; i--) {
if (GET32(sc, ric->ric_register) & RADEON_GPIO_SW_USE)
break;
}
}
/* enable the I2C clock */
SET32(sc, ric->ric_register, RADEON_GPIO_EN_1);
return 0;
}
/*
* audioixp_reset_port()
*
* Description:
* This routine resets the DMA engine pareparing it for work.
*
* Arguments:
* audioixp_port_t *port Port of DMA engine to reset.
*/
static void
audioixp_reset_port(audioixp_port_t *port)
{
audioixp_state_t *statep = port->statep;
ASSERT(mutex_owned(&statep->inst_lock));
/*
* XXX: reset counters.
*/
port->count = 0;
if (statep->suspended)
return;
/*
* Perform full reset of the engine, and enable its interrupts
* but leave it turned off.
*/
if (port->num == IXP_REC) {
PUT32(IXP_AUDIO_FIFO_FLUSH, IXP_AUDIO_FIFO_FLUSH_IN);
SET32(IXP_AUDIO_CMD, IXP_AUDIO_CMD_INTER_IN);
SET32(IXP_AUDIO_CMD, IXP_AUDIO_CMD_EN_IN_DMA);
PUT32(IXP_AUDIO_IN_DMA_LINK_P,
port->bdl_paddr | IXP_AUDIO_IN_DMA_LINK_P_EN);
} else {
uint32_t slot = GET32(IXP_AUDIO_OUT_DMA_SLOT_EN_THRESHOLD);
PUT32(IXP_AUDIO_FIFO_FLUSH, IXP_AUDIO_FIFO_FLUSH_OUT);
/* clear all slots */
slot &= ~ (IXP_AUDIO_OUT_DMA_SLOT_3 |
IXP_AUDIO_OUT_DMA_SLOT_4 |
IXP_AUDIO_OUT_DMA_SLOT_5 |
IXP_AUDIO_OUT_DMA_SLOT_6 |
IXP_AUDIO_OUT_DMA_SLOT_7 |
IXP_AUDIO_OUT_DMA_SLOT_8 |
IXP_AUDIO_OUT_DMA_SLOT_9 |
IXP_AUDIO_OUT_DMA_SLOT_10 |
IXP_AUDIO_OUT_DMA_SLOT_11 |
IXP_AUDIO_OUT_DMA_SLOT_12);
/* enable 6 channel out, unconditional for now */
slot |= IXP_AUDIO_OUT_DMA_SLOT_3 |
IXP_AUDIO_OUT_DMA_SLOT_4 |
IXP_AUDIO_OUT_DMA_SLOT_6 |
IXP_AUDIO_OUT_DMA_SLOT_9 |
IXP_AUDIO_OUT_DMA_SLOT_7 |
IXP_AUDIO_OUT_DMA_SLOT_8;
PUT32(IXP_AUDIO_OUT_DMA_SLOT_EN_THRESHOLD, slot);
SET32(IXP_AUDIO_CMD, IXP_AUDIO_CMD_INTER_OUT);
SET32(IXP_AUDIO_CMD, IXP_AUDIO_CMD_EN_OUT_DMA);
PUT32(IXP_AUDIO_OUT_DMA_LINK_P,
port->bdl_paddr | IXP_AUDIO_OUT_DMA_LINK_P_EN);
}
}
/*
* audio1575_stop()
*
* Description:
* This is called by the framework to stop a port that is
* transferring data.
*
* Arguments:
* void *arg The DMA engine to stop
*/
static void
audio1575_stop(void *arg)
{
audio1575_port_t *port = arg;
audio1575_state_t *statep = port->statep;
mutex_enter(&statep->lock);
if (port->num == M1575_REC) {
SET32(M1575_DMACR_REG, M1575_DMACR_PCMIPAUSE);
} else {
SET32(M1575_DMACR_REG, M1575_DMACR_PCMOPAUSE);
}
mutex_exit(&statep->lock);
}
//
// "Alpine" file loading
// Since the developers were coming after us with torches and pitchforks, we decided to
// allow this kind of thing. ;-) But ONLY FOR THE DEVS, DAMMIT! >:-U O_O
//
bool AlpineLoadFile(char * path)
{
uint8 * buffer = NULL;
jaguarROMSize = JaguarLoadROM(buffer, path);
if (jaguarROMSize == 0)
{
// It's up to the GUI to deal with failure, not us. ;-)
WriteLog("FILE: Could not load Alpine from file \"%s\"...\nAborting load!\n", path);
return false;
}
jaguarMainROMCRC32 = crc32_calcCheckSum(buffer, jaguarROMSize);
WriteLog("CRC: %08X\n", (unsigned int)jaguarMainROMCRC32);
EepromInit();
jaguarRunAddress = 0x802000;
WriteLog("FILE: Setting up Alpine ROM with non-standard length... Run address: 00802000, length: %08X\n", jaguarROMSize);
memset(jagMemSpace + 0x800000, 0xFF, 0x2000);
memcpy(jagMemSpace + 0x802000, buffer, jaguarROMSize);
delete[] buffer;
// Maybe instead of this, we could try requiring the STUBULATOR ROM? Just a thought...
// Try setting the vector to say, $1000 and putting an instruction there that loops forever:
// This kludge works! Yeah!
SET32(jaguarMainRAM, 0x10, 0x00001000); // Set Exception #4 (Illegal Instruction)
SET16(jaguarMainRAM, 0x1000, 0x60FE); // Here: bra Here
return true;
}
/*
* audioixp_start_port()
*
* Description:
* This routine starts the DMA engine.
*
* Arguments:
* audioixp_port_t *port Port of DMA engine to start.
*/
static void
audioixp_start_port(audioixp_port_t *port)
{
audioixp_state_t *statep = port->statep;
ASSERT(mutex_owned(&statep->inst_lock));
/* if suspended, then do nothing else */
if (statep->suspended) {
return;
}
if (port->num == IXP_REC) {
SET32(IXP_AUDIO_CMD, IXP_AUDIO_CMD_EN_IN);
} else {
SET32(IXP_AUDIO_CMD, IXP_AUDIO_CMD_EN_OUT);
}
}
void
radeonfb_i2c_release_bus(void *cookie, int flags)
{
struct radeonfb_i2c *ric = (struct radeonfb_i2c *)cookie;
struct radeonfb_softc *sc = ric->ric_softc;
if (ric->ric_register == RADEON_GPIO_DVI_DDC) {
/* we no longer "want" I2C, and we're "done" with it */
CLR32(sc, ric->ric_register, RADEON_GPIO_SW_USE);
SET32(sc, ric->ric_register, RADEON_GPIO_SW_DONE);
}
}
bool retro_load_game(const struct retro_game_info *info)
{
enum retro_pixel_format fmt = RETRO_PIXEL_FORMAT_XRGB8888;
if (!environ_cb(RETRO_ENVIRONMENT_SET_PIXEL_FORMAT, &fmt))
{
fprintf(stderr, "Pixel format XRGB8888 not supported by platform, cannot use.\n");
return false;
}
const char *full_path;
if(failed_init)
return false;
full_path = info->path;
vjs.renderType = 0;
check_variables();
jaguarCartInserted = true;
if (log_enabled)
{
bool success = (bool)LogInit("./virtualjaguar.log"); // Init logfile
if (!success)
printf("Failed to open virtualjaguar.log for writing!\n");
}
//strcpy(vjs.EEPROMPath, "/path/to/eeproms/"); // battery saves
JaguarInit(); // set up hardware
memcpy(jagMemSpace + 0xE00000, (vjs.biosType == BT_K_SERIES ? jaguarBootROM : jaguarBootROM2), 0x20000); // Use the stock BIOS
//memcpy(jagMemSpace + 0x800000, jaguarCDBootROM, 0x40000);
JaguarSetScreenPitch(videoWidth);
JaguarSetScreenBuffer(videoBuffer);
//Init video
for (int i = 0; i < videoWidth * videoHeight; ++i)
videoBuffer[i] = 0xFF00FFFF;
SET32(jaguarMainRAM, 0, 0x00200000); // set up stack
JaguarLoadFile((char *)full_path); // load rom
JaguarReset();
return true;
}
/*
* audioixp_reset_ac97()
*
* Description:
* Reset AC97 Codec register.
*
* Arguments:
* audioixp_state_t *state The device's state structure
*
* Returns:
* DDI_SUCCESS Reset the codec successfully
* DDI_FAILURE Failed to reset the codec
*/
static int
audioixp_reset_ac97(audioixp_state_t *statep)
{
uint32_t cmd;
int i;
CLR32(IXP_AUDIO_CMD, IXP_AUDIO_CMD_POWER_DOWN);
drv_usecwait(10);
/* register reset */
SET32(IXP_AUDIO_CMD, IXP_AUDIO_CMD_AC_SOFT_RESET);
/* force a read to flush caches */
(void) GET32(IXP_AUDIO_CMD);
drv_usecwait(10);
CLR32(IXP_AUDIO_CMD, IXP_AUDIO_CMD_AC_SOFT_RESET);
/* cold reset */
for (i = 0; i < 300; i++) {
cmd = GET32(IXP_AUDIO_CMD);
if (cmd & IXP_AUDIO_CMD_AC_ACTIVE) {
cmd |= IXP_AUDIO_CMD_AC_RESET | IXP_AUDIO_CMD_AC_SYNC;
PUT32(IXP_AUDIO_CMD, cmd);
return (DDI_SUCCESS);
}
cmd &= ~IXP_AUDIO_CMD_AC_RESET;
cmd |= IXP_AUDIO_CMD_AC_SYNC;
PUT32(IXP_AUDIO_CMD, cmd);
(void) GET32(IXP_AUDIO_CMD);
drv_usecwait(10);
cmd |= IXP_AUDIO_CMD_AC_RESET;
PUT32(IXP_AUDIO_CMD, cmd);
drv_usecwait(10);
}
audio_dev_warn(statep->adev, "AC'97 reset timed out");
return (DDI_FAILURE);
}
void Assembler::nFragExit(LInsp guard)
{
SideExit* exit = guard->record()->exit;
Fragment *frag = exit->target;
GuardRecord *lr;
if (frag && frag->fragEntry)
{
JMP(frag->fragEntry);
lr = 0;
}
else
{
// Target doesn't exit yet. Emit jump to epilog, and set up to patch later.
if (!_epilogue)
_epilogue = genEpilogue();
lr = guard->record();
JMP_long((intptr_t)_epilogue);
lr->jmp = _nIns;
}
// return value is GuardRecord*
SET32(int(lr), O0);
}
static void
do_query_reply(unsigned char code)
{
size_t len;
unsigned i;
const char *comma = "";
size_t obptr0 = obptr - obuf;
unsigned char *obptr_len;
unsigned short num, denom;
if (qr_in_progress) {
trace_ds("> StructuredField\n");
qr_in_progress = false;
}
space3270out(4);
obptr += 2; /* skip length for now */
*obptr++ = SFID_QREPLY;
*obptr++ = code;
switch (code) {
case QR_CHARSETS:
trace_ds("> QueryReply(CharacterSets)\n");
space3270out(64);
if (dbcs)
*obptr++ = 0x8e; /* flags: GE, CGCSGID, DBCS */
else
*obptr++ = 0x82; /* flags: GE, CGCSGID present */
*obptr++ = 0x00; /* more flags */
*obptr++ = char_width; /* SDW */
*obptr++ = char_height; /* SDW */
*obptr++ = 0x00; /* no load PS */
*obptr++ = 0x00;
*obptr++ = 0x00;
*obptr++ = 0x00;
if (dbcs)
*obptr++ = 0x0b; /* DL (11 bytes) */
else
*obptr++ = 0x07; /* DL (7 bytes) */
*obptr++ = 0x00; /* SET 0: */
if (dbcs)
*obptr++ = 0x00; /* FLAGS: non-load, single-
plane, single-bute */
else
*obptr++ = 0x10; /* FLAGS: non-loadable,
single-plane, single-byte,
no compare */
*obptr++ = 0x00; /* LCID 0 */
if (dbcs) {
*obptr++ = 0x00; /* SW 0 */
*obptr++ = 0x00; /* SH 0 */
*obptr++ = 0x00; /* SUBSN */
*obptr++ = 0x00; /* SUBSN */
}
SET32(obptr, cgcsgid); /* CGCSGID */
if (!standard_font) {
/* special 3270 font, includes APL */
*obptr++ = 0x01;/* SET 1: */
*obptr++ = 0x10;/* FLAGS: non-loadable, single-plane,
single-byte, no compare */
*obptr++ = 0xf1;/* LCID */
if (dbcs) {
*obptr++ = 0x00;/* SW 0 */
*obptr++ = 0x00;/* SH 0 */
*obptr++ = 0x00;/* SUBSN */
*obptr++ = 0x00;/* SUBSN */
}
*obptr++ = 0x03;/* CGCSGID: 3179-style APL2 */
*obptr++ = 0xc3;
*obptr++ = 0x01;
*obptr++ = 0x36;
}
if (dbcs) {
*obptr++ = 0x80; /* SET 0x80: */
*obptr++ = 0x20; /* FLAGS: DBCS */
*obptr++ = 0xf8; /* LCID: 0xf8 */
*obptr++ = char_width * 2; /* SW */
*obptr++ = char_height; /* SH */
*obptr++ = 0x41; /* SUBSN */
*obptr++ = 0x7f; /* SUBSN */
SET32(obptr, cgcsgid_dbcs); /* CGCSGID */
}
break;
case QR_IMP_PART:
trace_ds("> QueryReply(ImplicitPartition)\n");
space3270out(13);
*obptr++ = 0x0; /* reserved */
*obptr++ = 0x0;
*obptr++ = 0x0b; /* length of display size */
*obptr++ = 0x01; /* "implicit partition size" */
*obptr++ = 0x00; /* reserved */
SET16(obptr, 72); /* implicit partition width */
SET16(obptr, 66); /* implicit partition height */
SET16(obptr, maxCOLS); /* alternate height */
SET16(obptr, maxROWS); /* alternate width */
break;
case QR_NULL:
trace_ds("> QueryReply(Null)\n");
break;
case QR_SUMMARY:
trace_ds("> QueryReply(Summary(");
space3270out(NSR);
for (i = 0; i < NSR; i++) {
if (dbcs || supported_replies[i] != QR_DBCS_ASIA) {
trace_ds("%s%s", comma,
see_qcode(supported_replies[i]));
comma = ",";
*obptr++ = supported_replies[i];
}
}
trace_ds("))\n");
break;
case QR_USABLE_AREA:
trace_ds("> QueryReply(UsableArea)\n");
space3270out(19);
*obptr++ = 0x01; /* 12/14-bit addressing */
*obptr++ = 0x00; /* no special character features */
SET16(obptr, maxCOLS); /* usable width */
SET16(obptr, maxROWS); /* usable height */
*obptr++ = 0x01; /* units (mm) */
num = /*display_widthMM()*/ 8*5/4;
denom = /*display_width()*/ 7 * 72;
while (!(num %2) && !(denom % 2)) {
num /= 2;
denom /= 2;
}
SET16(obptr, (int)num); /* Xr numerator */
SET16(obptr, (int)denom); /* Xr denominator */
num = /*display_heightMM()*/ 11*5/4;
denom = /*display_height()*/ 9*66;
while (!(num %2) && !(denom % 2)) {
num /= 2;
denom /= 2;
}
SET16(obptr, (int)num); /* Yr numerator */
SET16(obptr, (int)denom); /* Yr denominator */
*obptr++ = char_width; /* AW */
*obptr++ = char_height; /* AH */
SET16(obptr, 0); /* buffer */
break;
case QR_COLOR:
trace_ds("> QueryReply(Color)\n");
space3270out(4 + 2*15);
*obptr++ = 0x00; /* no options */
*obptr++ = 16; /* report on 16 colors */
*obptr++ = 0x00; /* default color: */
*obptr++ = 0xf0 + HOST_COLOR_GREEN; /* green */
for (i = 0xf1; i <= 0xff; i++) {
*obptr++ = i;
*obptr++ = i;
}
break;
case QR_HIGHLIGHTING:
trace_ds("> QueryReply(Highlighting)\n");
space3270out(11);
*obptr++ = 5; /* report on 5 pairs */
*obptr++ = XAH_DEFAULT; /* default: */
*obptr++ = XAH_NORMAL; /* normal */
*obptr++ = XAH_BLINK; /* blink: */
*obptr++ = XAH_BLINK; /* blink */
*obptr++ = XAH_REVERSE; /* reverse: */
*obptr++ = XAH_REVERSE; /* reverse */
*obptr++ = XAH_UNDERSCORE; /* underscore: */
*obptr++ = XAH_UNDERSCORE; /* underscore */
*obptr++ = XAH_INTENSIFY; /* intensify: */
*obptr++ = XAH_INTENSIFY; /* intensify */
break;
case QR_REPLY_MODES:
trace_ds("> QueryReply(ReplyModes)\n");
space3270out(3);
*obptr++ = SF_SRM_FIELD;
*obptr++ = SF_SRM_XFIELD;
*obptr++ = SF_SRM_CHAR;
break;
case QR_DBCS_ASIA:
/* XXX: Should we support this, even when not in DBCS mode? */
trace_ds("> QueryReply(DbcsAsia)\n");
space3270out(7);
*obptr++ = 0x00; /* flags (none) */
*obptr++ = 0x03; /* field length 3 */
*obptr++ = 0x01; /* SI/SO supported */
*obptr++ = 0x80; /* character set ID 0x80 */
*obptr++ = 0x03; /* field length 3 */
*obptr++ = 0x02; /* input control */
*obptr++ = 0x01; /* creation supported */
break;
case QR_ALPHA_PART:
trace_ds("> QueryReply(AlphanumericPartitions)\n");
space3270out(4);
*obptr++ = 0; /* 1 partition */
SET16(obptr, maxROWS*maxCOLS); /* buffer space */
*obptr++ = 0; /* no special features */
break;
case QR_DDM:
trace_ds("> QueryReply(DistributedDataManagement)\n");
space3270out(8);
SET16(obptr,0); /* set reserved field to 0 */
SET16(obptr,2048); /* set inbound length limit */
SET16(obptr,2048); /* set outbound length limit */
SET16(obptr,0x0101); /* NSS=01, DDMSS=01 */
break;
default:
return; /* internal error */
}
obptr_len = obuf + obptr0;
len = (obptr - obuf) - obptr0;
SET16(obptr_len, len);
}
//
// Jaguar file loading
// We do a more intelligent file analysis here instead of relying on (possible false)
// file extensions which people don't seem to give two shits about anyway. :-(
//
bool JaguarLoadFile(char * path)
{
uint8 * buffer = NULL;
jaguarROMSize = JaguarLoadROM(buffer, path);
if (jaguarROMSize == 0)
{
// It's up to the GUI to report errors, not us. :-)
WriteLog("FILE: Could not load ROM from file \"%s\"...\nAborting load!\n", path);
return false;
}
jaguarMainROMCRC32 = crc32_calcCheckSum(buffer, jaguarROMSize);
WriteLog("CRC: %08X\n", (unsigned int)jaguarMainROMCRC32);
// TODO: Check for EEPROM file in ZIP file. If there is no EEPROM in the user's EEPROM
// directory, copy the one from the ZIP file, if it exists.
EepromInit();
jaguarRunAddress = 0x802000; // For non-BIOS runs, this is true
int fileType = ParseFileType(buffer, jaguarROMSize);
jaguarCartInserted = false;
if (fileType == JST_ROM)
{
jaguarCartInserted = true;
memcpy(jagMemSpace + 0x800000, buffer, jaguarROMSize);
// Checking something...
jaguarRunAddress = GET32(jagMemSpace, 0x800404);
WriteLog("FILE: Cartridge run address is reported as $%X...\n", jaguarRunAddress);
delete[] buffer;
return true;
}
else if (fileType == JST_ALPINE)
{
// File extension ".ROM": Alpine image that loads/runs at $802000
WriteLog("FILE: Setting up Alpine ROM... Run address: 00802000, length: %08X\n", jaguarROMSize);
memset(jagMemSpace + 0x800000, 0xFF, 0x2000);
memcpy(jagMemSpace + 0x802000, buffer, jaguarROMSize);
delete[] buffer;
// Maybe instead of this, we could try requiring the STUBULATOR ROM? Just a thought...
// Try setting the vector to say, $1000 and putting an instruction there that loops forever:
// This kludge works! Yeah!
SET32(jaguarMainRAM, 0x10, 0x00001000);
SET16(jaguarMainRAM, 0x1000, 0x60FE); // Here: bra Here
return true;
}
else if (fileType == JST_ABS_TYPE1)
{
// For ABS type 1, run address == load address
uint32 loadAddress = GET32(buffer, 0x16),
codeSize = GET32(buffer, 0x02) + GET32(buffer, 0x06);
WriteLog("FILE: Setting up homebrew (ABS-1)... Run address: %08X, length: %08X\n", loadAddress, codeSize);
memcpy(jagMemSpace + loadAddress, buffer + 0x24, codeSize);
delete[] buffer;
jaguarRunAddress = loadAddress;
return true;
}
else if (fileType == JST_ABS_TYPE2)
{
uint32 loadAddress = GET32(buffer, 0x28), runAddress = GET32(buffer, 0x24),
codeSize = GET32(buffer, 0x18) + GET32(buffer, 0x1C);
WriteLog("FILE: Setting up homebrew (ABS-2)... Run address: %08X, length: %08X\n", runAddress, codeSize);
memcpy(jagMemSpace + loadAddress, buffer + 0xA8, codeSize);
delete[] buffer;
jaguarRunAddress = runAddress;
return true;
}
// NB: This is *wrong*
/*
Basically, if there is no "JAG" at position $1C, then the long there is the load/start
address in LITTLE ENDIAN.
If "JAG" is present, the the next character ("R" or "L") determines the size of the
JagServer command (2 bytes vs. 4). Following that are the commands themselves;
typically it will either be 2 (load) or 3 (load & run). Command headers go like so:
2:
Load address (long)
Length (long)
payload
3:
Load address (long)
Length (long)
Run address (long)
payload
5: (Reset)
[command only]
7: (Run at address)
Run address (long)
[no payload]
9: (Clear memory)
Start address (long)
End address (long)
[no payload]
10: (Poll for commands)
[command only]
12: (Load & run user program)
filname, terminated with NULL
[no payload]
$FFFF: (Halt)
[no payload]
*/
else if (fileType == JST_JAGSERVER)
{
// This kind of shiaut should be in the detection code below...
// (and now it is! :-)
// if (buffer[0x1C] == 'J' && buffer[0x1D] == 'A' && buffer[0x1E] == 'G')
// {
// Still need to do some checking here for type 2 vs. type 3. This assumes 3
// Also, JAGR vs. JAGL (word command size vs. long command size)
uint32 loadAddress = GET32(buffer, 0x22), runAddress = GET32(buffer, 0x2A);
WriteLog("FILE: Setting up homebrew (Jag Server)... Run address: $%X, length: $%X\n", runAddress, jaguarROMSize - 0x2E);
memcpy(jagMemSpace + loadAddress, buffer + 0x2E, jaguarROMSize - 0x2E);
delete[] buffer;
jaguarRunAddress = runAddress;
return true;
// }
// else // Special WTFOMGBBQ type here...
// {
// uint32_t loadAddress = (buffer[0x1F] << 24) | (buffer[0x1E] << 16) | (buffer[0x1D] << 8) | buffer[0x1C];
// WriteLog("FILE: Setting up homebrew (GEMDOS WTFOMGBBQ type)... Run address: $%X, length: $%X\n", loadAddress, jaguarROMSize - 0x20);
// memcpy(jagMemSpace + loadAddress, buffer + 0x20, jaguarROMSize - 0x20);
// delete[] buffer;
// jaguarRunAddress = loadAddress;
// return true;
// }
}
else if (fileType == JST_WTFOMGBBQ)
{
uint32_t loadAddress = (buffer[0x1F] << 24) | (buffer[0x1E] << 16) | (buffer[0x1D] << 8) | buffer[0x1C];
WriteLog("FILE: Setting up homebrew (GEMDOS WTFOMGBBQ type)... Run address: $%X, length: $%X\n", loadAddress, jaguarROMSize - 0x20);
memcpy(jagMemSpace + loadAddress, buffer + 0x20, jaguarROMSize - 0x20);
delete[] buffer;
jaguarRunAddress = loadAddress;
return true;
}
// We can assume we have JST_NONE at this point. :-P
return false;
}
/*
* audio1575_start()
*
* Description:
* This is called by the framework to start a port transferring data.
*
* Arguments:
* void *arg The DMA engine to start
*
* Returns:
* 0 on success (never fails, errno if it did)
*/
static int
audio1575_start(void *arg)
{
audio1575_port_t *port = arg;
audio1575_state_t *statep = port->statep;
mutex_enter(&statep->lock);
port->offset = 0;
if (port->num == M1575_REC) {
/* Uli FIFO madness ... */
SET32(M1575_FIFOCR1_REG, M1575_FIFOCR1_PCMIRST);
SET32(M1575_DMACR_REG, M1575_DMACR_PCMIPAUSE);
PUT8(M1575_PCMICR_REG, 0);
PUT8(M1575_PCMICR_REG, M1575_CR_RR);
PUT32(M1575_PCMIBDBAR_REG, port->bdl_paddr);
PUT8(M1575_PCMILVIV_REG, M1575_BD_NUMS - 1);
CLR32(M1575_DMACR_REG, M1575_DMACR_PCMIPAUSE);
/* ULi says do fifo resets here */
SET32(M1575_FIFOCR1_REG, M1575_FIFOCR1_PCMIRST);
CLR32(M1575_DMACR_REG, M1575_DMACR_PCMIPAUSE);
PUT8(M1575_PCMICR_REG, 0);
SET32(M1575_DMACR_REG, M1575_DMACR_PCMISTART);
} else {
uint32_t scr;
/* Uli FIFO madness ... */
SET32(M1575_FIFOCR1_REG, M1575_FIFOCR1_PCMORST);
SET32(M1575_DMACR_REG, M1575_DMACR_PCMOPAUSE);
/* configure the number of channels properly */
scr = GET32(M1575_SCR_REG);
scr &= ~(M1575_SCR_6CHL_MASK | M1575_SCR_CHAMOD_MASK);
scr |= M1575_SCR_6CHL_2; /* select our proper ordering */
switch (port->nchan) {
case 2:
scr |= M1575_SCR_CHAMOD_2;
break;
case 4:
scr |= M1575_SCR_CHAMOD_4;
break;
case 6:
scr |= M1575_SCR_CHAMOD_6;
break;
}
PUT32(M1575_SCR_REG, scr);
PUT8(M1575_PCMOCR_REG, 0);
PUT8(M1575_PCMOCR_REG, M1575_CR_RR);
PUT32(M1575_PCMOBDBAR_REG, port->bdl_paddr);
PUT8(M1575_PCMOLVIV_REG, M1575_BD_NUMS - 1);
CLR32(M1575_DMACR_REG, M1575_DMACR_PCMOPAUSE);
PUT8(M1575_PCMOCR_REG, 0);
SET32(M1575_DMACR_REG, M1575_DMACR_PCMOSTART);
}
mutex_exit(&statep->lock);
return (0);
}
/*
* audio1575_dma_stop()
*
* Description:
* This routine is used to put each DMA engine into the quiet state.
*
* Arguments:
* audio1575_state_t *statep The device's state structure
*/
static void
audio1575_dma_stop(audio1575_state_t *statep, boolean_t quiesce)
{
uint32_t intrsr;
int i;
if (statep->regsh == NULL) {
return;
}
/* pause bus master (needed for the following reset register) */
for (i = 0; i < M1575_LOOP_CTR; i++) {
SET32(M1575_DMACR_REG, M1575_DMACR_PAUSE_ALL);
if (GET32(M1575_DMACR_REG) & M1575_DMACR_PAUSE_ALL) {
break;
}
drv_usecwait(10);
}
if (i >= M1575_LOOP_CTR) {
if (!quiesce)
audio_dev_warn(statep->adev, "failed to stop DMA");
return;
}
/* Pause bus master (needed for the following reset register) */
PUT8(M1575_PCMICR_REG, 0);
PUT8(M1575_PCMOCR_REG, 0);
PUT8(M1575_MICICR_REG, 0);
PUT8(M1575_CSPOCR_REG, 0);
PUT8(M1575_PCMI2CR_RR, 0);
PUT8(M1575_MICI2CR_RR, 0);
/* Reset the bus master registers for all DMA engines */
PUT8(M1575_PCMICR_REG, M1575_PCMICR_RR);
PUT8(M1575_PCMOCR_REG, M1575_PCMOCR_RR);
PUT8(M1575_MICICR_REG, M1575_MICICR_RR);
PUT8(M1575_CSPOCR_REG, M1575_CSPOCR_RR);
PUT8(M1575_PCMI2CR_REG, M1575_PCMI2CR_RR);
PUT8(M1575_MICI2CR_REG, M1575_MICI2CR_RR);
/* Reset FIFOS */
PUT32(M1575_FIFOCR1_REG, 0x81818181);
PUT32(M1575_FIFOCR2_REG, 0x81818181);
PUT32(M1575_FIFOCR3_REG, 0x81818181);
/* Clear Interrupts */
SET16(M1575_PCMISR_REG, M1575_SR_CLR);
SET16(M1575_PCMOSR_REG, M1575_SR_CLR);
SET16(M1575_MICISR_REG, M1575_SR_CLR);
SET16(M1575_CSPOSR_REG, M1575_SR_CLR);
SET16(M1575_PCMI2SR_REG, M1575_SR_CLR);
SET16(M1575_MICI2SR_REG, M1575_SR_CLR);
/*
* clear the interrupt control and status register
* READ/WRITE/READ workaround required to flush PCI caches
*/
PUT32(M1575_INTRCR_REG, 0);
(void) GET32(M1575_INTRCR_REG);
intrsr = GET32(M1575_INTRSR_REG);
PUT32(M1575_INTRSR_REG, (intrsr & M1575_INTR_MASK));
(void) GET32(M1575_INTRSR_REG);
}
/*
* audio1575_chip_init()
*
* Description:
* This routine initializes the M1575 AC97 audio controller and the AC97
* codec. The AC97 codec registers are programmed from codec_shadow[].
* If we are not doing a restore, we initialize codec_shadow[], otherwise
* we use the current values of shadow. This routine expects that the
* PCI IO and Memory spaces have been mapped and enabled already.
* Arguments:
* audio1575_state_t *state The device's state structure
* restore from codec_shadow[]
* Returns:
* DDI_SUCCESS The hardware was initialized properly
* DDI_FAILURE The hardware couldn't be initialized properly
*/
static int
audio1575_chip_init(audio1575_state_t *statep)
{
uint32_t ssr;
uint32_t rtsr;
uint32_t intrsr;
int i;
int j;
#ifdef __sparc
uint8_t clk_detect;
ddi_acc_handle_t pcih;
#endif
clock_t ticks;
/*
* clear the interrupt control and status register
* READ/WRITE/READ workaround required
* for buggy hardware
*/
PUT32(M1575_INTRCR_REG, 0);
(void) GET32(M1575_INTRCR_REG);
intrsr = GET32(M1575_INTRSR_REG);
PUT32(M1575_INTRSR_REG, (intrsr & M1575_INTR_MASK));
(void) GET32(M1575_INTRSR_REG);
ticks = drv_usectohz(M1575_LOOP_CTR);
/*
* SADA only supports stereo, so we set the channel bits
* to "00" to select 2 channels.
* will also set the following:
*
* Disable double rate enable
* no SPDIF output selected
* 16 bit audio record mode
* 16 bit pcm out mode
* PCM Out 6 chan mode FL FR CEN BL BR LFE
* PCM Out 2 channel mode (00)
*/
for (i = 0; i < M1575_LOOP_CTR; i++) {
/* Reset the AC97 Codec and default to 2 channel 16 bit mode */
PUT32(M1575_SCR_REG, M1575_SCR_COLDRST);
delay(ticks<<1);
/* Read the System Status Reg */
ssr = GET32(M1575_SSR_REG);
/* make sure and release the blocked reset bit */
if (ssr & M1575_SSR_RSTBLK) {
SET32(M1575_INTFCR_REG, M1575_INTFCR_RSTREL);
delay(ticks);
/* Read the System Status Reg */
ssr = GET32(M1575_SSR_REG);
/* make sure and release the blocked reset bit */
if (ssr & M1575_SSR_RSTBLK) {
return (DDI_FAILURE);
}
/* Reset the controller */
PUT32(M1575_SCR_REG, M1575_SCR_COLDRST);
delay(ticks);
}
/* according AC'97 spec, wait for codec reset */
for (j = 0; j < M1575_LOOP_CTR; j++) {
if ((GET32(M1575_SCR_REG) & M1575_SCR_COLDRST) == 0) {
break;
}
delay(ticks);
}
/* codec reset failed */
if (j >= M1575_LOOP_CTR) {
audio_dev_warn(statep->adev,
"failure to reset codec");
return (DDI_FAILURE);
}
/*
* Wait for FACRDY First codec ready. The hardware can
* provide the state of
* codec ready bit on SDATA_IN[0] and as reflected in
* the Recv Tag Slot Reg.
*/
rtsr = GET32(M1575_RTSR_REG);
if (rtsr & M1575_RTSR_FACRDY) {
break;
} else { /* reset the status and wait for new status to set */
rtsr |= M1575_RTSR_FACRDY;
PUT32(M1575_RTSR_REG, rtsr);
drv_usecwait(10);
}
}
/* if we could not reset the AC97 codec then report failure */
if (i >= M1575_LOOP_CTR) {
audio_dev_warn(statep->adev,
"no codec ready signal received");
return (DDI_FAILURE);
}
#ifdef __sparc
/* Magic code from ULi to Turn on the AC_LINK clock */
pcih = statep->pcih;
pci_config_put8(pcih, M1575_PCIACD_REG, 0);
pci_config_put8(pcih, M1575_PCIACD_REG, 4);
pci_config_put8(pcih, M1575_PCIACD_REG, 0);
(void) pci_config_get8(pcih, M1575_PCIACD_REG);
pci_config_put8(pcih, M1575_PCIACD_REG, 2);
pci_config_put8(pcih, M1575_PCIACD_REG, 0);
clk_detect = pci_config_get8(pcih, M1575_PCIACD_REG);
if (clk_detect != 1) {
audio_dev_warn(statep->adev, "No AC97 Clock Detected");
return (DDI_FAILURE);
}
#endif
/* Magic code from Uli to Init FIFO1 and FIFO2 */
PUT32(M1575_FIFOCR1_REG, 0x81818181);
PUT32(M1575_FIFOCR2_REG, 0x81818181);
PUT32(M1575_FIFOCR3_REG, 0x81818181);
/* Make sure that PCM in and PCM out are enabled */
SET32(M1575_INTFCR_REG, (M1575_INTFCR_PCMIENB | M1575_INTFCR_PCMOENB));
audio1575_dma_stop(statep, B_FALSE);
return (DDI_SUCCESS);
}
