void Osd::HwInit() { ZX_DEBUG_ASSERT(initialized_); // Setup VPP horizontal width WRITE32_REG(VPU, VPP_POSTBLEND_H_SIZE, display_width_); // init vpu fifo control register uint32_t regVal = READ32_REG(VPU, VPP_OFIFO_SIZE); regVal = 0xfff << 20; regVal |= (0xfff + 1); WRITE32_REG(VPU, VPP_OFIFO_SIZE, regVal); // init osd fifo control and set DDR request priority to be urgent regVal = 1; regVal |= 4 << 5; // hold_fifo_lines regVal |= 1 << 10; // burst_len_sel 3 = 64. This bit is split between 10 and 31 regVal |= 2 << 22; regVal |= 2 << 24; regVal |= 1 << 31; regVal |= 32 << 12; // fifo_depth_val: 32*8 = 256 WRITE32_REG(VPU, VPU_VIU_OSD1_FIFO_CTRL_STAT, regVal); WRITE32_REG(VPU, VPU_VIU_OSD2_FIFO_CTRL_STAT, regVal); SET_MASK32(VPU, VPP_MISC, VPP_POSTBLEND_EN); CLEAR_MASK32(VPU, VPP_MISC, VPP_PREBLEND_EN); // just disable osd to avoid booting hang up regVal = 0x1 << 0; regVal |= kOsdGlobalAlphaDef << 12; regVal |= (1 << 21); WRITE32_REG(VPU, VPU_VIU_OSD1_CTRL_STAT , regVal); WRITE32_REG(VPU, VPU_VIU_OSD2_CTRL_STAT , regVal); DefaultSetup(); EnableScaling(true); // Apply scale coefficients SET_BIT32(VPU, VPU_VPP_OSD_SCALE_COEF_IDX, 0x0000, 0, 9); for (int i = 0; i < 33; i++) { WRITE32_REG(VPU, VPU_VPP_OSD_SCALE_COEF, osd_filter_coefs_bicubic[i]); } SET_BIT32(VPU, VPU_VPP_OSD_SCALE_COEF_IDX, 0x0100, 0, 9); for (int i = 0; i < 33; i++) { WRITE32_REG(VPU, VPU_VPP_OSD_SCALE_COEF, osd_filter_coefs_bicubic[i]); } // update blending WRITE32_REG(VPU, VPU_VPP_OSD1_BLD_H_SCOPE, display_width_ - 1); WRITE32_REG(VPU, VPU_VPP_OSD1_BLD_V_SCOPE, display_height_ - 1); WRITE32_REG(VPU, VPU_VPP_OUT_H_V_SIZE, display_width_ << 16 | display_height_); }
void Interrupt::Enable(UINT interruptNum) { DistributorRegs* gicd = (DistributorRegs *)(this->baseRegAddr + (REALVIEW_PBA8_GIC_DIST_BASE - REALVIEW_PBA8_GIC_CPU_BASE)); UINT bitNum = 0; if(interruptNum >= IRQ_GIC_START && interruptNum <= IRQ_GIC_END){ if(interruptNum < (IRQ_GIC_START + WORDSIZE)){ bitNum = interruptNum - IRQ_GIC_START; SET_BIT32(&gicd->SetEnable1, bitNum); // SetEnable1 accept irq num 32-63 }else{ bitNum = interruptNum - (IRQ_GIC_START + WORDSIZE); SET_BIT32(&gicd->SetEnable2, bitNum); // SetEnable2 accept irq num 64-95 } } }
void Osd::EnableScaling(bool enable) { int hf_phase_step, vf_phase_step; int src_w, src_h, dst_w, dst_h; int bot_ini_phase; int vsc_ini_rcv_num, vsc_ini_rpt_p0_num; int hsc_ini_rcv_num, hsc_ini_rpt_p0_num; int hf_bank_len = 4; int vf_bank_len = 0; uint32_t data32 = 0x0; vf_bank_len = 4; hsc_ini_rcv_num = hf_bank_len; vsc_ini_rcv_num = vf_bank_len; hsc_ini_rpt_p0_num = (hf_bank_len / 2 - 1) > 0 ? (hf_bank_len / 2 - 1) : 0; vsc_ini_rpt_p0_num = (vf_bank_len / 2 - 1) > 0 ? (vf_bank_len / 2 - 1) : 0; src_w = fb_width_; src_h = fb_height_; dst_w = display_width_; dst_h = display_height_; data32 = 0x0; if (enable) { /* enable osd scaler */ data32 |= 1 << 2; /* enable osd scaler */ data32 |= 1 << 3; /* enable osd scaler path */ WRITE32_REG(VPU, VPU_VPP_OSD_SC_CTRL0, data32); } else { /* disable osd scaler path */ WRITE32_REG(VPU, VPU_VPP_OSD_SC_CTRL0, 0); } hf_phase_step = (src_w << 18) / dst_w; hf_phase_step = (hf_phase_step << 6); vf_phase_step = (src_h << 20) / dst_h; bot_ini_phase = 0; vf_phase_step = (vf_phase_step << 4); /* config osd scaler in/out hv size */ data32 = 0x0; if (enable) { data32 = (((src_h - 1) & 0x1fff) | ((src_w - 1) & 0x1fff) << 16); WRITE32_REG(VPU, VPU_VPP_OSD_SCI_WH_M1, data32); data32 = (((display_width_ - 1) & 0xfff)); WRITE32_REG(VPU, VPU_VPP_OSD_SCO_H_START_END, data32); data32 = (((display_height_ - 1) & 0xfff)); WRITE32_REG(VPU, VPU_VPP_OSD_SCO_V_START_END, data32); } data32 = 0x0; if (enable) { data32 |= (vf_bank_len & 0x7) | ((vsc_ini_rcv_num & 0xf) << 3) | ((vsc_ini_rpt_p0_num & 0x3) << 8); data32 |= 1 << 24; } WRITE32_REG(VPU, VPU_VPP_OSD_VSC_CTRL0, data32); data32 = 0x0; if (enable) { data32 |= (hf_bank_len & 0x7) | ((hsc_ini_rcv_num & 0xf) << 3) | ((hsc_ini_rpt_p0_num & 0x3) << 8); data32 |= 1 << 22; } WRITE32_REG(VPU, VPU_VPP_OSD_HSC_CTRL0, data32); data32 = 0x0; if (enable) { data32 |= (bot_ini_phase & 0xffff) << 16; SET_BIT32(VPU,VPU_VPP_OSD_HSC_PHASE_STEP, hf_phase_step, 0, 28); SET_BIT32(VPU,VPU_VPP_OSD_HSC_INI_PHASE, 0, 0, 16); SET_BIT32(VPU,VPU_VPP_OSD_VSC_PHASE_STEP, vf_phase_step, 0, 28); WRITE32_REG(VPU, VPU_VPP_OSD_VSC_INI_PHASE, data32); } }
void Osd::DefaultSetup() { // osd blend ctrl WRITE32_REG(VPU, VIU_OSD_BLEND_CTRL, 4 << 29| 0 << 27| // blend2_premult_en 1 << 26| // blend_din0 input to blend0 0 << 25| // blend1_dout to blend2 0 << 24| // blend1_din3 input to blend1 1 << 20| // blend_din_en 0 << 16| // din_premult_en 1 << 0); // din_reoder_sel = OSD1 // vpp osd1 blend ctrl WRITE32_REG(VPU, OSD1_BLEND_SRC_CTRL, (0 & 0xf) << 0 | (0 & 0x1) << 4 | (3 & 0xf) << 8 | // postbld_src3_sel (0 & 0x1) << 16| // postbld_osd1_premult (1 & 0x1) << 20); // vpp osd2 blend ctrl WRITE32_REG(VPU, OSD2_BLEND_SRC_CTRL, (0 & 0xf) << 0 | (0 & 0x1) << 4 | (0 & 0xf) << 8 | // postbld_src4_sel (0 & 0x1) << 16 | // postbld_osd2_premult (1 & 0x1) << 20); // used default dummy data WRITE32_REG(VPU, VIU_OSD_BLEND_DUMMY_DATA0, 0x0 << 16 | 0x0 << 8 | 0x0); // used default dummy alpha data WRITE32_REG(VPU, VIU_OSD_BLEND_DUMMY_ALPHA, 0x0 << 20 | 0x0 << 11 | 0x0); // osdx setting WRITE32_REG(VPU, VPU_VIU_OSD_BLEND_DIN0_SCOPE_H, (fb_width_ - 1) << 16); WRITE32_REG(VPU, VPU_VIU_OSD_BLEND_DIN0_SCOPE_V, (fb_height_ - 1) << 16); WRITE32_REG(VPU, VIU_OSD_BLEND_BLEND0_SIZE, fb_height_ << 16 | fb_width_); WRITE32_REG(VPU, VIU_OSD_BLEND_BLEND1_SIZE, fb_height_ << 16 | fb_width_); SET_BIT32(VPU, DOLBY_PATH_CTRL, 0x3, 2, 2); WRITE32_REG(VPU, VPP_OSD1_IN_SIZE, fb_height_ << 16 | fb_width_); // setting blend scope WRITE32_REG(VPU, VPP_OSD1_BLD_H_SCOPE, 0 << 16 | (fb_width_ - 1)); WRITE32_REG(VPU, VPP_OSD1_BLD_V_SCOPE, 0 << 16 | (fb_height_ - 1)); // Set geometry to normal mode uint32_t data32 = ((fb_width_ - 1) & 0xfff) << 16; WRITE32_REG(VPU, VPU_VIU_OSD1_BLK0_CFG_W3 , data32); data32 = ((fb_height_ - 1) & 0xfff) << 16; WRITE32_REG(VPU, VPU_VIU_OSD1_BLK0_CFG_W4, data32); WRITE32_REG(VPU, VPU_VIU_OSD1_BLK0_CFG_W1, ((fb_width_ - 1) & 0x1fff) << 16); WRITE32_REG(VPU, VPU_VIU_OSD1_BLK0_CFG_W2, ((fb_height_ - 1) & 0x1fff) << 16); // enable osd blk0 SET_BIT32(VPU, VPU_VIU_OSD1_CTRL_STAT, kHwOsdBlockEnable0, 0, 4); }