int s2650_execute(int cycles) { s2650_ICount = cycles; do { S.ppc = S.page + S.iar; S.ir = ROP(); s2650_ICount -= S2650_Cycles[S.ir]; S.r = S.ir & 3; /* register / value */ switch (S.ir) { case 0x00: /* LODZ,0 */ case 0x01: /* LODZ,1 */ case 0x02: /* LODZ,2 */ case 0x03: /* LODZ,3 */ M_LOD( R0, S.reg[S.r] ); break; case 0x04: /* LODI,0 v */ case 0x05: /* LODI,1 v */ case 0x06: /* LODI,2 v */ case 0x07: /* LODI,3 v */ M_LOD( S.reg[S.r], ARG() ); break; case 0x08: /* LODR,0 (*)a */ case 0x09: /* LODR,1 (*)a */ case 0x0a: /* LODR,2 (*)a */ case 0x0b: /* LODR,3 (*)a */ REL_EA( S.page ); M_LOD( S.reg[S.r], RDMEM(S.ea) ); break; case 0x0c: /* LODA,0 (*)a(,X) */ case 0x0d: /* LODA,1 (*)a(,X) */ case 0x0e: /* LODA,2 (*)a(,X) */ case 0x0f: /* LODA,3 (*)a(,X) */ ABS_EA(); M_LOD( S.reg[S.r], RDMEM(S.ea) ); break; case 0x10: /* illegal */ case 0x11: /* illegal */ break; case 0x12: /* SPSU */ M_SPSU(); break; case 0x13: /* SPSL */ M_SPSL(); break; case 0x14: /* RETC,0 (zero) */ case 0x15: /* RETC,1 (plus) */ case 0x16: /* RETC,2 (minus) */ M_RET( (S.psl >> 6) == S.r ); break; case 0x17: /* RETC,3 (always) */ M_RET( 1 ); break; case 0x18: /* BCTR,0 (*)a */ case 0x19: /* BCTR,1 (*)a */ case 0x1a: /* BCTR,2 (*)a */ M_BRR( (S.psl >> 6) == S.r ); break; case 0x1b: /* BCTR,3 (*)a */ M_BRR( 1 ); break; case 0x1c: /* BCTA,0 (*)a */ case 0x1d: /* BCTA,1 (*)a */ case 0x1e: /* BCTA,2 (*)a */ M_BRA( (S.psl >> 6) == S.r ); break; case 0x1f: /* BCTA,3 (*)a */ M_BRA( 1 ); break; case 0x20: /* EORZ,0 */ case 0x21: /* EORZ,1 */ case 0x22: /* EORZ,2 */ case 0x23: /* EORZ,3 */ M_EOR( R0, S.reg[S.r] ); break; case 0x24: /* EORI,0 v */ case 0x25: /* EORI,1 v */ case 0x26: /* EORI,2 v */ case 0x27: /* EORI,3 v */ M_EOR( S.reg[S.r], ARG() ); break; case 0x28: /* EORR,0 (*)a */ case 0x29: /* EORR,1 (*)a */ case 0x2a: /* EORR,2 (*)a */ case 0x2b: /* EORR,3 (*)a */ REL_EA( S.page ); M_EOR( S.reg[S.r], RDMEM(S.ea) ); break; case 0x2c: /* EORA,0 (*)a(,X) */ case 0x2d: /* EORA,1 (*)a(,X) */ case 0x2e: /* EORA,2 (*)a(,X) */ case 0x2f: /* EORA,3 (*)a(,X) */ ABS_EA(); M_EOR( S.reg[S.r], RDMEM(S.ea) ); break; case 0x30: /* REDC,0 */ case 0x31: /* REDC,1 */ case 0x32: /* REDC,2 */ case 0x33: /* REDC,3 */ S.reg[S.r] = cpu_readport(S2650_CTRL_PORT); SET_CC( S.reg[S.r] ); break; case 0x34: /* RETE,0 */ case 0x35: /* RETE,1 */ case 0x36: /* RETE,2 */ M_RETE( (S.psl >> 6) == S.r ); break; case 0x37: /* RETE,3 */ M_RETE( 1 ); break; case 0x38: /* BSTR,0 (*)a */ case 0x39: /* BSTR,1 (*)a */ case 0x3a: /* BSTR,2 (*)a */ M_BSR( (S.psl >> 6) == S.r ); break; case 0x3b: /* BSTR,R3 (*)a */ M_BSR( 1 ); break; case 0x3c: /* BSTA,0 (*)a */ case 0x3d: /* BSTA,1 (*)a */ case 0x3e: /* BSTA,2 (*)a */ M_BSA( (S.psl >> 6) == S.r ); break; case 0x3f: /* BSTA,3 (*)a */ M_BSA( 1 ); break; case 0x40: /* HALT */ S.iar = (S.iar - 1) & PMSK; S.halt = 1; if (s2650_ICount > 0) s2650_ICount = 0; break; case 0x41: /* ANDZ,1 */ case 0x42: /* ANDZ,2 */ case 0x43: /* ANDZ,3 */ M_AND( R0, S.reg[S.r] ); break; case 0x44: /* ANDI,0 v */ case 0x45: /* ANDI,1 v */ case 0x46: /* ANDI,2 v */ case 0x47: /* ANDI,3 v */ M_AND( S.reg[S.r], ARG() ); break; case 0x48: /* ANDR,0 (*)a */ case 0x49: /* ANDR,1 (*)a */ case 0x4a: /* ANDR,2 (*)a */ case 0x4b: /* ANDR,3 (*)a */ REL_EA( S.page ); M_AND( S.reg[S.r], RDMEM(S.ea) ); break; case 0x4c: /* ANDA,0 (*)a(,X) */ case 0x4d: /* ANDA,1 (*)a(,X) */ case 0x4e: /* ANDA,2 (*)a(,X) */ case 0x4f: /* ANDA,3 (*)a(,X) */ ABS_EA(); M_AND( S.reg[S.r], RDMEM(S.ea) ); break; case 0x50: /* RRR,0 */ case 0x51: /* RRR,1 */ case 0x52: /* RRR,2 */ case 0x53: /* RRR,3 */ M_RRR( S.reg[S.r] ); break; case 0x54: /* REDE,0 v */ case 0x55: /* REDE,1 v */ case 0x56: /* REDE,2 v */ case 0x57: /* REDE,3 v */ S.reg[S.r] = cpu_readport( ARG() ); SET_CC(S.reg[S.r]); break; case 0x58: /* BRNR,0 (*)a */ case 0x59: /* BRNR,1 (*)a */ case 0x5a: /* BRNR,2 (*)a */ case 0x5b: /* BRNR,3 (*)a */ M_BRR( S.reg[S.r] ); break; case 0x5c: /* BRNA,0 (*)a */ case 0x5d: /* BRNA,1 (*)a */ case 0x5e: /* BRNA,2 (*)a */ case 0x5f: /* BRNA,3 (*)a */ M_BRA( S.reg[S.r] ); break; case 0x60: /* IORZ,0 */ case 0x61: /* IORZ,1 */ case 0x62: /* IORZ,2 */ case 0x63: /* IORZ,3 */ M_IOR( R0, S.reg[S.r] ); break; case 0x64: /* IORI,0 v */ case 0x65: /* IORI,1 v */ case 0x66: /* IORI,2 v */ case 0x67: /* IORI,3 v */ M_IOR( S.reg[S.r], ARG() ); break; case 0x68: /* IORR,0 (*)a */ case 0x69: /* IORR,1 (*)a */ case 0x6a: /* IORR,2 (*)a */ case 0x6b: /* IORR,3 (*)a */ REL_EA( S.page ); M_IOR( S.reg[S. r],RDMEM(S.ea) ); break; case 0x6c: /* IORA,0 (*)a(,X) */ case 0x6d: /* IORA,1 (*)a(,X) */ case 0x6e: /* IORA,2 (*)a(,X) */ case 0x6f: /* IORA,3 (*)a(,X) */ ABS_EA(); M_IOR( S.reg[S.r], RDMEM(S.ea) ); break; case 0x70: /* REDD,0 */ case 0x71: /* REDD,1 */ case 0x72: /* REDD,2 */ case 0x73: /* REDD,3 */ S.reg[S.r] = cpu_readport(S2650_DATA_PORT); SET_CC(S.reg[S.r]); break; case 0x74: /* CPSU */ M_CPSU(); break; case 0x75: /* CPSL */ M_CPSL(); break; case 0x76: /* PPSU */ M_PPSU(); break; case 0x77: /* PPSL */ M_PPSL(); break; case 0x78: /* BSNR,0 (*)a */ case 0x79: /* BSNR,1 (*)a */ case 0x7a: /* BSNR,2 (*)a */ case 0x7b: /* BSNR,3 (*)a */ M_BSR( S.reg[S.r] ); break; case 0x7c: /* BSNA,0 (*)a */ case 0x7d: /* BSNA,1 (*)a */ case 0x7e: /* BSNA,2 (*)a */ case 0x7f: /* BSNA,3 (*)a */ M_BSA( S.reg[S.r] ); break; case 0x80: /* ADDZ,0 */ case 0x81: /* ADDZ,1 */ case 0x82: /* ADDZ,2 */ case 0x83: /* ADDZ,3 */ M_ADD( R0,S.reg[S.r] ); break; case 0x84: /* ADDI,0 v */ case 0x85: /* ADDI,1 v */ case 0x86: /* ADDI,2 v */ case 0x87: /* ADDI,3 v */ M_ADD( S.reg[S.r], ARG() ); break; case 0x88: /* ADDR,0 (*)a */ case 0x89: /* ADDR,1 (*)a */ case 0x8a: /* ADDR,2 (*)a */ case 0x8b: /* ADDR,3 (*)a */ REL_EA(S.page); M_ADD( S.reg[S.r], RDMEM(S.ea) ); break; case 0x8c: /* ADDA,0 (*)a(,X) */ case 0x8d: /* ADDA,1 (*)a(,X) */ case 0x8e: /* ADDA,2 (*)a(,X) */ case 0x8f: /* ADDA,3 (*)a(,X) */ ABS_EA(); M_ADD( S.reg[S.r], RDMEM(S.ea) ); break; case 0x90: /* illegal */ case 0x91: /* illegal */ break; case 0x92: /* LPSU */ S.psu = R0 & ~PSU34; break; case 0x93: /* LPSL */ /* change register set ? */ if ((S.psl ^ R0) & RS) SWAP_REGS; S.psl = R0; break; case 0x94: /* DAR,0 */ case 0x95: /* DAR,1 */ case 0x96: /* DAR,2 */ case 0x97: /* DAR,3 */ M_DAR( S.reg[S.r] ); break; case 0x98: /* BCFR,0 (*)a */ case 0x99: /* BCFR,1 (*)a */ case 0x9a: /* BCFR,2 (*)a */ M_BRR( (S.psl >> 6) != S.r ); break; case 0x9b: /* ZBRR (*)a */ M_ZBRR(); break; case 0x9c: /* BCFA,0 (*)a */ case 0x9d: /* BCFA,1 (*)a */ case 0x9e: /* BCFA,2 (*)a */ M_BRA( (S.psl >> 6) != S.r ); break; case 0x9f: /* BXA (*)a */ M_BXA(); break; case 0xa0: /* SUBZ,0 */ case 0xa1: /* SUBZ,1 */ case 0xa2: /* SUBZ,2 */ case 0xa3: /* SUBZ,3 */ M_SUB( R0, S.reg[S.r] ); break; case 0xa4: /* SUBI,0 v */ case 0xa5: /* SUBI,1 v */ case 0xa6: /* SUBI,2 v */ case 0xa7: /* SUBI,3 v */ M_SUB( S.reg[S.r], ARG() ); break; case 0xa8: /* SUBR,0 (*)a */ case 0xa9: /* SUBR,1 (*)a */ case 0xaa: /* SUBR,2 (*)a */ case 0xab: /* SUBR,3 (*)a */ REL_EA(S.page); M_SUB( S.reg[S.r], RDMEM(S.ea) ); break; case 0xac: /* SUBA,0 (*)a(,X) */ case 0xad: /* SUBA,1 (*)a(,X) */ case 0xae: /* SUBA,2 (*)a(,X) */ case 0xaf: /* SUBA,3 (*)a(,X) */ ABS_EA(); M_SUB( S.reg[S.r], RDMEM(S.ea) ); break; case 0xb0: /* WRTC,0 */ case 0xb1: /* WRTC,1 */ case 0xb2: /* WRTC,2 */ case 0xb3: /* WRTC,3 */ cpu_writeport(S2650_CTRL_PORT,S.reg[S.r]); break; case 0xb4: /* TPSU */ M_TPSU(); break; case 0xb5: /* TPSL */ M_TPSL(); break; case 0xb6: /* illegal */ case 0xb7: /* illegal */ break; case 0xb8: /* BSFR,0 (*)a */ case 0xb9: /* BSFR,1 (*)a */ case 0xba: /* BSFR,2 (*)a */ M_BSR( (S.psl >> 6) != S.r ); break; case 0xbb: /* ZBSR (*)a */ M_ZBSR(); break; case 0xbc: /* BSFA,0 (*)a */ case 0xbd: /* BSFA,1 (*)a */ case 0xbe: /* BSFA,2 (*)a */ M_BSA( (S.psl >> 6) != S.r ); break; case 0xbf: /* BSXA (*)a */ M_BSXA(); break; case 0xc0: /* NOP */ break; case 0xc1: /* STRZ,1 */ case 0xc2: /* STRZ,2 */ case 0xc3: /* STRZ,3 */ M_LOD( S.reg[S.r], R0 ); break; case 0xc4: /* illegal */ case 0xc5: /* illegal */ case 0xc6: /* illegal */ case 0xc7: /* illegal */ break; case 0xc8: /* STRR,0 (*)a */ case 0xc9: /* STRR,1 (*)a */ case 0xca: /* STRR,2 (*)a */ case 0xcb: /* STRR,3 (*)a */ REL_EA(S.page); M_STR( S.ea, S.reg[S.r] ); break; case 0xcc: /* STRA,0 (*)a(,X) */ case 0xcd: /* STRA,1 (*)a(,X) */ case 0xce: /* STRA,2 (*)a(,X) */ case 0xcf: /* STRA,3 (*)a(,X) */ ABS_EA(); M_STR( S.ea, S.reg[S.r] ); break; case 0xd0: /* RRL,0 */ case 0xd1: /* RRL,1 */ case 0xd2: /* RRL,2 */ case 0xd3: /* RRL,3 */ M_RRL( S.reg[S.r] ); break; case 0xd4: /* WRTE,0 v */ case 0xd5: /* WRTE,1 v */ case 0xd6: /* WRTE,2 v */ case 0xd7: /* WRTE,3 v */ cpu_writeport( ARG(), S.reg[S.r] ); break; case 0xd8: /* BIRR,0 (*)a */ case 0xd9: /* BIRR,1 (*)a */ case 0xda: /* BIRR,2 (*)a */ case 0xdb: /* BIRR,3 (*)a */ M_BRR( ++S.reg[S.r] ); break; case 0xdc: /* BIRA,0 (*)a */ case 0xdd: /* BIRA,1 (*)a */ case 0xde: /* BIRA,2 (*)a */ case 0xdf: /* BIRA,3 (*)a */ M_BRA( ++S.reg[S.r] ); break; case 0xe0: /* COMZ,0 */ case 0xe1: /* COMZ,1 */ case 0xe2: /* COMZ,2 */ case 0xe3: /* COMZ,3 */ M_COM( R0, S.reg[S.r] ); break; case 0xe4: /* COMI,0 v */ case 0xe5: /* COMI,1 v */ case 0xe6: /* COMI,2 v */ case 0xe7: /* COMI,3 v */ M_COM( S.reg[S.r], ARG() ); break; case 0xe8: /* COMR,0 (*)a */ case 0xe9: /* COMR,1 (*)a */ case 0xea: /* COMR,2 (*)a */ case 0xeb: /* COMR,3 (*)a */ REL_EA(S.page); M_COM( S.reg[S.r], RDMEM(S.ea) ); break; case 0xec: /* COMA,0 (*)a(,X) */ case 0xed: /* COMA,1 (*)a(,X) */ case 0xee: /* COMA,2 (*)a(,X) */ case 0xef: /* COMA,3 (*)a(,X) */ ABS_EA(); M_COM( S.reg[S.r], RDMEM(S.ea) ); break; case 0xf0: /* WRTD,0 */ case 0xf1: /* WRTD,1 */ case 0xf2: /* WRTD,2 */ case 0xf3: /* WRTD,3 */ cpu_writeport(S2650_DATA_PORT, S.reg[S.r]); break; case 0xf4: /* TMI,0 v */ case 0xf5: /* TMI,1 v */ case 0xf6: /* TMI,2 v */ case 0xf7: /* TMI,3 v */ M_TMI( S.reg[S.r] ); break; case 0xf8: /* BDRR,0 (*)a */ case 0xf9: /* BDRR,1 (*)a */ case 0xfa: /* BDRR,2 (*)a */ case 0xfb: /* BDRR,3 (*)a */ M_BRR( --S.reg[S.r] ); break; case 0xfc: /* BDRA,0 (*)a */ case 0xfd: /* BDRA,1 (*)a */ case 0xfe: /* BDRA,2 (*)a */ case 0xff: /* BDRA,3 (*)a */ M_BRA( --S.reg[S.r] ); break; } } while( s2650_ICount > 0 ); return cycles - s2650_ICount; }
// *********************************************************************** // *********************************************************************** // lc3 simulator task // // argc = 2 // argv[0] = 0 - load from system // 1 - load from FAT // int lc3Task(int argc, char* argv[]) { int DR, oldpc, ir; // local variables int i; int LC3_REGS[8]; // General purpose registers int LC3_CC = 0x02; // NZP condition codes int LC3_PC = 0x3000; // program counter int ips = 0; // instructions per swap // Initialize LC3 Simulator // clear registers for (i=0; i<8; i++) LC3_REGS[i] = 0; // set condition codes to nZp LC3_CC = 0x02; // load program if ((LC3_PC = loadLC3Program(argv)) < 0) return -1; // Execute LC3 program while(1) { oldpc = LC3_PC; // save old pc for debug message ir = getMemoryData(LC3_PC); // load ir and increment pc LC3_PC = LC3_PC + 1; // increment program counter DR = GET_DR; // preload destination register # switch(GET_OPCODE) { case LC3_ADD: // ADD instruction if (!GET_IMMEDIATE_BIT) { if (LC3_DEBUG&0x01) printf(ADD_MSG, oldpc, DR, GET_SR1, GET_SR2); LC3_REGS[DR] = MASKTO16BITS(LC3_REGS[GET_SR1] + LC3_REGS[GET_SR2]); } else { if (LC3_DEBUG&0x01) printf(ADDI_MSG, oldpc, DR, GET_SR1, MASKTO16BITS(SEXT5(ir))); LC3_REGS[DR] = MASKTO16BITS(LC3_REGS[GET_SR1] + SEXT5(ir)); } SET_CC(LC3_REGS[DR]); break; case LC3_AND: // AND instruction if (!GET_IMMEDIATE_BIT) { if (LC3_DEBUG&0x01) printf(AND_MSG, oldpc, DR, GET_SR1, GET_SR2); LC3_REGS[DR] = MASKTO16BITS(LC3_REGS[GET_SR1] & LC3_REGS[GET_SR2]); } else { if (LC3_DEBUG&0x01) printf(ANDI_MSG, oldpc, DR, GET_SR1, MASKTO16BITS(SEXT5(ir))); LC3_REGS[DR] = MASKTO16BITS(LC3_REGS[GET_SR1] & SEXT5(ir)); } SET_CC(LC3_REGS[DR]); break; case LC3_BR: // BR instruction if (ir == 0) { printf("\n**(%d) Illegal instruction 0x%04x at 0x%04x (frame %d)", LC3_TID, ir, LC3_PC, LC3_PC>>6); return -1; // abort! } if ((LC3_CC&0x04 && GET_N) || (LC3_CC&0x02 && GET_Z) || (LC3_CC&0x01 && GET_P)) LC3_PC = LC3_PC + SEXT9(ir); if (LC3_DEBUG&0x01) { char cchr[4]; cchr[0] = 0; if (GET_N) strcat(cchr, "N"); if (GET_Z) strcat(cchr, "Z"); if (GET_P) strcat(cchr, "P"); printf(BR_MSG, oldpc, cchr, LC3_PC); } break; case LC3_JMP: // JMP instruction if (LC3_DEBUG&0x01) { if (GET_BASER == 7) printf(RET_MSG, oldpc); else printf(JMP_MSG, oldpc, GET_BASER); } LC3_PC = LC3_REGS[GET_BASER]; break; case LC3_JSR: // JSR instruction LC3_REGS[7] = MASKTO16BITS(LC3_PC); if (GET_ADDR_BIT == 0) { if (LC3_DEBUG&0x01) printf(JSRR_MSG, oldpc, GET_BASER); LC3_PC = LC3_REGS[GET_BASER]; } else { if (LC3_DEBUG&0x01) printf(JSR_MSG, oldpc, LC3_PC + SEXT11(ir)); LC3_PC = LC3_PC + SEXT11(ir); } break; case LC3_LD: // LD instruction if (LC3_DEBUG&0x01) printf(LD_MSG, oldpc, DR, SEXT9(ir)); LC3_REGS[DR] = MASKTO16BITS(getMemoryData(LC3_PC + SEXT9(ir))); SET_CC(LC3_REGS[DR]); break; case LC3_LDI: // LDI instruction if (LC3_DEBUG&0x01) printf(LDI_MSG, oldpc, DR, SEXT9(ir)); LC3_REGS[DR] = MASKTO16BITS(getMemoryData(getMemoryData(LC3_PC + SEXT9(ir)))); SET_CC(LC3_REGS[DR]); break; case LC3_LDR: // LDR instruction if (LC3_DEBUG&0x01) printf(LDR_MSG, oldpc, DR, GET_BASER, SEXT6(ir)); LC3_REGS[DR] = MASKTO16BITS(getMemoryData(LC3_REGS[GET_BASER] + SEXT6(ir))); SET_CC(LC3_REGS[DR]); break; case LC3_LEA: // LEA instruction if (LC3_DEBUG&0x01) printf(LEA_MSG, oldpc, DR, LC3_PC + SEXT9(ir)); LC3_REGS[DR] = MASKTO16BITS(LC3_PC + SEXT9(ir)); SET_CC(LC3_REGS[DR]); break; case LC3_NOT: // NOT instruction if (LC3_DEBUG&0x01) printf(NOT_MSG, oldpc, DR, GET_SR1); LC3_REGS[DR] = MASKTO16BITS(~LC3_REGS[GET_SR1]); SET_CC(LC3_REGS[DR]); break; case LC3_ST: // ST instruction if (LC3_DEBUG&0x01) printf(ST_MSG, oldpc, GET_SR, LC3_PC + SEXT9(ir)); setMemoryData(LC3_PC + SEXT9(ir), LC3_REGS[GET_SR]); break; case LC3_STI: // STI instruction if (LC3_DEBUG&0x01) printf(STI_MSG, oldpc, GET_SR, SEXT9(ir)); setMemoryData(getMemoryData(LC3_PC + SEXT9(ir)), LC3_REGS[GET_SR]); break; case LC3_STR: // STR instruction if (LC3_DEBUG&0x01) printf(STR_MSG, oldpc, GET_SR, GET_BASER, SEXT6(ir)); setMemoryData(LC3_REGS[GET_BASER] + SEXT6(ir), LC3_REGS[GET_SR]); break; case LC3_TRAP: // TRAP instruction { int trapv = getMemoryData(GET_TRAPVECT8); // access trap vector getMemoryData(trapv); // access system routine switch(GET_TRAPVECT8) { int tmp, string_address; case LC3_GETID: { // Note: This function not supported by simulator. if (LC3_DEBUG&0x01) printf(TRAP_MSG, oldpc, "GETTID"); //printf("\nLC3_TID = %d (%d)", LC3_TID, curTask); LC3_REGS[0] = LC3_TID; LC3_REGS[7] = MASKTO16BITS(LC3_PC); break; } case LC3_GETC: { // Note: This does not function quite like GETC. if (LC3_DEBUG&0x01) printf(TRAP_MSG, oldpc, "GETC"); LC3_REGS[0] = MASKTO8BITS(getCharacter()); LC3_REGS[7] = MASKTO16BITS(LC3_PC); break; } case LC3_OUT: { if (LC3_DEBUG&0x01) printf(TRAP_MSG, oldpc, "OUT"); putchar(LC3_REGS[0]); LC3_REGS[7] = MASKTO16BITS(LC3_PC); break; } case LC3_PUTSP: { if (LC3_DEBUG&0x01) printf(TRAP_MSG, oldpc, "PUTSP"); putchar(' '); LC3_REGS[7] = MASKTO16BITS(LC3_PC); break; } case LC3_PUTS: { if (LC3_DEBUG&0x01) printf(TRAP_MSG, oldpc, "PUTS"); string_address = LC3_REGS[0]; while((tmp=getMemoryData(string_address++)) != 0) putchar(tmp); LC3_REGS[7] = MASKTO16BITS(LC3_PC); break; } case LC3_IN: { // Note: This does not function quite like IN. if (LC3_DEBUG&0x01) printf(TRAP_MSG, oldpc, "IN"); putchar(':'); LC3_REGS[0] = MASKTO8BITS(getCharacter()); LC3_REGS[7] = MASKTO16BITS(LC3_PC); break; } case LC3_HALT: { LC3_REGS[7] = MASKTO16BITS(LC3_PC); if (LC3_DEBUG&0x01) printf(TRAP_MSG, oldpc, "HALT"); printf("\nProcess #%d Halted at 0x%04x\n", LC3_TID, LC3_PC); charFlag = 0; // release input return 0; } case LC3_getNextDirEntry: { // Note: This function not supported by simulator. // IN: R0 = int *dirNum // R1 = char* mask // R2 = DirEntry* dirEntry // R3 = int cDir // OUT: R0 = 0-success, otherwise error if (LC3_DEBUG&0x01) printf(TRAP_MSG, oldpc, "fmsGetNextDirEntry"); LC3_REGS[0] = fmsGetNextDirEntry((int*)getMemAdr(LC3_REGS[0], 1), // int *dirNum (char*)getMemAdr(LC3_REGS[1], 0), // char* mask (DirEntry*)getMemAdr(LC3_REGS[2], 1), // DirEntry* dirEntry (short int)LC3_REGS[3]); // int cDir SWAP break; } case LC3_closeFile: { // Note: This function not supported by simulator. // IN: R0 = int fileDescriptor // OUT: R0 = 0-success, otherwise error if (LC3_DEBUG&0x01) printf(TRAP_MSG, oldpc, "fmsCloseFile"); LC3_REGS[0] = fmsCloseFile((short int)LC3_REGS[0]); // int fileDescriptor SWAP break; } case LC3_defineFile: { // Note: This function not supported by simulator. // IN: R0 = char* fileName // OUT: R0 = 0-success, otherwise error char fileName[32]; char* s = (char*)getMemAdr(LC3_REGS[0], 0); int j = i = 0; if(!s[j]) j++; while((fileName[i++] = s[j])) j+=2; if (LC3_DEBUG&0x01) printf(TRAP_MSG, oldpc, "fmsCreateFile"); LC3_REGS[0] = fmsDefineFile(fileName, 0); // char* fileName SWAP break; } case LC3_deleteFile: { // Note: This function not supported by simulator. // IN: R0 = char* fileName // OUT: R0 = 0-success, otherwise error char fileName[32]; char* s = (char*)getMemAdr(LC3_REGS[0], 0); int j = i = 0; if(!s[j]) j++; while((fileName[i++] = s[j])) j+=2; if (LC3_DEBUG&0x01) printf(TRAP_MSG, oldpc, "fmsDeleteFile"); LC3_REGS[0] = fmsDeleteFile(fileName); // char* fileName SWAP break; } case LC3_openFile: { // Note: This function not supported by simulator. // IN: R0 = char* fileName // R1 = int rwMode // OUT: R0 = 0-success, otherwise error char fileName[32]; char* s = (char*)getMemAdr(LC3_REGS[0], 0); int j = i = 0; if(!s[j]) j++; while((fileName[i++] = s[j])) j+=2; if (LC3_DEBUG&0x01) printf(TRAP_MSG, oldpc, "fmsOpenFile"); LC3_REGS[0] = fmsOpenFile(fileName, // char* fileName (short int)LC3_REGS[1]); // int rwMode SWAP break; } case LC3_readFile: { // Note: This function not supported by simulator. // IN: R0 = int fileDescriptor // R1 = char* buffer // R2 = int nBytes // OUT: R0 = 0-success, otherwise error if (LC3_DEBUG&0x01) printf(TRAP_MSG, oldpc, "fmsReadFile"); LC3_REGS[0] = fmsReadFile((short int)LC3_REGS[0], // int fileDescriptor (char*)getMemAdr(LC3_REGS[1], 0), // char* buffer (short int)LC3_REGS[2]); // int nBytes SWAP break; } case LC3_seekFile: { // Note: This function not supported by simulator. // IN: R0 = int fileDescriptor // R1 = int index // OUT: R0 = 0-success, otherwise error if (LC3_DEBUG&0x01) printf(TRAP_MSG, oldpc, "fmsSeekFile"); LC3_REGS[0] = fmsSeekFile((short int)LC3_REGS[0], // int fileDescriptor (short int)LC3_REGS[1]); // int index SWAP break; } case LC3_writeFile: { // Note: This function not supported by simulator. // IN: R0 = int fileDescriptor // R1 = char* buffer // R2 = int nBytes // OUT: R0 = 0-success, otherwise error if (LC3_DEBUG&0x01) printf(TRAP_MSG, oldpc, "fmsWriteFile"); LC3_REGS[0] = fmsWriteFile((short int)LC3_REGS[0], // int fileDescriptor (char*)getMemAdr(LC3_REGS[1], 0), // char* buffer (short int)LC3_REGS[2]); // int nBytes SWAP break; } default: printf(TRAP_ERROR_MSG, GET_TRAPVECT8); break; } break; } default: printf(UNDEFINED_OPCODE_MSG, GET_OPCODE); return -1; // abort! } if (LC3_DEBUG&0x02) // debug mode { char cchr[4]; // \n--PC:3000 IR:193b Nzp - 0000 0001 0002 0003 0004 0005 0006 0007 printf("\n--PC:%04x IR:%04x ",LC3_PC, ir); cchr[0] = (LC3_CC&0x04)?'N':'n'; cchr[1] = (LC3_CC&0x02)?'Z':'z'; cchr[2] = (LC3_CC&0x01)?'P':'p'; cchr[3] = 0; printf("%s -", &cchr[0]); for (i=0; i<8; i++) printf(" %04x", LC3_REGS[i]); //getchar(); // enable to single step } // swap tasks every INSTRUCTIONS_PER_SWAP instructions if (ips++ > INSTRUCTIONS_PER_SWAP) { ips = 0; SWAP }