/*-------------------------------------------------------------------*/
static REGS *copy_regs (REGS *regs)
{
REGS *newregs, *hostregs;
size_t size;
size = (SIE_MODE(regs) || SIE_ACTIVE(regs)) ? 2*sizeof(REGS) : sizeof(REGS);
newregs = malloc(size);
if (newregs == NULL)
{
logmsg(_("HHCMS001E malloc failed for REGS copy: %s\n"),
strerror(errno));
return NULL;
}
/* Perform partial copy and clear the TLB */
memcpy(newregs, regs, sysblk.regs_copy_len);
memset(&newregs->tlb.vaddr, 0, TLBN * sizeof(DW));
newregs->tlbID = 1;
newregs->ghostregs = 1;
newregs->hostregs = newregs;
newregs->guestregs = NULL;
newregs->sie_active=0;
/* Copy host regs if in SIE mode */
/* newregs is a SIE Guest REGS */
if(SIE_MODE(newregs))
{
hostregs = newregs + 1;
memcpy(hostregs, regs->hostregs, sysblk.regs_copy_len);
memset(&hostregs->tlb.vaddr, 0, TLBN * sizeof(DW));
hostregs->tlbID = 1;
hostregs->ghostregs = 1;
hostregs->hostregs = hostregs;
hostregs->guestregs = newregs;
newregs->hostregs = hostregs;
newregs->guestregs = newregs;
}
return newregs;
}
/*-------------------------------------------------------------------*/
static U16 ARCH_DEP(virt_to_abs) (RADR *raptr, int *siptr, VADR vaddr,
volatile int arn, REGS *regs, int acctype)
{
int icode;
if( !(icode = setjmp(regs->progjmp)) )
{
int temp_arn = arn; // bypass longjmp clobber warning
if (acctype == ACCTYPE_INSTFETCH)
temp_arn = USE_INST_SPACE;
if (SIE_MODE(regs))
memcpy(regs->hostregs->progjmp, regs->progjmp,
sizeof(jmp_buf));
ARCH_DEP(logical_to_main) (vaddr, temp_arn, regs, acctype, 0);
}
*siptr = regs->dat.stid;
*raptr = regs->hostregs->dat.raddr;
return icode;
} /* end function virt_to_abs */
/*-------------------------------------------------------------------*/
static void ARCH_DEP(external_interrupt) (int code, REGS *regs)
{
RADR pfx;
PSA *psa;
int rc;
PTT(PTT_CL_SIG,"*EXTINT",code,regs->cpuad,regs->psw.IA_L);
#if defined(_FEATURE_SIE)
/* Set the main storage reference and change bits */
if(SIE_MODE(regs)
#if defined(_FEATURE_EXPEDITED_SIE_SUBSET)
&& !SIE_FEATB(regs, S, EXP_TIMER)
#endif /*defined(_FEATURE_EXPEDITED_SIE_SUBSET)*/
#if defined(_FEATURE_EXTERNAL_INTERRUPT_ASSIST)
&& !SIE_FEATB(regs, EC0, EXTA)
#endif
)
{
/* Point to SIE copy of PSA in state descriptor */
psa = (void*)(regs->hostregs->mainstor + SIE_STATE(regs) + SIE_IP_PSA_OFFSET);
STORAGE_KEY(SIE_STATE(regs), regs->hostregs) |= (STORKEY_REF | STORKEY_CHANGE);
}
else
#endif /*defined(_FEATURE_SIE)*/
{
/* Point to PSA in main storage */
pfx = regs->PX;
#if defined(_FEATURE_EXPEDITED_SIE_SUBSET)
SIE_TRANSLATE(&pfx, ACCTYPE_SIE, regs);
#endif /*defined(_FEATURE_EXPEDITED_SIE_SUBSET)*/
psa = (void*)(regs->mainstor + pfx);
STORAGE_KEY(pfx, regs) |= (STORKEY_REF | STORKEY_CHANGE);
}
/* Store the interrupt code in the PSW */
regs->psw.intcode = code;
/* Zero extcpuad field unless extcall or ems signal or blockio */
if(code != EXT_EXTERNAL_CALL_INTERRUPT
#if defined(FEATURE_VM_BLOCKIO)
&& code != EXT_BLOCKIO_INTERRUPT
#endif /* defined(FEATURE_VM_BLOCKIO) */
&& code != EXT_EMERGENCY_SIGNAL_INTERRUPT)
STORE_HW(psa->extcpad,0);
#if defined(FEATURE_BCMODE)
/* For ECMODE, store external interrupt code at PSA+X'86' */
if ( ECMODE(®s->psw) )
#endif /*defined(FEATURE_BCMODE)*/
STORE_HW(psa->extint,code);
if ( !SIE_MODE(regs)
#if defined(_FEATURE_EXPEDITED_SIE_SUBSET)
|| SIE_FEATB(regs, S, EXP_TIMER)
#endif /*defined(_FEATURE_EXPEDITED_SIE_SUBSET)*/
#if defined(_FEATURE_EXTERNAL_INTERRUPT_ASSIST)
|| SIE_FEATB(regs, EC0, EXTA)
#endif
)
{
/* Store current PSW at PSA+X'18' */
ARCH_DEP(store_psw) (regs, psa->extold);
/* Load new PSW from PSA+X'58' */
rc = ARCH_DEP(load_psw) (regs, psa->extnew);
if ( rc )
{
RELEASE_INTLOCK(regs);
ARCH_DEP(program_interrupt)(regs, rc);
}
}
#if defined(FEATURE_INTERVAL_TIMER)
/* Ensure the interval timer is uptodate */
ARCH_DEP(store_int_timer_nolock) (regs);
#endif
RELEASE_INTLOCK(regs);
if ( SIE_MODE(regs)
#if defined(_FEATURE_EXPEDITED_SIE_SUBSET)
&& !SIE_FEATB(regs, S, EXP_TIMER)
#endif /*defined(_FEATURE_EXPEDITED_SIE_SUBSET)*/
#if defined(_FEATURE_EXTERNAL_INTERRUPT_ASSIST)
&& !SIE_FEATB(regs, EC0, EXTA)
#endif
)
longjmp (regs->progjmp, SIE_INTERCEPT_EXT);
else
longjmp (regs->progjmp, SIE_NO_INTERCEPT);
} /* end function external_interrupt */
/*-------------------------------------------------------------------*/
void ARCH_DEP(display_inst) (REGS *iregs, BYTE *inst)
{
QWORD qword; /* Doubleword work area */
BYTE opcode; /* Instruction operation code*/
int ilc; /* Instruction length */
#ifdef DISPLAY_INSTRUCTION_OPERANDS
int b1=-1, b2=-1, x1; /* Register numbers */
VADR addr1 = 0, addr2 = 0; /* Operand addresses */
#endif /*DISPLAY_INSTRUCTION_OPERANDS*/
char buf[256]; /* Message buffer */
int n; /* Number of bytes in buffer */
REGS *regs; /* Copied regs */
if (iregs->ghostregs)
regs = iregs;
else if ((regs = copy_regs(iregs)) == NULL)
return;
#if defined(_FEATURE_SIE)
if(SIE_MODE(regs))
logmsg(_("SIE: "));
#endif /*defined(_FEATURE_SIE)*/
#if 0
#if _GEN_ARCH == 370
logmsg("S/370 ");
#elif _GEN_ARCH == 390
logmsg("ESA/390 ");
#else
logmsg("Z/Arch ");
#endif
#endif
/* Display the PSW */
memset (qword, 0x00, sizeof(qword));
copy_psw (regs, qword);
if(sysblk.cpus>1)
{
n=sprintf(buf,"CPU%4.4X: ",regs->cpuad);
}
else
{
n=0;
}
n += sprintf (buf+n,
"PSW=%2.2X%2.2X%2.2X%2.2X %2.2X%2.2X%2.2X%2.2X ",
qword[0], qword[1], qword[2], qword[3],
qword[4], qword[5], qword[6], qword[7]);
#if defined(FEATURE_ESAME)
n += sprintf (buf + n,
"%2.2X%2.2X%2.2X%2.2X%2.2X%2.2X%2.2X%2.2X ",
qword[8], qword[9], qword[10], qword[11],
qword[12], qword[13], qword[14], qword[15]);
#endif /*defined(FEATURE_ESAME)*/
/* Exit if instruction is not valid */
if (inst == NULL)
{
logmsg (_("%sInstruction fetch error\n"), buf);
display_regs (regs);
if (!iregs->ghostregs) free(regs);
return;
}
/* Extract the opcode and determine the instruction length */
opcode = inst[0];
ilc = ILC(opcode);
/* Show registers associated with the instruction */
if (sysblk.showregsfirst)
display_inst_regs (regs, inst, opcode);
/* Display the instruction */
n += sprintf (buf+n, "INST=%2.2X%2.2X", inst[0], inst[1]);
if (ilc > 2) n += sprintf (buf+n, "%2.2X%2.2X", inst[2], inst[3]);
if (ilc > 4) n += sprintf (buf+n, "%2.2X%2.2X", inst[4], inst[5]);
logmsg ("%s %s", buf,(ilc<4) ? " " : (ilc<6) ? " " : "");
DISASM_INSTRUCTION(inst, buf);
logmsg("%s\n", buf);
#ifdef DISPLAY_INSTRUCTION_OPERANDS
/* Process the first storage operand */
if (ilc > 2
&& opcode != 0x84 && opcode != 0x85
&& opcode != 0xA5 && opcode != 0xA7
&& opcode != 0xB3
&& opcode != 0xC0 && opcode != 0xC4 && opcode != 0xC6
&& opcode != 0xEC)
{
/* Calculate the effective address of the first operand */
b1 = inst[2] >> 4;
addr1 = ((inst[2] & 0x0F) << 8) | inst[3];
if (b1 != 0)
{
addr1 += regs->GR(b1);
addr1 &= ADDRESS_MAXWRAP(regs);
}
/* Apply indexing for RX/RXE/RXF instructions */
if ((opcode >= 0x40 && opcode <= 0x7F) || opcode == 0xB1
|| opcode == 0xE3 || opcode == 0xED)
{
x1 = inst[1] & 0x0F;
if (x1 != 0)
{
addr1 += regs->GR(x1);
addr1 &= ADDRESS_MAXWRAP(regs);
}
}
}
/*-------------------------------------------------------------------*/
void ARCH_DEP(perform_external_interrupt) (REGS *regs)
{
PSA *psa; /* -> Prefixed storage area */
U16 cpuad; /* Originating CPU address */
#if defined(FEATURE_VM_BLOCKIO)
#if defined(FEATURE_ESAME)
RADR servpadr; /* Address of 64-bit block I/O interrupt */
#endif
U16 servcode; /* Service Signal or Block I/O Interrupt code */
#endif /* defined(FEATURE_VM_BLOCKIO) */
/* External interrupt if console interrupt key was depressed */
if ( OPEN_IC_INTKEY(regs) && !SIE_MODE(regs) )
{
WRMSG (HHC00840, "I");
/* Reset interrupt key pending */
OFF_IC_INTKEY;
/* Generate interrupt key interrupt */
ARCH_DEP(external_interrupt) (EXT_INTERRUPT_KEY_INTERRUPT, regs);
}
/* External interrupt if malfunction alert is pending */
if (OPEN_IC_MALFALT(regs))
{
/* Find first CPU which generated a malfunction alert */
for (cpuad = 0; regs->malfcpu[cpuad] == 0; cpuad++)
{
if (cpuad >= sysblk.maxcpu)
{
OFF_IC_MALFALT(regs);
return;
}
} /* end for(cpuad) */
// /*debug*/ logmsg (_("External interrupt: Malfuction Alert from CPU %d\n"),
// /*debug*/ cpuad);
/* Reset the indicator for the CPU which was found */
regs->malfcpu[cpuad] = 0;
/* Store originating CPU address at PSA+X'84' */
psa = (void*)(regs->mainstor + regs->PX);
STORE_HW(psa->extcpad,cpuad);
/* Reset emergency signal pending flag if there are
no other CPUs which generated emergency signal */
OFF_IC_MALFALT(regs);
while (++cpuad < sysblk.maxcpu)
{
if (regs->malfcpu[cpuad])
{
ON_IC_MALFALT(regs);
break;
}
} /* end while */
/* Generate emergency signal interrupt */
ARCH_DEP(external_interrupt) (EXT_MALFUNCTION_ALERT_INTERRUPT, regs);
}
/* External interrupt if emergency signal is pending */
if (OPEN_IC_EMERSIG(regs))
{
/* Find first CPU which generated an emergency signal */
for (cpuad = 0; regs->emercpu[cpuad] == 0; cpuad++)
{
if (cpuad >= sysblk.maxcpu)
{
OFF_IC_EMERSIG(regs);
return;
}
} /* end for(cpuad) */
// /*debug*/ logmsg (_("External interrupt: Emergency Signal from CPU %d\n"),
// /*debug*/ cpuad);
/* Reset the indicator for the CPU which was found */
regs->emercpu[cpuad] = 0;
/* Store originating CPU address at PSA+X'84' */
psa = (void*)(regs->mainstor + regs->PX);
STORE_HW(psa->extcpad,cpuad);
/* Reset emergency signal pending flag if there are
no other CPUs which generated emergency signal */
OFF_IC_EMERSIG(regs);
while (++cpuad < sysblk.maxcpu)
{
if (regs->emercpu[cpuad])
{
ON_IC_EMERSIG(regs);
break;
}
} /* end while */
/* Generate emergency signal interrupt */
ARCH_DEP(external_interrupt) (EXT_EMERGENCY_SIGNAL_INTERRUPT, regs);
}
/* External interrupt if external call is pending */
if (OPEN_IC_EXTCALL(regs))
{
// /*debug*/logmsg (_("External interrupt: External Call from CPU %d\n"),
// /*debug*/ regs->extccpu);
/* Reset external call pending */
OFF_IC_EXTCALL(regs);
/* Store originating CPU address at PSA+X'84' */
psa = (void*)(regs->mainstor + regs->PX);
STORE_HW(psa->extcpad,regs->extccpu);
/* Generate external call interrupt */
ARCH_DEP(external_interrupt) (EXT_EXTERNAL_CALL_INTERRUPT, regs);
}
/* External interrupt if TOD clock exceeds clock comparator */
if ( tod_clock(regs) > regs->clkc
&& OPEN_IC_CLKC(regs) )
{
if (CPU_STEPPING_OR_TRACING_ALL)
{
WRMSG (HHC00841, "I");
}
ARCH_DEP(external_interrupt) (EXT_CLOCK_COMPARATOR_INTERRUPT, regs);
}
/* External interrupt if CPU timer is negative */
if ( CPU_TIMER(regs) < 0
&& OPEN_IC_PTIMER(regs) )
{
if (CPU_STEPPING_OR_TRACING_ALL)
{
WRMSG (HHC00842, "I", CPU_TIMER(regs) << 8);
}
ARCH_DEP(external_interrupt) (EXT_CPU_TIMER_INTERRUPT, regs);
}
/* External interrupt if interval timer interrupt is pending */
#if defined(FEATURE_INTERVAL_TIMER)
if (OPEN_IC_ITIMER(regs)
#if defined(_FEATURE_SIE)
&& !(SIE_STATB(regs, M, ITMOF))
#endif /*defined(_FEATURE_SIE)*/
)
{
if (CPU_STEPPING_OR_TRACING_ALL)
{
WRMSG (HHC00843, "I");
}
OFF_IC_ITIMER(regs);
ARCH_DEP(external_interrupt) (EXT_INTERVAL_TIMER_INTERRUPT, regs);
}
#if defined(FEATURE_ECPSVM)
if ( OPEN_IC_ECPSVTIMER(regs) )
{
OFF_IC_ECPSVTIMER(regs);
ARCH_DEP(external_interrupt) (EXT_VINTERVAL_TIMER_INTERRUPT,regs);
}
#endif /*FEATURE_ECPSVM*/
#endif /*FEATURE_INTERVAL_TIMER*/
/* External interrupt if service signal is pending */
if ( OPEN_IC_SERVSIG(regs) && !SIE_MODE(regs) )
{
#if defined(FEATURE_VM_BLOCKIO)
/* Note: Both Block I/O and Service Signal are enabled by the */
/* the same CR0 bit. Hence they are handled in the same code */
switch(sysblk.servcode)
{
case EXT_BLOCKIO_INTERRUPT: /* VM Block I/O Interrupt */
if (sysblk.biodev->ccwtrace)
{
WRMSG (HHC00844, "I",
SSID_TO_LCSS(sysblk.biodev->ssid),
sysblk.biodev->devnum,
sysblk.servcode,
sysblk.bioparm,
sysblk.biostat,
sysblk.biosubcd
);
}
servcode = EXT_BLOCKIO_INTERRUPT;
#if defined(FEATURE_ESAME)
/* Real address used to store the 64-bit interrupt parameter */
#define VM_BLOCKIO_INT_PARM 0x11B8
if (sysblk.biosubcd == 0x07)
{
/* 8-byte interrupt parm */
if (CPU_STEPPING_OR_TRACING_ALL)
{
char buf[40];
MSGBUF(buf, "%16.16X", (unsigned) sysblk.bioparm);
WRMSG (HHC00845,"I", buf);
}
/* Set the main storage reference and change bits */
/* for 64-bit interruption parameter. */
/* Note: This is handled for the first 4K page in */
/* ARCH_DEP(external_interrupt), but not for the */
/* the second 4K page used for the 64-bit interrupt */
/* parameter. */
/* Point to 2nd page of PSA in main storage */
servpadr=APPLY_PREFIXING(VM_BLOCKIO_INT_PARM,regs->PX);
STORAGE_KEY(servpadr, regs)
|= (STORKEY_REF | STORKEY_CHANGE);
#if 0
/* Store the 64-bit interrupt parameter */
logmsg (_("Saving 64-bit Block I/O interrupt parm at "
"%16.16X: %16.16X\n"),
servpadr,
sysblk.bioparm
);
#endif
STORE_DW(regs->mainstor + servpadr,sysblk.bioparm);
psa = (void*)(regs->mainstor + regs->PX);
}
else
{
#endif /* defined(FEATURE_ESAME) */
/* 4-byte interrupt parm */
if (CPU_STEPPING_OR_TRACING_ALL)
{
char buf[40];
MSGBUF(buf, "%8.8X", (U32) sysblk.bioparm);
WRMSG (HHC00845,"I", buf);
}
/* Store Block I/O parameter at PSA+X'80' */
psa = (void*)(regs->mainstor + regs->PX);
STORE_FW(psa->extparm,(U32)sysblk.bioparm);
#if defined(FEATURE_ESAME)
}
#endif
/* Store sub-interruption code and status at PSA+X'84' */
STORE_HW(psa->extcpad,(sysblk.biosubcd<<8)|sysblk.biostat);
/* Reset interruption data */
sysblk.bioparm = 0;
sysblk.biosubcd = 0;
sysblk.biostat = 0;
break;
case EXT_SERVICE_SIGNAL_INTERRUPT: /* Service Signal */
default:
servcode = EXT_SERVICE_SIGNAL_INTERRUPT;
/* Apply prefixing if the parameter is a storage address */
if ( (sysblk.servparm & SERVSIG_ADDR) )
sysblk.servparm =
APPLY_PREFIXING (sysblk.servparm, regs->PX);
if (CPU_STEPPING_OR_TRACING_ALL)
{
WRMSG (HHC00846,"I", sysblk.servparm);
}
/* Store service signal parameter at PSA+X'80' */
psa = (void*)(regs->mainstor + regs->PX);
STORE_FW(psa->extparm,sysblk.servparm);
} /* end switch(sysblk.servcode) */
/* Reset service parameter */
sysblk.servparm = 0;
/* Reset service code */
sysblk.servcode = 0;
/* Reset service signal pending */
OFF_IC_SERVSIG;
/* Generate service signal interrupt */
ARCH_DEP(external_interrupt) (servcode, regs);
#else /* defined(FEATURE_VM_BLOCKIO) */
/* Apply prefixing if the parameter is a storage address */
if ( (sysblk.servparm & SERVSIG_ADDR) )
sysblk.servparm =
APPLY_PREFIXING (sysblk.servparm, regs->PX);
if (CPU_STEPPING_OR_TRACING_ALL)
{
WRMSG (HHC00846,"I", sysblk.servparm);
}
/* Store service signal parameter at PSA+X'80' */
psa = (void*)(regs->mainstor + regs->PX);
STORE_FW(psa->extparm,sysblk.servparm);
/* Reset service parameter */
sysblk.servparm = 0;
/* Reset service signal pending */
OFF_IC_SERVSIG;
/* Generate service signal interrupt */
ARCH_DEP(external_interrupt) (EXT_SERVICE_SIGNAL_INTERRUPT, regs);
#endif /* defined(FEATURE_VM_BLOCKIO) */
} /* end OPEN_IC_SERVSIG(regs) */
} /* end function perform_external_interrupt */