void enter_vlls1(void)
{
volatile unsigned int dummyread;
SMC_PMPROT = SMC_PMPROT_AVLLS_MASK;
/* Write to PMPROT to allow all possible power modes */
/* Set the STOPM field to 0b100 for VLLS1 mode */
SMC_PMCTRL &= ~SMC_PMCTRL_STOPM_MASK;
SMC_PMCTRL |= SMC_PMCTRL_STOPM(0x4);
/* set VLLSM = 0b01 */
SMC_STOPCTRL = SMC_STOPCTRL_VLLSM(1);
/*wait for write to complete to SMC before stopping core */
dummyread = SMC_STOPCTRL;
dummyread++;
SCB_SCR |= SCB_SCR_SLEEPDEEP_MASK;
__wfi();
/* Now execute the stop instruction to go into VLLS1 */
// #ifdef CMSIS
// /* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */
// SCB_SCR |= SCB_SCR_SLEEPDEEP_MASK;
// __wfi();
//#else
// stop();
//#endif
}
void enter_vlls0_nopor(void)
{
volatile unsigned int dummyread;
int i;
/* Write to PMPROT to allow all possible power modes */
SMC_PMPROT = SMC_PMPROT_AVLLS_MASK;
if ((SMC_PMSTAT & SMC_PMSTAT_PMSTAT_MASK)== 4){
SMC_PMCTRL &= ~SMC_PMCTRL_RUNM_MASK; // go back to RUN mode temporarily
for (i=0;i<0xff;i++)
{
if ((SMC_PMSTAT & SMC_PMSTAT_PMSTAT_MASK)== 1)
break;
}
}
/* Set the STOPM field to 0b100 for VLLS0 mode */
SMC_PMCTRL &= ~SMC_PMCTRL_STOPM_MASK;
SMC_PMCTRL |= SMC_PMCTRL_STOPM(0x4);
/* set VLLSM = 00 * and PORPO = 1 */
SMC_STOPCTRL &= ~SMC_STOPCTRL_VLLSM_MASK;
SMC_STOPCTRL = SMC_STOPCTRL_VLLSM(0) | SMC_STOPCTRL_PORPO_MASK;
/*wait for write to complete to SMC before stopping core */
dummyread = SMC_STOPCTRL;
dummyread = dummyread + 1;
/* Now execute the stop instruction to go into VLLS0 */
#ifdef CMSIS
/* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */
SCB_SCR |= SCB_SCR_SLEEPDEEP_MASK;
__wfi();
#else
stop();
#endif
}
inline void _stop( void ) {
// Set the STOPM field to 0b000 for normal STOP mode - Need to
// retain state of LPWUI bit 8
SMC_PMCTRL = SMC_PMCTRL_STOPM( 0x00 );// set STOPM = 0b000
( void ) SMC_PMCTRL;
stop( );
}
void enter_vlps(void)
{
volatile unsigned int dummyread;
/* The PMPROT register may have already been written by init code
If so then this next write is not done since
PMPROT is write once after RESET
allows the MCU to enter the VLPR, VLPW, and VLPS modes.
If AVLP is already writen to 0
Stop is entered instead of VLPS*/
SMC_PMPROT = SMC_PMPROT_AVLP_MASK;
/* Set the STOPM field to 0b010 for VLPS mode */
SMC_PMCTRL &= ~SMC_PMCTRL_STOPM_MASK;
SMC_PMCTRL |= SMC_PMCTRL_STOPM(0x2);
/*wait for write to complete to SMC before stopping core */
dummyread = SMC_PMCTRL;
dummyread = dummyread + 1;
/* Now execute the stop instruction to go into VLPS */
#ifdef CMSIS
/* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */
SCB_SCR |= SCB_SCR_SLEEPDEEP_MASK;
__wfi();
#else
stop();
#endif
}
/* STOP mode entry routine. Puts the processor into normal stop mode.
* In this mode core, bus and peripheral clocks are disabled.
*
* Mode transitions:
* RUN -> STOP
*
* This function can be used to enter normal stop mode.
* If you are executing in normal run mode when calling this
* function and AVLP = 0, then you will enter normal stop mode.
* If AVLP = 1 with previous write to PMPROT
* then you will enter VLPS mode instead.
*
* STOP mode is exited using any enabled interrupt or RESET, so no
* exit_stop routine is needed.
*
* Parameters:
* Partial Stop Option:
* 0x00 = STOP - Normal Stop Mode
* 0x40 = PSTOP1 - Partial Stop with both system and bus clocks disabled
* 0x80 = PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
* 0xC0 = Reserved
*/
void enter_stop(unsigned char partial_stop_opt)
{
volatile unsigned int dummyread;
/* The PMPROT register may have already been written by init code
If so then this next write is not done since
PMPROT is write once after RESET
this write-once bit allows the MCU to enter the
normal STOP mode.
If AVLP is already a 1, VLPS mode is entered instead of normal STOP*/
SMC_PMPROT = 0;
/* Set the STOPM field to 0b000 for normal STOP mode */
SMC_PMCTRL &= ~SMC_PMCTRL_STOPM_MASK;
SMC_PMCTRL |= SMC_PMCTRL_STOPM(0);
SMC_STOPCTRL &= ~SMC_STOPCTRL_PSTOPO_MASK;
SMC_STOPCTRL |= partial_stop_opt;
/*wait for write to complete to SMC before stopping core */
dummyread = SMC_PMCTRL;
dummyread = dummyread + 1;
#ifdef CMSIS
/* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */
SCB_SCR |= SCB_SCR_SLEEPDEEP_MASK;
__wfi();
#else
stop();
#endif
}
void enter_vlls0(unsigned char PORPO_value )
{
int i;
/* Write to PMPROT to allow all possible power modes */
SMC_PMPROT = SMC_PMPROT_AVLLS_MASK;
if ((SMC_PMSTAT & SMC_PMSTAT_PMSTAT_MASK)== 4){
SMC_PMCTRL &= ~SMC_PMCTRL_RUNM_MASK; // go back to RUN mode temporarily
for (i=0;i<0xff;i++)
{
if ((SMC_PMSTAT & SMC_PMSTAT_PMSTAT_MASK)== 1)
break;
}
}
/* Set the STOPM field to 0b100 for VLLS0 mode */
SMC_PMCTRL &= ~SMC_PMCTRL_STOPM_MASK;
SMC_PMCTRL |= SMC_PMCTRL_STOPM(0x4);
/* set VLLSM = 0b00 */
SMC_STOPCTRL &= ~SMC_STOPCTRL_VLLSM_MASK;
SMC_STOPCTRL &= ~SMC_STOPCTRL_PORPO_MASK;
SMC_STOPCTRL |= (PORPO_value <<SMC_STOPCTRL_PORPO_SHIFT)
| SMC_STOPCTRL_VLLSM(0);
/*wait for write to complete to SMC before stopping core */
PORPO_value = SMC_STOPCTRL;
/* Now execute the stop instruction to go into VLLS0 */
SCB_SCR |= SCB_SCR_SLEEPDEEP_MASK;
__wfi();
// #ifdef CMSIS
// /* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */
// SCB_SCR |= SCB_SCR_SLEEPDEEP_MASK;
// __wfi();
//#else
// stop();
//#endif
}
static void SetPowerRegisters()
{
SMC->PMPROT = ((1<<SMC_PMPROT_AVLP_SHIFT)|SMC_PMPROT_AVLP_MASK)|((0<<SMC_PMPROT_AVLLS_SHIFT)|SMC_PMPROT_AVLLS_MASK);//allow low power modes to be entered via PMCTRL
SMC->PMCTRL = SMC_PMCTRL_RUNM(2)|SMC_PMCTRL_STOPM(2);//run in VLPR mode, entering sleep will put us in VLPS mode
return;
}
inline void vlps( void ) {
#if defined(__MK66FX1M0__)
#if F_CPU > 120000000
kinetis_hsrun_disable( );
SMC_PMCTRL = SMC_PMCTRL_RUNM( 0x02 ) | SMC_PMCTRL_STOPM( 0x02 );
( void ) SMC_PMCTRL;
#else
SMC_PMCTRL = SMC_PMCTRL_RUNM( 0x02 ) | SMC_PMCTRL_STOPM( 0x02 );
( void ) SMC_PMCTRL;
#endif
#else
SMC_PMCTRL = SMC_PMCTRL_STOPM( 0x02 ) ;
( void ) SMC_PMCTRL;
#endif
// Now execute the stop instruction to go into VLPS
stop( );
}
/* LLS mode entry routine. Puts the processor into LLS mode from
* normal run mode or VLPR.
*
* Mode transitions:
* RUN -> LLS
* VLPR -> LLS
*
* NOTE: LLS mode will always exit to RUN mode even if you were
* in VLPR mode before entering LLS.
*
* Wakeup from LLS mode is controlled by the LLWU module. Most
* modules cannot issue a wakeup interrupt in LLS mode, so make
* sure to setup the desired wakeup sources in the LLWU before
* calling this function.
*
* Parameters:
* none
*/
void enter_lls(void)
{
/* Write to PMPROT to allow LLS power modes */
SMC_PMPROT = SMC_PMPROT_ALLS_MASK; //this write-once bit allows the MCU to enter the
//LLS low power mode
/* Set the LPLLSM field to 0b011 for LLS mode */
SMC_PMCTRL = SMC_PMCTRL_STOPM(0x3) ;
/* Now execute the stop instruction to go into LLS */
stop();
}
/* VLPS mode entry routine. Puts the processor into VLPS mode directly
* from normal run mode.
*
* Mode transitions:
* RUN -> VLPS
*
* If VLPS mode is entered directly from normal RUN mode, then the
* LPWUI bit is forced to 1 by hardware. This means that when an
* interrupt occurs you will exit to normal run mode instead of VLPR.
*
* If however VLPS mode is entered from VLPR the state of the LPWUI bit
* determines the state the MCU will return to upon exit from VLPS.If LPWUI is set
* and an interrupt occurs you will exit to normal run mode instead of VLPR.
* If LPWUI is clear and an interrupt occurs you will exit to VLPR.
*
* Parameters: value of LPWUI
* none
*/
void enter_vlps(char lpwui_value)
{
/* Write to PMPROT to allow VLPS power modes */
SMC_PMPROT = SMC_PMPROT_AVLP_MASK; // write oneif not all set make sure all enabled
//this write-once bit allows the MCU to enter the
//very low power modes: VLPR, VLPW, and VLPS.
/* Set the LPLLSM field to 0b010 for VLPS mode - Need to set state of LPWUI bit 8 */
if(lpwui_value == 1){
SMC_PMCTRL = (SMC_PMCTRL & (SMC_PMCTRL_RUNM_MASK))|
SMC_PMCTRL_LPWUI_MASK |
SMC_PMCTRL_STOPM(0x2) ;
} else {
SMC_PMCTRL = (SMC_PMCTRL & (SMC_PMCTRL_RUNM_MASK )) |
SMC_PMCTRL_STOPM(0x2) ;
}
/* Now execute the stop instruction to go into VLPS */
stop();
}
inline void vlls0_nopor( void ) {
#if defined(__MK66FX1M0__)
#if F_CPU > 120000000
SMC_PMCTRL = SMC_PMCTRL_RUNM( 0x03 ) | SMC_PMCTRL_STOPM( 0x04 );
( void ) SMC_PMCTRL;
#else
SMC_PMCTRL = SMC_PMCTRL_STOPM( 0x03 ) ;
( void ) SMC_PMCTRL;
#endif
#else
SMC_PMCTRL = SMC_PMCTRL_STOPM( 0x03 ) ;
( void ) SMC_PMCTRL;
#endif
SMC_VLLSCTRL = SMC_VLLSCTRL_VLLSM( 0x00 );// set VLLSM = 0b00
( void ) SMC_VLLSCTRL;
// Now execute the stop instruction to go into VLLS0
#if defined(__MK66FX1M0__)
kinetis_hsrun_enable( );
#endif
}
/* VLLS1 mode entry routine. Puts the processor into VLLS1 mode from
* normal run mode or VLPR.
*
* Mode transitions:
* RUN -> VLLS1
* VLPR -> VLLS1
*
* NOTE: VLLSx modes will always exit to RUN mode even if you were
* in VLPR mode before entering VLLSx.
*
* Wakeup from VLLSx mode is controlled by the LLWU module. Most
* modules cannot issue a wakeup interrupt in VLLSx mode, so make
* sure to setup the desired wakeup sources in the LLWU before
* calling this function.
*
* Parameters:
* none
*/
void enter_vlls1(void)
{
/* Write to PMPROT to allow all possible power modes */
/* Set the VLLSM field to 0b100 for VLLS1 mode - Need to retain state of LPWUI bit 8 */
SMC_PMCTRL = (SMC_PMCTRL & (SMC_PMCTRL_RUNM_MASK |SMC_PMCTRL_LPWUI_MASK)) |
SMC_PMCTRL_STOPM(0x4) ; // retain LPWUI
SMC_VLLSCTRL = SMC_VLLSCTRL_VLLSM(1); // set VLLSM = 0b01
/* Now execute the stop instruction to go into VLLS1 */
stop();
}
/* VLLS2 mode entry routine. Puts the processor into VLLS2 mode from
* normal run mode or VLPR.
*
* Mode transitions:
* RUN -> VLLS2
* VLPR -> VLLS2
*
* NOTE: VLLSx modes will always exit to RUN mode even if you were
* in VLPR mode before entering VLLSx.
*
* Wakeup from VLLSx mode is controlled by the LLWU module. Most
* modules cannot issue a wakeup interrupt in VLLSx mode, so make
* sure to setup the desired wakeup sources in the LLWU before
* calling this function.
*
* Parameters:
* none
*/
void enter_vlls2(void)
{
/* Write to PMPROT to allow VLLS2 power modes */
SMC_PMPROT = SMC_PMPROT_AVLLS_MASK;
/* Set the VLLSM field to 0b100 for VLLS2 mode - Need to retain state of LPWUI bit 8 */
SMC_PMCTRL = (SMC_PMCTRL & (SMC_PMCTRL_RUNM_MASK |SMC_PMCTRL_LPWUI_MASK)) |
SMC_PMCTRL_STOPM(0x4) ; // retain LPWUI
SMC_VLLSCTRL = SMC_VLLSCTRL_VLLSM(2); // set VLLSM = 0b10
/* Now execute the stop instruction to go into VLLS2 */
stop();
}
inline void lls( void ) {
#if defined(__MK66FX1M0__)
#if F_CPU > 120000000
kinetis_hsrun_disable( );
SMC_PMCTRL = SMC_PMCTRL_STOPM( 0x03 );
( void ) SMC_PMCTRL;
//SMC_STOPCTRL = 0x02;
#else
SMC_PMCTRL = SMC_PMCTRL_STOPM( 0x03 ) ;
( void ) SMC_PMCTRL;
#endif
#else
SMC_PMCTRL = SMC_PMCTRL_STOPM( 0x03 ) ;
( void ) SMC_PMCTRL;
#endif
// Now execute the stop instruction to go into LLS
stop( );
#if defined(__MK66FX1M0__)
#if F_CPU > 120000000
kinetis_hsrun_enable( );
#endif
#endif
}
inline void vlls1( void ) {
#if defined(__MK66FX1M0__)
#if F_CPU > 120000000
kinetis_hsrun_disable( );
SMC_PMCTRL = SMC_PMCTRL_STOPM( 0x04 );
( void ) SMC_PMCTRL;
#else
SMC_PMCTRL = SMC_PMCTRL_STOPM( 0x04 ) ;
( void ) SMC_PMCTRL;
#endif
#else
SMC_PMCTRL = SMC_PMCTRL_STOPM( 0x04 ) ;
( void ) SMC_PMCTRL;
#endif
SMC_VLLSCTRL = SMC_VLLSCTRL_VLLSM( 0x01 );// set VLLSM = 0b01
( void ) SMC_VLLSCTRL;
// Now execute the stop instruction to go into VLLS1
stop( );
#if defined(__MK66FX1M0__)
#if F_CPU > 120000000
kinetis_hsrun_enable( );
#endif
#endif
}
/* ===================================================================*/
LDD_TError Cpu_SetOperationMode(LDD_TDriverOperationMode OperationMode, LDD_TCallback ModeChangeCallback, LDD_TCallbackParam *ModeChangeCallbackParamPtr)
{
(void) ModeChangeCallback; /* Parameter is not used, suppress unused argument warning */
(void) ModeChangeCallbackParamPtr; /* Parameter is not used, suppress unused argument warning */
switch (OperationMode) {
case DOM_RUN:
/* SCB_SCR: SLEEPDEEP=0,SLEEPONEXIT=0 */
SCB_SCR &= (uint32_t)~(uint32_t)(
SCB_SCR_SLEEPDEEP_MASK |
SCB_SCR_SLEEPONEXIT_MASK
);
if (ClockConfigurationID != 2U) {
if ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(3)) { /* If in PBE mode, switch to PEE. PEE to PBE transition was caused by wakeup from low power mode. */
/* MCG_C1: CLKS=0,IREFS=0 */
MCG_C1 &= (uint8_t)~(uint8_t)((MCG_C1_CLKS(0x03) | MCG_C1_IREFS_MASK));
while( (MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait for PLL lock */
}
}
}
break;
case DOM_WAIT:
/* SCB_SCR: SLEEPDEEP=0 */
SCB_SCR &= (uint32_t)~(uint32_t)(SCB_SCR_SLEEPDEEP_MASK);
/* SCB_SCR: SLEEPONEXIT=0 */
SCB_SCR &= (uint32_t)~(uint32_t)(SCB_SCR_SLEEPONEXIT_MASK);
PE_WFI();
break;
case DOM_SLEEP:
/* SCB_SCR: SLEEPDEEP=1 */
SCB_SCR |= SCB_SCR_SLEEPDEEP_MASK;
/* SMC_PMCTRL: STOPM=0 */
SMC_PMCTRL &= (uint8_t)~(uint8_t)(SMC_PMCTRL_STOPM(0x07));
(void)(SMC_PMCTRL == 0U); /* Dummy read of SMC_PMCTRL to ensure the register is written before enterring low power mode */
/* SCB_SCR: SLEEPONEXIT=1 */
SCB_SCR |= SCB_SCR_SLEEPONEXIT_MASK;
PE_WFI();
break;
case DOM_STOP:
break;
default:
return ERR_PARAM_MODE;
}
return ERR_OK;
}
void enter_lls(void)
{
volatile unsigned int dummyread;
/* Write to PMPROT to allow LLS power modes this write-once
bit allows the MCU to enter the LLS low power mode*/
SMC_PMPROT = SMC_PMPROT_ALLS_MASK;
/* Set the STOPM field to 0b011 for LLS mode */
SMC_PMCTRL &= ~SMC_PMCTRL_STOPM_MASK;
SMC_PMCTRL |= SMC_PMCTRL_STOPM(0x3);
/*wait for write to complete to SMC before stopping core */
dummyread = SMC_PMCTRL;
dummyread = dummyread + 1;
/* Now execute the stop instruction to go into LLS */
#ifdef CMSIS
/* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */
SCB_SCR |= SCB_SCR_SLEEPDEEP_MASK;
__wfi();
#else
stop();
#endif
}
int cmd_low_power(int argc, char * const argv[])
{
printf("entering VLPS mode...\r\n");
printf("press NMI switch (k2) to wake up\r\n");
/* allow VLPS mode */
SMC->PMPROT |= SMC_PMPROT_AVLP(1);
/* set VLPS mode */
SMC->PMCTRL &= ~SMC_PMCTRL_STOPM_MASK;
SMC->PMCTRL |= SMC_PMCTRL_STOPM(2);
DelayMs(10);
/* enter STOP */
EnterSTOPMode(false);
printf("wake up from VLPS mode\r\n");
return 0;
}
/*----------------------------------------------------------------------------
MAIN function
*----------------------------------------------------------------------------*/
int main (void) {
#if USE_VLPR == 1
// enter low power run
SIM->CLKDIV1 = (0x1 << SIM_CLKDIV1_OUTDIV1_SHIFT) | (0x5 << SIM_CLKDIV1_OUTDIV4_SHIFT); // reduce core clock < 4 MHz and flash < 1 MHz
MCG->C6 &= ~MCG_C6_CME0_MASK; // disable MCG clock monitor
MCG->C2 |= MCG_C2_IRCS_MASK; // don't use slow internal reference clock
MCG->C1 |= MCG_C1_CLKS(2); // enter BLPE mode
MCG->C1 &= ~MCG_C1_IREFS_MASK;
MCG->C6 &= ~MCG_C6_PLLS_MASK;
while(!(MCG->S & MCG_S_IREFST_MASK >> MCG_S_IREFST_SHIFT)); // wait to ensure clock change
MCG->C2 |= MCG_C2_LP_MASK;
#endif
Init_RGB_LEDs();
#if DEBUG_SIGNALS == 1
Init_Debug_Signals();
#endif
// I2C and MMA
i2c_init(); /* init i2c */
if (!init_mma()) { /* init mma peripheral */
Control_RGB_LEDs(1, 0, 0); /* Light red error LED */
while (1) /* not able to initialize mma */
;
}
#if RUN_I2C_FAST == 1
// increase i2c baud rate
I2C_DISABLE;
I2C0->F = (I2C_F_ICR(0x00) | I2C_F_MULT(0));
I2C_ENABLE;
#endif
// configure low power modes
SMC->PMPROT = SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK; // allow low leakage stop mode
SMC->PMCTRL = SMC_PMCTRL_RUNM(2) | SMC_PMCTRL_STOPM(3); // enable low power run mode (10) and low leakage stop mode (011)
SMC->STOPCTRL = SMC_STOPCTRL_PSTOPO(0) | SMC_STOPCTRL_VLLSM(3); // normal stop mode and VLL stop3 (not needed?)
// configure low leakage wakeup unit (LLWU)
LLWU->ME |= LLWU_ME_WUME0_MASK; // internal module 0 is wakeup source which is apparently the LPTMR
// enable stop mode (deep sleep)
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
// LPTMR
Init_LPTMR();
Start_LPTMR();
__enable_irq();
while (1) {
// read acceleration every 100 ms
if (run_Read_Accel){
run_Read_Accel = 0;
Read_Accel();
}
// update LEDs every 500 ms; keep them on for 10 ms
if (run_Update_LEDs){
run_Update_LEDs = 0;
Update_LEDs();
#if USE_PWM == 1
#if PWM_SLEEP == 1
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; // switch to regular sleep mode
#if USE_SLEEP_MODES == 1
#if DEBUG_SIGNALS == 1
PTE->PSOR |= MASK(30);
#endif
__wfi(); // PWM does not work in LLS mode
#endif
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; // switch back to LLS mode
#else
while(led_on_period); // poll -> bad solution
#endif
#endif
}
#if USE_SLEEP_MODES == 1
#if DEBUG_SIGNALS == 1
PTE->PSOR |= MASK(30);
#endif
__wfi(); // go to sleep
#endif
}
}
/* STOP mode entry routine. Puts the processor into normal stop mode.
* In this mode core, bus and peripheral clocks are disabled.
*
* Mode transitions:
* RUN -> STOP
* VLPR -> VLPS
*
* This function can be used to enter normal stop mode or VLPS
* mode. If you are executing in normal run mode when calling this
* function, then you will enter normal stop mode. If you are in VLPR
* mode when calling this function, then you will enter VLPS mode instead.
*
* STOP mode is exited using any enabled interrupt or RESET, so no
* exit_stop routine is needed.
*
* Parameters:
* none
*/
void enter_stop(void)
{
/* Set the STOPM field to 0b000 for normal STOP mode - Need to retain state of LPWUI bit 8 */
SMC_PMCTRL = SMC_PMCTRL_STOPM(0); // set STOPM = 0b000
stop();
}
SMC_PMCTRL_LPWUI_MASK, // Mode PMCTRL register == voltage regulator ON after wakeup
LPM_CPU_POWER_MODE_FLAG_STOPE, // Mode flags == deepsleep, execute WFI
},
// VLPR
{
SMC_PMCTRL_RUNM(2), // Mode PMCTRL register == VLPR
0, // Mode flags == clear settings
},
// VLPW
{
SMC_PMCTRL_RUNM(2), // Mode PMCTRL register == VLPW
LPM_CPU_POWER_MODE_FLAG_WAITE, // Mode flags == execute WFI
},
// VLPS
{
SMC_PMCTRL_STOPM(2), // Mode PMCTRL register == VLPS
LPM_CPU_POWER_MODE_FLAG_STOPE, // Mode flags == deepsleep, execute WFI
},
// LLS
{
SMC_PMCTRL_LPWUI_MASK | SMC_PMCTRL_STOPM(4), // Mode PMCTRL register == voltage regulator ON after wakeup, LLS
LPM_CPU_POWER_MODE_FLAG_STOPE, // Mode flags == deepsleep, execute WFI
}
};
#else
static const LDD_TDriverOperationMode LPM_PE_OPERATION_MODE_MAP[LPM_OPERATION_MODES] =
{
void main (void)
{
#ifndef RAM16
int i;
int counter = 0;
#endif
#ifdef KEIL
start();
#endif
LLWU_Init();
SW_LED_Init();
LED0_ON;
LED1_ON;
LED2_ON;
LED3_ON;
// Dynamic interrupt vector modification whilst those interrupts are disabled
// __VECTOR_RAM[INT_ADC0] = (uint32)adc0_isr; // plug isr into vector table in case not there already
if ((RCM_SRS0 & RCM_SRS0_POR_MASK) || (RCM_SRS0 & RCM_SRS0_PIN_MASK))
{
printf("\nRunning VLPR LLS ADC Demo Project");
// ch = in_char();
// out_char(ch);
// disable_uart();
init_ADC16();
}
lptmr_init(100, LPTMR_USE_LPOCLK);
/* Enable LPTMR wakeup interrupt */
enable_irq(LPTMR_irq_no);
/* Enable ADC ready for this interrupt. */
// enable_irq(ADC0_irq_no) ;
EnableInterrupts;
//Set the STOPM field to 0b011 for LLS mode
SMC_PMCTRL |= SMC_PMCTRL_STOPM(0x3) ;
dummyread=SMC_PMCTRL;
// Set the SLEEPDEEP bit to enable deep sleep mode (STOP)
SCB_SCR |= SCB_SCR_SLEEPDEEP_MASK;
#ifdef RAM16
ram_main();
#else
while(1)
{
// WFI instruction will start entry into LLS mode
counter++;
if (counter & 0x0001)
F_LED0_ON;
else
F_LED0_OFF;
if (counter & 0x0002)
F_LED3_ON;
else
F_LED3_OFF;
if (counter & 0x0004)
F_LED2_ON;
else
F_LED2_OFF;
if (counter & 0x0008)
F_LED1_ON;
else
F_LED1_OFF;
asm("WFI");
for (i=0;i<1000;i++){
if (ADC0_SC2 & ADACT_ACTIVE)
F_LED2_TOGGLE;
else
break;
}
result0A = ADC0_RA ;
}
#endif
}
