int mau_config(MTK_MAU_CONFIG* pMauConf)
{
if(pMauConf->larb > SMI_LARB_NR ||
pMauConf->entry > MAU_ENTRY_NR
)
{
SMIERR("config:larb=%d,entry=%d\n", pMauConf->larb, pMauConf->entry);
SMIMSG("mau config error: larb=%d,entry=%d,rd=%d,wr=%d,vir=%d,start=0x%x,end=0x%x,port_msk=0x%x\n",
pMauConf->larb, pMauConf->entry, pMauConf->monitor_read, pMauConf->monitor_write,
pMauConf->virt,pMauConf->start, pMauConf->end, pMauConf->port_msk);
return -1;
}
SMIMSG("mau config: larb=%d,entry=%d,rd=%d,wr=%d,vir=%d,start=0x%x,end=0x%x,port_msk=0x%x\n",
pMauConf->larb, pMauConf->entry, pMauConf->monitor_read, pMauConf->monitor_write,
pMauConf->virt,pMauConf->start, pMauConf->end, pMauConf->port_msk);
larb_clock_on(pMauConf->larb);
mau_start_monitor(pMauConf->larb,
pMauConf->entry,
!!(pMauConf->monitor_read),
!!(pMauConf->monitor_write),
!!(pMauConf->virt),
pMauConf->start,
pMauConf->end,
pMauConf->port_msk);
larb_clock_off(pMauConf->larb);
return 0;
}
int larb_reg_restore(int larb)
{
unsigned int regval,regval1,regval2;
unsigned int larb_base = gLarbBaseAddr[larb];
/*
unsigned int* pReg = pLarbRegBackUp[larb];
int i;
//warning: larb_con is controlled by set/clr
regval = *(pReg++);
M4U_WriteReg32(larb_base, SMI_LARB_CON_CLR, ~(regval));
M4U_WriteReg32(larb_base, SMI_LARB_CON_SET, (regval));
M4U_WriteReg32(larb_base, SMI_SHARE_EN, *(pReg++) );
M4U_WriteReg32(larb_base, SMI_ROUTE_SEL, *(pReg++) );
for(i=0; i<3; i++)
{
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_START(i), *(pReg++));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_END(i), *(pReg++));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_GID(i), *(pReg++));
}
*/
//Clock manager enable LARB clock before call back restore already, it will be disabled after restore call back returns
//Got to enable OSTD before engine starts
regval = M4U_ReadReg32(larb_base , SMI_LARB_STAT);
regval1 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ0);
regval2 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ1);
if(0 == regval)
{
M4U_WriteReg32(larb_base , SMI_LARB_OSTD_CTRL_EN , 0xffffffff);
}
else
{
SMIMSG("Larb%d is busy : 0x%x , port:0x%x,0x%x ,fail to set OSTD\n" , larb , regval , regval1 , regval2);
smi_dumpDebugMsg();
SMIERR("DISP_MDP LARB%d OSTD cannot be set:0x%x,port:0x%x,0x%x\n" , larb , regval , regval1 , regval2);
}
if(0 == g_bInited)
{
initSetting();
g_bInited = 1;
SMIMSG("SMI init\n");
}
return 0;
}
// callback after larb clock is enabled
void on_larb_power_on(struct larb_monitor *h, int larb_idx)
{
SMIMSG("on_larb_power_on(), larb_idx=%d \n", larb_idx);
larb_reg_restore(larb_idx);
return;
}
static int smi_release(struct inode *inode, struct file *file)
{
#if 0
unsigned long u4Index = 0 ;
unsigned long u4AssignCnt = 0;
unsigned long * pu4Cnt = (unsigned long *)file->private_data;
MTK_SMI_BWC_CONFIG config;
for(; u4Index < SMI_BWC_SCEN_CNT ; u4Index += 1)
{
if(pu4Cnt[u4Index])
{
SMIMSG("Process:%s does not turn off BWC properly , force turn off %d\n" , current->comm , u4Index);
u4AssignCnt = pu4Cnt[u4Index];
config.b_on_off = 0;
config.scenario = (MTK_SMI_BWC_SCEN)u4Index;
do
{
smi_bwc_config( &config , pu4Cnt);
}
while(0 < u4AssignCnt);
}
}
#endif
if(NULL != file->private_data)
{
kfree(file->private_data);
file->private_data = NULL;
}
return 0;
}
void smi_bwc_mm_info_set(int property_id, long val1, long val2){
SMIMSG("Set BWC INFO:%d, val=[%d,%d]", val1, val2);
switch(property_id){
case SMI_BWC_INFO_CON_PROFILE:
g_smi_bwc_mm_info.concurrent_profile = (int)val1;
break;
case SMI_BWC_INFO_SENSOR_SIZE:
g_smi_bwc_mm_info.sensor_size[0] = val1;
g_smi_bwc_mm_info.sensor_size[1] = val2;
break;
case SMI_BWC_INFO_VIDEO_RECORD_SIZE:
g_smi_bwc_mm_info.video_record_size[0]= val1;
g_smi_bwc_mm_info.video_record_size[1]= val2;
break;
case SMI_BWC_INFO_DISP_SIZE:
g_smi_bwc_mm_info.display_size[0]= val1;
g_smi_bwc_mm_info.display_size[1]= val2;
break;
case SMI_BWC_INFO_TV_OUT_SIZE:
g_smi_bwc_mm_info.tv_out_size[0]= val1;
g_smi_bwc_mm_info.tv_out_size[1]= val2;
break;
case SMI_BWC_INFO_FPS:
g_smi_bwc_mm_info.fps = (int)val1;
break;
case SMI_BWC_INFO_VIDEO_ENCODE_CODEC:
g_smi_bwc_mm_info.video_encode_codec = (int)val1;
break;
case SMI_BWC_INFO_VIDEO_DECODE_CODEC:
g_smi_bwc_mm_info.video_decode_codec = (int)val1;
break;
}
}
/*****************************************************************************
* FUNCTION
* mau_isr
* DESCRIPTION
* 1. Print MAU status, such as port ID.
* 2. Clear interrupt status.
* PARAMETERS
* param1 : [IN] int irq
* irq number.
* param2 : [IN] void *dev_id
* No use in this function.
* RETURNS
* Type: irqreturn_t. IRQ_HANDLED mean success.
****************************************************************************/
static irqreturn_t mau_isr(int irq, void *dev_id)
{
int larb,i;
unsigned int larb_base;
unsigned int regval;
switch(irq)
{
case MT_SMI_LARB0_IRQ_ID:
larb = 0;
break;
default :
larb=0;
SMIERR("unkown irq(%d)\n",irq);
}
larb_clock_on(larb, "MAU");
larb_base = gLarbBaseAddr[larb];
//dump interrupt debug infomation
for(i=0; i<MAU_ENTRY_NR; i++)
{
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_STAT(i));
if(F_MAU_STAT_ASSERT(regval))
{
//violation happens in this entry
int port = F_MAU_STAT_ID(regval);
SMIMSG("[MAU] larb=%d, entry=%d, port=%d\n",larb,i,port);
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_START(i));
SMIMSG("start_addr=0x%x, read_en=%d, write_en=%d\n", F_MAU_START_ADDR_VAL(regval),
F_MAU_START_IS_RD(regval), F_MAU_START_IS_WR(regval));
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_END(i));
SMIMSG("end_addr=0x%x, virtual=%d\n", F_MAU_END_ADDR_VAL(regval),
F_MAU_END_IS_VIR(regval));
smi_aee_print("violation by %s\n",smi_port_name[port]);
}
//clear interrupt status
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_STAT(i));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_STAT(i), regval);
}
larb_clock_off(larb, "MAU");
return IRQ_HANDLED;
}
void smi_hanging_debug(int dump_count){
// dump 5 times
int i = 0;
// Step 0 Dump register state
SMIMSG("**SMI DBG 0: Dump register state\n");
for(i=0; i<dump_count;i++){
smi_dumpCommonDebugMsg();
smi_dumpLarbDebugMsg(0);
}
// Step 1
//write SMI_LARB0+0x64 = 0
SMIMSG("**SMI DBG 1: write SMI_LARB0+0x64 = 0\n");
M4U_WriteReg32(LARB0_BASE , 0x64 , 0);
SMIMSG("==========> REG DUMP\n");
for(i=0; i<dump_count;i++){
smi_dumpCommonDebugMsg();
smi_dumpLarbDebugMsg(0);
}
// Step 2
//write SMI_LARB0+0x8c = 0
SMIMSG("**SMI DBG 2: write SMI_LARB0+0x8c = 0\n");
M4U_WriteReg32(LARB0_BASE , 0x8c , 0);
SMIMSG("==========> REG DUMP\n");
for(i=0; i<dump_count;i++){
smi_dumpCommonDebugMsg();
smi_dumpLarbDebugMsg(0);
}
// Step 3
// write SMI_LARB0+0x28 = 0x30
// write SMI_LARB0+0x24 = 0x40
SMIMSG("**SMI DBG 3: write SMI_LARB0+0x28 = 0x30, SMI_LARB0+0x24 = 0x40\n");
M4U_WriteReg32(LARB0_BASE , 0x28 ,0x30);
M4U_WriteReg32(LARB0_BASE , 0x24 ,0x40);
SMIMSG("==========> REG DUMP\n");
for(i=0; i<dump_count;i++){
smi_dumpCommonDebugMsg();
smi_dumpLarbDebugMsg(0);
}
// Step 4
// write 0x1400_0138 = 0xFFFF_FFFD
// write 0x1400_0138 = 0xFFFF_FFFF
SMIMSG("**SMI DBG 3: write 0x14000138 = 0xFFFFFFFD, SMI_LARB0+0x14000138 = 0xFFFFFFFF\n");
M4U_WriteReg32(0xF4000138 , 0 ,0xFFFFFFFD);
M4U_WriteReg32(0xF4000138 , 0 ,0xFFFFFFFF);
SMIMSG("==========> REG DUMP\n");
for(i=0; i<dump_count;i++){
smi_dumpCommonDebugMsg();
smi_dumpLarbDebugMsg(0);
}
}
/*****************************************************************************
* FUNCTION
* mau_dump_status
* DESCRIPTION
* 1. Dump register in MAU related register.
* 2. Show MAU status
* PARAMETERS
* param1 : [IN] MTK_MAU_CONFIG* pMauConf
* MAU setting configuration.
* RETURNS
* None.
****************************************************************************/
void mau_dump_status(const int larb)
{
unsigned int larb_base;
unsigned int regval;
int i;
larb_clock_on(larb, "MAU");
larb_base = gLarbBaseAddr[larb];
//dump interrupt debug infomation
for(i=0; i<MAU_ENTRY_NR; i++)
{
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_GID(i));
if(regval!=0)
{
SMIMSG("larb(%d), entry(%d)=========>\n", larb, i);
SMIMSG("port mask = 0x%x\n", regval);
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_START(i));
SMIMSG("start_addr=0x%x, read_en=%d, write_en=%d\n",
F_MAU_START_ADDR_VAL(regval),
F_MAU_START_IS_RD(regval), F_MAU_START_IS_WR(regval));
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_END(i));
SMIMSG("end_addr=0x%x, virtual=%d\n", F_MAU_END_ADDR_VAL(regval),
F_MAU_END_IS_VIR(regval));
}
else
{
SMIMSG("larb(%d), entry(%d) is free\n", larb, i);
}
//dump interrupt debug infomation
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_STAT(i));
if(F_MAU_STAT_ASSERT(regval))
{
//violation happens in this entry
int port = F_MAU_STAT_ID(regval);
SMIMSG("[MAU] larb=%d, entry=%d, port=%d\n",larb,i,port);
SMIMSG("violation by %s\n",smi_port_name[port]);
}
else
{
SMIMSG("no violation of entry %d\n", i);
}
#if 0
//clear interrupt status
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_STAT(i));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_STAT(i), regval);
#endif
}
larb_clock_off(larb, "MAU");
}
void dump_smi_register(void)
{
int i;
SMIMSG(" SMI COMMON Register Start ======= \n");
for(i=0;i<4096/8;i+=4)
{
SMIMSG("+0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x \n", 8*i,
M4U_ReadReg32(SMI_COMMON_EXT_BASE, 8*i + 4*0), M4U_ReadReg32(SMI_COMMON_EXT_BASE, 8*i + 4*1),
M4U_ReadReg32(SMI_COMMON_EXT_BASE, 8*i + 4*2), M4U_ReadReg32(SMI_COMMON_EXT_BASE, 8*i + 4*3),
M4U_ReadReg32(SMI_COMMON_EXT_BASE, 8*i + 4*4), M4U_ReadReg32(SMI_COMMON_EXT_BASE, 8*i + 4*5),
M4U_ReadReg32(SMI_COMMON_EXT_BASE, 8*i + 4*6), M4U_ReadReg32(SMI_COMMON_EXT_BASE, 8*i + 4*7));
}
SMIMSG(" SMI COMMONR egister End ========== \n");
SMIMSG(" SMI LARB Register Start ======= \n");
for(i=0;i<4096/8;i+=4)
{
SMIMSG("+0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x \n", 8*i,
M4U_ReadReg32(LARB0_BASE, 8*i + 4*0), M4U_ReadReg32(LARB0_BASE, 8*i + 4*1),
M4U_ReadReg32(LARB0_BASE, 8*i + 4*2), M4U_ReadReg32(LARB0_BASE, 8*i + 4*3),
M4U_ReadReg32(LARB0_BASE, 8*i + 4*4), M4U_ReadReg32(LARB0_BASE, 8*i + 4*5),
M4U_ReadReg32(LARB0_BASE, 8*i + 4*6), M4U_ReadReg32(LARB0_BASE, 8*i + 4*7));
}
SMIMSG(" SMI LARB egister End ========== \n");
}
int smi_get_mm_info_ioctl_wrapper(struct file *pFile, unsigned int cmd, unsigned long param)
{
int ret = 0;
ret = copy_to_user((void *)param, (void *)&g_smi_bwc_mm_info, sizeof(MTK_SMI_BWC_MM_INFO));
if (ret) {
SMIMSG(" MTK_IOC_SMI_BWC_INFO_GET, copy_to_user failed: %d\n", ret);
return -EFAULT;
}
/* SMIMSG("Handle MTK_IOC_SMI_BWC_INFO_GET request... finish"); */
return ret;
}
// Check if specified MMSYS LARB is busy
// Return value:
// 1: MMSYS larb is busy
// 0: Bus is not busy
int is_smi_larb_busy(unsigned int u4Index){
unsigned int reg_value_0= 0;
unsigned int reg_value_1= 0;
unsigned int u4Base;
if(u4Index <0 || u4Index > 2){
SMIMSG("Doesn't support reg dump for Larb%d\n", u4Index);
return 0;
}
u4Base = gLarbBaseAddr[u4Index];
// 1. 0x0 == 1
reg_value_0 = M4U_ReadReg32(u4Base, 0x0);
if( 0x0!=1 ){
return 0;
}
// 2. (0x450 | 0x454) == 1
reg_value_0 = M4U_ReadReg32(u4Base, 0x450);
reg_value_1 = M4U_ReadReg32(u4Base, 0x454);
if( (reg_value_0 | reg_value_1) != 1){
return 0;
}
// 3. 0x600 == 0xaaaa
reg_value_0 = M4U_ReadReg32(u4Base, 0x600);
if( reg_value_0 != 0xaaaa){
return 0;
}
// 4. 0x604 == 0x2a8
reg_value_0 = M4U_ReadReg32(u4Base, 0x604);
if( reg_value_0 != 0x2a8){
return 0;
}
// 5. 0x610 == 0x3e0
reg_value_0 = M4U_ReadReg32(u4Base, 0x610);
if( reg_value_0 != 0x3e0){
return 0;
}
// 6. 0x614 == 0x3e0
reg_value_0 = M4U_ReadReg32(u4Base, 0x614);
if( reg_value_0 != 0x3e0){
return 0;
}
return 1;
}
/*****************************************************************************
* FUNCTION
* on_larb_power_on
* DESCRIPTION
* Callback after larb clock is enabled.
* PARAMETERS
* param1 : [IN] struct larb_monitor *h
* No used in this function.
* param2 : [IN] int larb_idx
* larb index.
* RETURNS
* None.
****************************************************************************/
static void on_larb_power_on(struct larb_monitor *h, int larb_idx)
{
SMIMSG("on_larb_power_on(), larb_idx=%d \n", larb_idx);
larb_reg_restore(larb_idx);
// larb_clock_on(0, "SMI");
#ifdef SMI_DEFAULT_VR
{
MTK_SMI_BWC_CONFIG p_conf;
p_conf.b_reduce_command_buffer = 1;
p_conf.scenario = SMI_BWC_SCEN_VR1066;
smi_bwc_config(&p_conf);
}
#endif
}
static int smi_open(struct inode *inode, struct file *file)
{
file->private_data = kmalloc(SMI_BWC_SCEN_CNT*sizeof(unsigned long) , GFP_ATOMIC);
if(NULL == file->private_data)
{
SMIMSG("Not enough entry for DDP open operation\n");
return -ENOMEM;
}
memset(file->private_data , 0 , SMI_BWC_SCEN_CNT*sizeof(unsigned long));
return 0;
}
int smi_set_mm_info_ioctl_wrapper(struct file *pFile, unsigned int cmd, unsigned long param)
{
int ret = 0;
MTK_SMI_BWC_INFO_SET cfg;
ret = copy_from_user(&cfg, (void *)param, sizeof(MTK_SMI_BWC_INFO_SET));
if (ret) {
SMIMSG(" MTK_IOC_SMI_BWC_INFO_SET, copy_to_user failed: %d\n", ret);
return -EFAULT;
}
/* Set the address to the value assigned by user space program */
smi_bwc_mm_info_set(cfg.property, cfg.value1, cfg.value2);
/* SMIMSG("Handle MTK_IOC_SMI_BWC_INFO_SET request... finish"); */
return ret;
}
void smi_dumpCommonDebugMsg(void)
{
unsigned int u4Base;
//SMI COMMON dump
SMIMSG("===SMI common reg dump===\n");
u4Base = SMI_COMMON_EXT_BASE;
SMIMSG("[0x200,0x204,0x208]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x200),M4U_ReadReg32(u4Base , 0x204),M4U_ReadReg32(u4Base , 0x208));
SMIMSG("[0x20C,0x210,0x214]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x20C),M4U_ReadReg32(u4Base , 0x210),M4U_ReadReg32(u4Base , 0x214));
SMIMSG("[0x218,0x230,0x234]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x218),M4U_ReadReg32(u4Base , 0x230),M4U_ReadReg32(u4Base , 0x234));
SMIMSG("[0x400,0x404]=[0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x400),M4U_ReadReg32(u4Base , 0x404));
// For VA and PA check:
// 0x1000C5C0 , 0x1000C5C4, 0x1000C5C8, 0x1000C5CC, 0x1000C5D0
u4Base = SMI_COMMON_AO_BASE;
SMIMSG("===SMI always on reg dump===\n");
SMIMSG("[0x5C0,0x5C4,0x5C8]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x5C0),M4U_ReadReg32(u4Base , 0x5C4),M4U_ReadReg32(u4Base , 0x5C8));
SMIMSG("[0x5CC,0x5D0]=[0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x5CC),M4U_ReadReg32(u4Base , 0x5D0));
}
/*****************************************************************************
* FUNCTION
* smi_ioctl
* DESCRIPTION
* File operations - unlocked_ioctl
* 1. call copy_from_user to get user space parameter
* 2. call internal function by operation.
* PARAMETERS
* param1 : [IN] struct file * pFile
* file structure*.
* param2 : [IN] unsigned int cmd
* operation command.
* param3 : [IN] unsigned long param
* parameter of ioctl.
* RETURNS
* Type: Integer. zero means success and others mean error.
****************************************************************************/
static long smi_ioctl(struct file * pFile,
unsigned int cmd,
unsigned long param)
{
int ret = 0;
switch (cmd)
{
case MTK_CONFIG_MM_MAU:
{
MTK_MAU_CONFIG b;
if(copy_from_user(&b, (void __user *)param, sizeof(b)))
{
SMIERR("copy_from_user failed!");
ret = -EFAULT;
} else {
mau_config(&b);
}
return ret;
}
case MTK_IOC_SMI_BWC_CONFIG:
{
MTK_SMI_BWC_CONFIG cfg;
ret = copy_from_user(&cfg, (void*)param , sizeof(MTK_SMI_BWC_CONFIG));
if(ret)
{
SMIMSG(" SMI_BWC_CONFIG, copy_from_user failed: %d\n", ret);
return -EFAULT;
}
smi_bwc_config( &cfg );
}
break;
default:
return -1;
}
return ret;
}
void smi_dumpLarbDebugMsg(unsigned int u4Index){
unsigned int u4Base;
if(0 == u4Index)
{
// if((0 == clock_is_on(MT_CG_DISP0_SMI_LARB0)) || (0 == clock_is_on(MT_CG_DISP0_SMI_COMMON)))
if(0x3 & M4U_ReadReg32(0xF4000000 , 0x100))
{
SMIMSG("===SMI%d is off===\n" , u4Index);
return;
}
}
else if(1 == u4Index)
{
// if(0 == clock_is_on(MT_CG_VDEC1_LARB))
if(0x1 & M4U_ReadReg32(0xF6000000 , 0xC))
{
SMIMSG("===SMI%d is off===\n" , u4Index);
return;
}
}
else if(2 == u4Index)
{
// if(0 == clock_is_on(MT_CG_IMAGE_LARB2_SMI))
if(0x1 & M4U_ReadReg32(0xF5000000 , 0))
{
SMIMSG("===SMI%d is off===\n" , u4Index);
return;
}
}
if(u4Index <0 || u4Index > 2)
{
SMIMSG("Doesn't support reg dump for Larb%d\n", u4Index);
return;
}else{
u4Base = gLarbBaseAddr[u4Index];
SMIMSG("===SMI%d reg dump===\n" , u4Index);
SMIMSG("[0x0,0x10,0x60]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x0),M4U_ReadReg32(u4Base , 0x10),M4U_ReadReg32(u4Base , 0x60));
SMIMSG("[0x64,0x8c,0x450]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x64),M4U_ReadReg32(u4Base , 0x8c),M4U_ReadReg32(u4Base , 0x450));
SMIMSG("[0x454,0x600,0x604]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x454),M4U_ReadReg32(u4Base , 0x600),M4U_ReadReg32(u4Base , 0x604));
SMIMSG("[0x610,0x614]=[0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x610),M4U_ReadReg32(u4Base , 0x614));
SMIMSG("[0x200,0x204,0x208]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x200),M4U_ReadReg32(u4Base , 0x204),M4U_ReadReg32(u4Base , 0x208));
SMIMSG("[0x20c,0x210,0x214]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x20c),M4U_ReadReg32(u4Base , 0x210),M4U_ReadReg32(u4Base , 0x214));
SMIMSG("[0x218,0x21c,0x220]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x218),M4U_ReadReg32(u4Base , 0x21c),M4U_ReadReg32(u4Base , 0x220));
SMIMSG("[0x224,0x228,0x22c]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x224),M4U_ReadReg32(u4Base , 0x228),M4U_ReadReg32(u4Base , 0x22c));
SMIMSG("[0x230,0x234,0x238]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x230),M4U_ReadReg32(u4Base , 0x234),M4U_ReadReg32(u4Base , 0x238));
SMIMSG("[0x23c,0x240]=[0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x23c),M4U_ReadReg32(u4Base , 0x240));
}
}
static void process_dbg_opt(const char *opt)
{
//m4u log
if (0 == strncmp(opt, "m4u_log:", 8))
{
if (0 == strncmp(opt + 8, "on", 2))
m4u_log_on();
else if (0 == strncmp(opt + 8, "off", 3))
m4u_log_off();
else
goto Error;
}
//m4u debug
if (0 == strncmp(opt, "m4u_debug:", 10))
{
unsigned int command;
char *p = (char *)opt + 10;
command = (unsigned int) simple_strtoul(p, &p, 10);
SMIMSG("m4u_debug_command, command=%d ", command);
m4u_debug_command(command);
}
//mau dump
if (0 == strncmp(opt, "mau_stat:", 9))
{
char *p = (char *)opt + 9;
unsigned int larb=(unsigned int)simple_strtoul(p, &p, 16);
if(larb>SMI_LARB_NR)
SMIERR("debug error: larb=%d\n", larb);
mau_dump_status(larb);
}
if (0 == strncmp(opt, "mau_config:", 11 ))
{
MTK_MAU_CONFIG MauConf;
unsigned int larb,entry, rd, wt, vir, start, end, port_msk;
char *p = (char *)opt + 11;
larb = (unsigned int) simple_strtoul(p, &p, 16);
p++;
entry = (unsigned int) simple_strtoul(p, &p, 16);
p++;
rd = (unsigned int) simple_strtoul(p, &p, 16);
p++;
wt = (unsigned int) simple_strtoul(p, &p, 16);
p++;
vir = (unsigned int) simple_strtoul(p, &p, 16);
p++;
start = (unsigned int) simple_strtoul(p, &p, 16);
p++;
end = (unsigned int) simple_strtoul(p, &p, 16);
p++;
port_msk = (unsigned int) simple_strtoul(p, &p, 16);
SMIMSG("larb=%d,entry=%d,rd=%d wt=%d vir=%d \n"
"start=0x%x end=0x%x msk=0x%x \n",
larb, entry, rd, wt, vir, start, end, port_msk);
MauConf.larb = larb;
MauConf.entry = entry;
MauConf.monitor_read = rd;
MauConf.monitor_write = wt;
MauConf.virt = vir;
MauConf.start = start;
MauConf.end = end;
MauConf.port_msk = port_msk;
mau_config(&MauConf);
}
if (0 == strncmp(opt, "spc_config:", 11 ))
{
MTK_SPC_CONFIG pCfg;
char *p = (char *)opt + 11;
SMIMSG("%s", p);
//0-no protect; 1-sec rw; 2-sec_rw nonsec_r; 3-no access
pCfg.domain_0_prot = (unsigned int) simple_strtoul(p, &p, 16);
SMIMSG("%d,%s", pCfg.domain_0_prot, p);
p++;
pCfg.domain_1_prot = (unsigned int) simple_strtoul(p, &p, 16);
p++;
SMIMSG("%d", pCfg.domain_1_prot);
pCfg.domain_2_prot = (unsigned int) simple_strtoul(p, &p, 16);
p++;
SMIMSG("%d", pCfg.domain_2_prot);
pCfg.domain_3_prot = (unsigned int) simple_strtoul(p, &p, 16);
p++;
SMIMSG("%d", pCfg.domain_3_prot);
pCfg.start = (unsigned int) simple_strtoul(p, &p, 16);
p++;
SMIMSG("%d", pCfg.domain_0_prot);
pCfg.end = (unsigned int) simple_strtoul(p, &p, 16);
SMIMSG("prot=(%d,%d,%d,%d), start=0x%x, end=0x%x\n",
pCfg.domain_0_prot,pCfg.domain_1_prot,
pCfg.domain_2_prot,pCfg.domain_3_prot,
pCfg.start,pCfg.end);
spc_config(&pCfg);
}
if (0 == strncmp(opt, "spc_status", 10 ))
{
spc_status_check();
}
if (0 == strncmp(opt, "spc_dump_reg", 12 ))
{
spc_dump_reg();
}
if (0 == strncmp(opt, "touch_sysram", 10 ))
{
volatile unsigned int *va;
unsigned int i;
//va = ioremap_nocache(0x1200C000, 1024*80);
va=(volatile unsigned int *)0xf2000000;
for(i=0; i<1024*80/4; i++)
{
va[i] = i;
}
SMIMSG("cpu read sysram: 0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,0x%x",
va[0],va[1],va[2],va[3],va[100],va[222],va[444]);
}
if (0 == strncmp(opt, "set_reg:", 8 ))
{
unsigned int addr, val;
char *p = (char *)opt + 8;
addr = (unsigned int) simple_strtoul(p, &p, 16);
p++;
val = (unsigned int) simple_strtoul(p, &p, 16);
SMIMSG("set register: 0x%x = 0x%x\n", addr, val);
COM_WriteReg32(addr, val);
}
if (0 == strncmp(opt, "get_reg:", 8 ))
{
unsigned int addr;
char *p = (char *)opt + 8;
addr = (unsigned int) simple_strtoul(p, &p, 16);
SMIMSG("get register: 0x%x = 0x%x \n", addr, COM_ReadReg32(addr));
}
return;
Error:
SMIERR("parse command error!\n");
SMIMSG("%s", STR_HELP);
}
static int smi_bwc_config( MTK_SMI_BWC_CONFIG* p_conf )
{
int i;
unsigned wdata = 0;
unsigned threshold = 0;
unsigned int larb_base = gLarbBaseAddr[0];
/*turn on larb clock*/
for(i=0; i<SMI_LARB_NR; i++){
larb_clock_on(i, "SMI");
}
/*Bandwidth Limiter*/
switch( p_conf->scenario )
{
#if 0
case SMI_BWC_SCEN_VP1066:
wdata = 391; //BW limit = x/4096
wdata |= (1<<11); // bw filter enable
wdata |= (1<<12); // bw hard limit enable
M4U_WriteReg32( 0x0, REG_SMI_L1ARB1, wdata );
wdata = 1494; //BW limit
wdata |= (1<<11); // bw filter enable, soft mode
M4U_WriteReg32( 0x0, REG_SMI_L1ARB0, wdata );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_CTRL_EN, 0xfffff );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x00, 0x4 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x04, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x08, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x10, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x14, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x18, 0x2 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x1c, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x20, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x24, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x28, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x2c, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x30, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x34, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x38, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x3c, 0x1 );
break;
#endif
case SMI_BWC_SCEN_VR1066:
SMIMSG("set as SMI_BWC_SCEN_VR1066");
#if 0
wdata = 432; //BW limit = x/4096
wdata |= (1<<11); // bw filter enable
wdata |= (1<<12); // bw hard limit enable
M4U_WriteReg32( 0x0, REG_SMI_L1ARB1, wdata );
#else
wdata = 0;
threshold = 7;
wdata |= (1<<12); // bw hard limit enable
wdata |= (threshold<<13);
wdata |= (threshold<<18);
wdata |= (1<<23);
M4U_WriteReg32( 0x0, REG_SMI_L1ARB1, wdata );
#endif
wdata = 2026; //BW limit
wdata |= (1<<11); // bw filter enable, soft mode
M4U_WriteReg32( 0x0, REG_SMI_L1ARB0, wdata );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_CTRL_EN, 0xfffff );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x00, 0x6 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x04, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x08, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x10, 0x4 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x14, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x18, 0x2 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x1c, 0x3 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x20, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x24, 0x3 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x28, 0x3 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x2c, 0x3 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x30, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x34, 0x3 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x38, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x3c, 0x1 );
/*reduce command buffer*/
//if( p_conf->b_reduce_command_buffer )
{
/*SMI COMMON reduce command buffer*/
M4U_WriteReg32( 0x0, REG_SMI_L1LEN, 0xb );
M4U_WriteReg32( 0x0, REG_SMI_READ_FIFO_TH, 0x323 );
M4U_WriteReg32( 0x0, REG_SMI_M4U_TH, 0x10c85 );
}
break;
case SMI_BWC_SCEN_NORMAL:
default:
SMIMSG("set as SMI_BWC_SCEN_NORMAL");
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_CTRL_EN, 0x0 );
M4U_WriteReg32( 0x0, REG_SMI_L1ARB0, 0x0 ); //larb0 venc:default
M4U_WriteReg32( 0x0, REG_SMI_L1ARB1, 0x0 ); //larb1 vdec:default
{
/*SMI COMMON reduce command buffer*/
M4U_WriteReg32( 0x0, REG_SMI_L1LEN, 0x3 );
M4U_WriteReg32( 0x0, REG_SMI_READ_FIFO_TH, 0x320 );
M4U_WriteReg32( 0x0, REG_SMI_M4U_TH, 0x29ca7 );
}
break;
}
#if 0 /*dump message*/
{
#define _SMI_BC_DUMP_REG( _base_, _off_ ) \
SMIMSG( "[SMI_REG] %s + %s = 0x%08X !\n", #_base_, #_off_, M4U_ReadReg32( _base_, _off_ ) );
/*Bandwidth Limiter*/
_SMI_BC_DUMP_REG( 0x0, REG_SMI_L1ARB0 ); //larb0 venc
_SMI_BC_DUMP_REG( 0x0, REG_SMI_L1ARB1 ); //larb1 vdec
/*SMI COMMON reduce command buffer*/
_SMI_BC_DUMP_REG( 0x0, REG_SMI_L1LEN );
_SMI_BC_DUMP_REG( 0x0, REG_SMI_READ_FIFO_TH );
_SMI_BC_DUMP_REG( 0x0, REG_SMI_M4U_TH );
_SMI_BC_DUMP_REG( larb_base, SMI_LARB_OSTD_CTRL_EN);
for(i = 0; i<20; i++)
{
_SMI_BC_DUMP_REG( larb_base, SMI_LARB_OSTD_PORT+0x4*i);
}
/*SMI LARB reduce command buffer (RO register)*/
_SMI_BC_DUMP_REG( LARB0_BASE, 0x10 );
}
dump_smi_register();
#endif
/*turn off larb clock*/
for(i=0; i<SMI_LARB_NR; i++){
larb_clock_off(i, "SMI");
}
return 0;
}
void smi_dumpDebugMsg(void)
{
unsigned int u4Index;
unsigned int u4Base;
unsigned int u4Offset;
//SMI COMMON dump
SMIMSG("===SMI common reg dump===\n");
u4Base = SMI_COMMON_EXT_BASE;
u4Offset = 0x400;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x404;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x234;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x200;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x204;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x208;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x20C;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x210;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x230;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
//SMI LARB dump
for( u4Index=0 ; u4Index < SMI_LARB_NR ; u4Index++)
{
if(0 == u4Index)
{
// if((0 == clock_is_on(MT_CG_DISP0_SMI_LARB0)) || (0 == clock_is_on(MT_CG_DISP0_SMI_COMMON)))
if(0x3 & M4U_ReadReg32(0xF4000000 , 0x100))
{
SMIMSG("===SMI%d is off===\n" , u4Index);
continue;
}
}
else if(1 == u4Index)
{
// if(0 == clock_is_on(MT_CG_VDEC1_LARB))
if(0x1 & M4U_ReadReg32(0xF6000000 , 0x4))
{
SMIMSG("===SMI%d is off===\n" , u4Index);
continue;
}
}
else if(2 == u4Index)
{
// if(0 == clock_is_on(MT_CG_IMAGE_LARB2_SMI))
if(0x1 & M4U_ReadReg32(0xF5000000 , 0))
{
SMIMSG("===SMI%d is off===\n" , u4Index);
continue;
}
}
else
{
continue;
}
SMIMSG("===SMI%d reg dump===\n" , u4Index);
u4Base = gLarbBaseAddr[u4Index];
u4Offset = 0;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x10;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x450;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x454;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x600;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x604;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x610;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x614;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
for(u4Offset = 0x200; u4Offset < 0x244 ; u4Offset += 4)
{
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
}
}
}
static long smi_ioctl( struct file * pFile,
unsigned int cmd,
unsigned long param)
{
int ret = 0;
// unsigned long * pu4Cnt = (unsigned long *)pFile->private_data;
switch (cmd)
{
#ifdef __MAU_SPC_ENABLE__
case MTK_CONFIG_MM_MAU:
{
MTK_MAU_CONFIG b;
if(copy_from_user(&b, (void __user *)param, sizeof(b)))
{
SMIERR("copy_from_user failed!");
ret = -EFAULT;
} else {
mau_config(&b);
}
return ret;
}
case MTK_IOC_SPC_CONFIG :
{
MTK_SPC_CONFIG cfg;
ret = copy_from_user(&cfg, (void*)param , sizeof(MTK_SPC_CONFIG));
if(ret)
{
SMIMSG(" SPC_CONFIG, copy_from_user failed: %d\n", ret);
return -EFAULT;
}
spc_config(&cfg);
}
break;
case MTK_IOC_SPC_DUMP_REG :
spc_dump_reg();
break;
case MTK_IOC_SPC_DUMP_STA :
spc_status_check();
break;
case MTK_IOC_SPC_CMD :
spc_test(param);
break;
#endif
case MTK_IOC_SMI_BWC_CONFIG:
{
MTK_SMI_BWC_CONFIG cfg;
ret = copy_from_user(&cfg, (void*)param , sizeof(MTK_SMI_BWC_CONFIG));
if(ret)
{
SMIMSG(" SMI_BWC_CONFIG, copy_from_user failed: %d\n", ret);
return -EFAULT;
}
// ret = smi_bwc_config( &cfg , pu4Cnt);
ret = smi_bwc_config( &cfg , NULL);
}
break;
// GMP start
case MTK_IOC_SMI_BWC_INFO_SET:
{
MTK_SMI_BWC_INFO_SET cfg;
SMIMSG("Handle MTK_IOC_SMI_BWC_INFO_SET request... start");
ret = copy_from_user(&cfg, (void*)param , sizeof(MTK_SMI_BWC_INFO_SET));
if(ret)
{
SMIMSG(" MTK_IOC_SMI_BWC_INFO_SET, copy_to_user failed: %d\n", ret);
return -EFAULT;
}
// Set the address to the value assigned by user space program
smi_bwc_mm_info_set(cfg.property, cfg.value1, cfg.value2);
SMIMSG("Handle MTK_IOC_SMI_BWC_INFO_SET request... finish");
break;
}
case MTK_IOC_SMI_BWC_INFO_GET:
{
MTK_SMI_BWC_INFO_GET cfg;
MTK_SMI_BWC_MM_INFO * return_address = NULL;
SMIMSG("Handle MTK_IOC_SMI_BWC_INFO_GET request... start");
ret = copy_from_user(&cfg, (void*)param , sizeof(MTK_SMI_BWC_INFO_GET));
if(ret)
{
SMIMSG(" MTK_IOC_SMI_BWC_INFO_GET, copy_to_user failed: %d\n", ret);
return -EFAULT;
}
return_address = (MTK_SMI_BWC_MM_INFO *)cfg.return_address;
if( return_address != NULL){
ret = copy_to_user((void*) return_address, (void*)&g_smi_bwc_mm_info, sizeof(MTK_SMI_BWC_MM_INFO));
if(ret)
{
SMIMSG(" MTK_IOC_SMI_BWC_INFO_GET, copy_to_user failed: %d\n", ret);
return -EFAULT;
}
}
SMIMSG("Handle MTK_IOC_SMI_BWC_INFO_GET request... finish");
break;
}
// GMP end
default:
return -1;
}
return ret;
}
int larb_reg_restore(int larb)
{
unsigned int regval,regval1,regval2;
unsigned int larb_base = gLarbBaseAddr[larb];
/*
unsigned int* pReg = pLarbRegBackUp[larb];
int i;
//warning: larb_con is controlled by set/clr
regval = *(pReg++);
M4U_WriteReg32(larb_base, SMI_LARB_CON_CLR, ~(regval));
M4U_WriteReg32(larb_base, SMI_LARB_CON_SET, (regval));
M4U_WriteReg32(larb_base, SMI_SHARE_EN, *(pReg++) );
M4U_WriteReg32(larb_base, SMI_ROUTE_SEL, *(pReg++) );
for(i=0; i<3; i++)
{
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_START(i), *(pReg++));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_END(i), *(pReg++));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_GID(i), *(pReg++));
}
*/
//Clock manager enable LARB clock before call back restore already, it will be disabled after restore call back returns
//Got to enable OSTD before engine starts
regval = M4U_ReadReg32(larb_base , SMI_LARB_STAT);
regval1 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ0);
regval2 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ1);
if(0 == regval)
{
int retry_count = 0;
SMIMSG("Init OSTD for larb_base: 0x%x\n" , larb_base);
// Write 0x60 = 0xFFFF_FFFF, enable BW limiter
M4U_WriteReg32(larb_base , 0x60 , 0xffffffff);
// Polling 0x600 = 0xaaaa
for(retry_count= 0; retry_count<64; retry_count++)
{
if(M4U_ReadReg32(larb_base , 0x600) == 0xaaaa)
{
//Step3. Once it is found 0x600 == 0xaaaa, we can start to enable outstanding limiter and set outstanding limit
break;
}
SMIMSG("Larb: 0x%x busy : waiting for idle\n" , larb_base);
udelay(500);
}
// Write 0x60 = 0x0, disable BW limiter
M4U_WriteReg32(larb_base , 0x60 , 0x0);
// enable ISTD
M4U_WriteReg32(larb_base , SMI_LARB_OSTD_CTRL_EN , 0xffffffff);
}
else
{
SMIMSG("Larb%d is busy : 0x%x , port:0x%x,0x%x ,fail to set OSTD\n" , larb , regval , regval1 , regval2);
smi_dumpDebugMsg();
SMIERR("DISP_MDP LARB%d OSTD cannot be set:0x%x,port:0x%x,0x%x\n" , larb , regval , regval1 , regval2);
}
if(0 == g_bInited)
{
initSetting();
g_bInited = 1;
SMIMSG("SMI init\n");
}
// Show SMI always on register when larb 0 is enable
if(larb == 0){
SMIMSG("===SMI always on reg dump===\n");
SMIMSG("[0x5C0,0x5C4,0x5C8]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5C0),M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5C4),M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5C8));
SMIMSG("[0x5CC,0x5D0]=[0x%x,0x%x]\n" ,M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5CC),M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5D0));
}
return 0;
}
static int smi_bwc_config( MTK_SMI_BWC_CONFIG* p_conf , unsigned long * pu4LocalCnt)
{
int i;
unsigned long u4Concurrency = 0;
MTK_SMI_BWC_SCEN eFinalScen;
static MTK_SMI_BWC_SCEN ePreviousFinalScen = SMI_BWC_SCEN_CNT;
if((SMI_BWC_SCEN_CNT <= p_conf->scenario) || (0 > p_conf->scenario))
{
SMIERR("Incorrect SMI BWC config : 0x%x, how could this be...\n" , p_conf->scenario);
return -1;
}
//Debug - S
//SMIMSG("SMI setTo%d,%s,%d\n" , p_conf->scenario , (p_conf->b_on_off ? "on" : "off") , ePreviousFinalScen);
//Debug - E
spin_lock(&g_SMIInfo.SMI_lock);
if(p_conf->b_on_off)
{
//turn on certain scenario
g_SMIInfo.pu4ConcurrencyTable[p_conf->scenario] += 1;
if(NULL != pu4LocalCnt)
{
pu4LocalCnt[p_conf->scenario] += 1;
}
}
else
{
//turn off certain scenario
if(0 == g_SMIInfo.pu4ConcurrencyTable[p_conf->scenario])
{
SMIMSG("Too many turning off for global SMI profile:%d,%d\n" , p_conf->scenario , g_SMIInfo.pu4ConcurrencyTable[p_conf->scenario]);
}
else
{
g_SMIInfo.pu4ConcurrencyTable[p_conf->scenario] -= 1;
}
if(NULL != pu4LocalCnt)
{
if(0 == pu4LocalCnt[p_conf->scenario])
{
SMIMSG("Process : %s did too many turning off for local SMI profile:%d,%d\n" , current->comm ,p_conf->scenario , pu4LocalCnt[p_conf->scenario]);
}
else
{
pu4LocalCnt[p_conf->scenario] -= 1;
}
}
}
for(i=0 ; i < SMI_BWC_SCEN_CNT ; i++)
{
if(g_SMIInfo.pu4ConcurrencyTable[i])
{
u4Concurrency |= (1 << i);
}
}
if((1 << SMI_BWC_SCEN_VR) & u4Concurrency)
{
eFinalScen = SMI_BWC_SCEN_VR;
}
else if((1 << SMI_BWC_SCEN_VP) & u4Concurrency)
{
eFinalScen = SMI_BWC_SCEN_VP;
}
else
{
eFinalScen = SMI_BWC_SCEN_NORMAL;
}
if(ePreviousFinalScen == eFinalScen)
{
SMIMSG("Scen equal%d,don't change\n" , eFinalScen);
spin_unlock(&g_SMIInfo.SMI_lock);
return 0;
}
else
{
ePreviousFinalScen = eFinalScen;
}
/*turn on larb clock*/
for( i=0 ; i < SMI_LARB_NR ; i++){
larb_clock_on(i);
}
/*Bandwidth Limiter*/
switch( eFinalScen )
{
case SMI_BWC_SCEN_VP:
SMIMSG( "[SMI_PROFILE] : %s\n", "SMI_BWC_VP");
#if 1
M4U_WriteReg32(REG_SMI_M4U_TH , 0 , ((0x2 << 15) + (0x3 << 10) + (0x4 << 5) + 0x5));// 2 non-ultra write, 3 write command , 4 non-ultra read , 5 ultra read
M4U_WriteReg32(REG_SMI_L1LEN , 0 , 0xB);//Level 1 LARB, apply new outstanding control method, 1/4 bandwidth limiter overshoot control , enable warb channel
M4U_WriteReg32(REG_SMI_READ_FIFO_TH , 0 , 0xC8F);//total 8 commnads between smi common to M4U, 12 non ultra commands between smi common to M4U, 1 commnads can in write AXI slice for all LARBs
M4U_WriteReg32(REG_SMI_L1ARB0 , 0 , 0xC57);//1111/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB1 , 0 , 0x9F7);//503/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB2 , 0 , 0x961);//353/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB3 , 0 , 0x885A25);//549/4096 maximum grant counts, hard limiter, 2 read 2 write outstanding limit
M4U_WriteReg32(LARB0_BASE , 0x200 , 0x8);//OVL
M4U_WriteReg32(LARB0_BASE , 0x204 , 0x8);//RDMA
M4U_WriteReg32(LARB0_BASE , 0x208 , 0x3);//WDMA
M4U_WriteReg32(LARB0_BASE , 0x20C , 0x1);//CMDQ
M4U_WriteReg32(LARB0_BASE , 0x210 , 0x2);//MDP_RDMA
M4U_WriteReg32(LARB0_BASE , 0x214 , 0x1);//MDP_WDMA
M4U_WriteReg32(LARB0_BASE , 0x218 , 0x4);//MDP_ROTO
M4U_WriteReg32(LARB0_BASE , 0x21C , 0x2);//MDP_ROTCO
M4U_WriteReg32(LARB0_BASE , 0x220 , 0x2);//MDP_ROTVO
M4U_WriteReg32(LARB1_BASE , 0x200 , 0x6);//MC
M4U_WriteReg32(LARB1_BASE , 0x204 , 0x2);//PP
M4U_WriteReg32(LARB1_BASE , 0x208 , 0x1);//AVC MV
M4U_WriteReg32(LARB1_BASE , 0x20C , 0x3);//RD
M4U_WriteReg32(LARB1_BASE , 0x210 , 0x3);//WR
M4U_WriteReg32(LARB1_BASE , 0x214 , 0x1);//VLD
M4U_WriteReg32(LARB1_BASE , 0x218 , 0x1);//PPWRAP
M4U_WriteReg32(LARB2_BASE , 0x200 , 0x1);//IMGO
M4U_WriteReg32(LARB2_BASE , 0x204 , 0x1);//IMG2O
M4U_WriteReg32(LARB2_BASE , 0x208 , 0x1);//LSCI
M4U_WriteReg32(LARB2_BASE , 0x20C , 0x1);//IMGI
M4U_WriteReg32(LARB2_BASE , 0x210 , 0x1);//ESFKO
M4U_WriteReg32(LARB2_BASE , 0x214 , 0x1);//AAO
M4U_WriteReg32(LARB2_BASE , 0x218 , 0x1);//JPG_RDMA
M4U_WriteReg32(LARB2_BASE , 0x21C , 0x1);//JPG_BSDMA
M4U_WriteReg32(LARB2_BASE , 0x220 , 0x2);//VENC_RD_COMV
M4U_WriteReg32(LARB2_BASE , 0x224 , 0x1);//VENC_SV_COMV
M4U_WriteReg32(LARB2_BASE , 0x228 , 0x4);//VENC_RCPU
M4U_WriteReg32(LARB2_BASE , 0x22C , 0x2);//VENC_REC_FRM
M4U_WriteReg32(LARB2_BASE , 0x230 , 0x2);//VENC_REF_LUMA
M4U_WriteReg32(LARB2_BASE , 0x234 , 0x1);//VENC_REF_CHROMA
M4U_WriteReg32(LARB2_BASE , 0x238 , 0x1);//VENC_BSDMA
M4U_WriteReg32(LARB2_BASE , 0x23C , 0x1);//VENC_CUR_LUMA
M4U_WriteReg32(LARB2_BASE , 0x240 , 0x1);//VENC_CUR_CHROMA
#endif
break;
case SMI_BWC_SCEN_VR:
SMIMSG( "[SMI_PROFILE] : %s\n", "SMI_BWC_VR");
#if 1
M4U_WriteReg32(REG_SMI_M4U_TH , 0 , ((0x2 << 15) + (0x3 << 10) + (0x4 << 5) + 0x5));// 2 non-ultra write, 3 write command , 4 non-ultra read , 5 ultra read
M4U_WriteReg32(REG_SMI_L1LEN , 0 , 0xB);//Level 1 LARB, apply new outstanding control method, 1/4 bandwidth limiter overshoot control , enable warb channel
M4U_WriteReg32(REG_SMI_READ_FIFO_TH , 0 , 0xC8F);//total 8 commnads between smi common to M4U, 12 non ultra commands between smi common to M4U, 1 commnads can in write AXI slice for all LARBs
M4U_WriteReg32(REG_SMI_L1ARB0 , 0 , 0xC57);//1111/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB1 , 0 , 0x9F7);//503/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB2 , 0 , 0xD4F);//1359/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB3 , 0 , 0x884912);// 274/4096 maximum grant counts, soft limiter, 2 read 2 write outstanding limit
M4U_WriteReg32(LARB0_BASE , 0x200 , 0x8);//OVL
M4U_WriteReg32(LARB0_BASE , 0x204 , 0x8);//RDMA
M4U_WriteReg32(LARB0_BASE , 0x208 , 0x1);//WDMA
M4U_WriteReg32(LARB0_BASE , 0x20C , 0x1);//CMDQ
M4U_WriteReg32(LARB0_BASE , 0x210 , 0x2);//MDP_RDMA
M4U_WriteReg32(LARB0_BASE , 0x214 , 0x2);//MDP_WDMA
M4U_WriteReg32(LARB0_BASE , 0x218 , 0x2);//MDP_ROTO
M4U_WriteReg32(LARB0_BASE , 0x21C , 0x4);//MDP_ROTCO
M4U_WriteReg32(LARB0_BASE , 0x220 , 0x1);//MDP_ROTVO
M4U_WriteReg32(LARB1_BASE , 0x200 , 0x1);//MC
M4U_WriteReg32(LARB1_BASE , 0x204 , 0x1);//PP
M4U_WriteReg32(LARB1_BASE , 0x208 , 0x1);//AVC MV
M4U_WriteReg32(LARB1_BASE , 0x20C , 0x1);//RD
M4U_WriteReg32(LARB1_BASE , 0x210 , 0x1);//WR
M4U_WriteReg32(LARB1_BASE , 0x214 , 0x1);//VLD
M4U_WriteReg32(LARB1_BASE , 0x218 , 0x1);//PPWRAP
M4U_WriteReg32(LARB2_BASE , 0x200 , 0x6);//IMGO
M4U_WriteReg32(LARB2_BASE , 0x204 , 0x1);//IMG2O
M4U_WriteReg32(LARB2_BASE , 0x208 , 0x1);//LSCI
M4U_WriteReg32(LARB2_BASE , 0x20C , 0x4);//IMGI
M4U_WriteReg32(LARB2_BASE , 0x210 , 0x1);//ESFKO
M4U_WriteReg32(LARB2_BASE , 0x214 , 0x1);//AAO
M4U_WriteReg32(LARB2_BASE , 0x218 , 0x1);//JPG_RDMA
M4U_WriteReg32(LARB2_BASE , 0x21C , 0x1);//JPG_BSDMA
M4U_WriteReg32(LARB2_BASE , 0x220 , 0x1);//VENC_RD_COMV
M4U_WriteReg32(LARB2_BASE , 0x224 , 0x1);//VENC_SV_COMV
M4U_WriteReg32(LARB2_BASE , 0x228 , 0x1);//VENC_RCPU
M4U_WriteReg32(LARB2_BASE , 0x22C , 0x2);//VENC_REC_FRM
M4U_WriteReg32(LARB2_BASE , 0x230 , 0x4);//VENC_REF_LUMA
M4U_WriteReg32(LARB2_BASE , 0x234 , 0x2);//VENC_REF_CHROMA
M4U_WriteReg32(LARB2_BASE , 0x238 , 0x1);//VENC_BSDMA
M4U_WriteReg32(LARB2_BASE , 0x23C , 0x2);//VENC_CUR_LUMA
M4U_WriteReg32(LARB2_BASE , 0x240 , 0x1);//VENC_CUR_CHROMA
#endif
break;
case SMI_BWC_SCEN_NORMAL:
SMIMSG( "[SMI_PROFILE] : %s\n", "SMI_BWC_SCEN_NORMAL");
initSetting();
default:
break;
}
/*turn off larb clock*/
for(i = 0 ; i < SMI_LARB_NR ; i++){
larb_clock_off(i);
}
spin_unlock(&g_SMIInfo.SMI_lock);
SMIMSG("ScenTo:%d,turn %s,Curr Scen:%d,%d,%d,%d\n" , p_conf->scenario , (p_conf->b_on_off ? "on" : "off") , eFinalScen ,
g_SMIInfo.pu4ConcurrencyTable[SMI_BWC_SCEN_NORMAL] , g_SMIInfo.pu4ConcurrencyTable[SMI_BWC_SCEN_VR] , g_SMIInfo.pu4ConcurrencyTable[SMI_BWC_SCEN_VP]);
//Debug usage - S
//smi_dumpDebugMsg();
//SMIMSG("Config:%d,%d,%d\n" , eFinalScen , g_SMIInfo.pu4ConcurrencyTable[SMI_BWC_SCEN_NORMAL] , (NULL == pu4LocalCnt ? (-1) : pu4LocalCnt[p_conf->scenario]));
//Debug usage - E
return 0;
}
// callback before larb clock is disabled
void on_larb_power_off(struct larb_monitor *h, int larb_idx)
{
SMIMSG("on_larb_power_off(), larb_idx=%d \n", larb_idx);
larb_reg_backup(larb_idx);
}
static long smi_ioctl( struct file * pFile,
unsigned int cmd,
unsigned long param)
{
int ret = 0;
// unsigned long * pu4Cnt = (unsigned long *)pFile->private_data;
switch (cmd)
{
#ifdef __MAU_SPC_ENABLE__
case MTK_CONFIG_MM_MAU:
{
MTK_MAU_CONFIG b;
if(copy_from_user(&b, (void __user *)param, sizeof(b)))
{
SMIERR("copy_from_user failed!");
ret = -EFAULT;
} else {
mau_config(&b);
}
return ret;
}
case MTK_IOC_SPC_CONFIG :
{
MTK_SPC_CONFIG cfg;
ret = copy_from_user(&cfg, (void*)param , sizeof(MTK_SPC_CONFIG));
if(ret)
{
SMIMSG(" SPC_CONFIG, copy_from_user failed: %d\n", ret);
return -EFAULT;
}
spc_config(&cfg);
}
break;
case MTK_IOC_SPC_DUMP_REG :
spc_dump_reg();
break;
case MTK_IOC_SPC_DUMP_STA :
spc_status_check();
break;
case MTK_IOC_SPC_CMD :
spc_test(param);
break;
#endif
case MTK_IOC_SMI_BWC_CONFIG:
{
MTK_SMI_BWC_CONFIG cfg;
ret = copy_from_user(&cfg, (void*)param , sizeof(MTK_SMI_BWC_CONFIG));
if(ret)
{
SMIMSG(" SMI_BWC_CONFIG, copy_from_user failed: %d\n", ret);
return -EFAULT;
}
// ret = smi_bwc_config( &cfg , pu4Cnt);
ret = smi_bwc_config( &cfg , NULL);
}
break;
default:
return -1;
}
return ret;
}
