int bus_minfreq_handle(unsigned int req_value) { unsigned int reg_val; void __iomem *reg_addr; if(DFS_BUS_FREQ_MIN >= req_value) { reg_addr = (void __iomem *)HISI_VA_ADDRESS(SOC_AO_SCTRL_SC_MCU_VOTE1DIS_ADDR(SOC_AO_SCTRL_BASE_ADDR)); /*set SC_MCU_VOTE1DIS bit,vote lock,enable bus150M dfs*/ reg_val = readl(reg_addr); writel((reg_val | BIT(BUS_DFS_BIT_ACPU)), reg_addr); } else { reg_addr = (void __iomem *)HISI_VA_ADDRESS(SOC_AO_SCTRL_SC_MCU_VOTE1EN_ADDR(SOC_AO_SCTRL_BASE_ADDR)); /*set SC_MCU_VOTE1EN bit,vote unlock,disable bus150M dfs*/ reg_val = readl(reg_addr); writel((reg_val | BIT(BUS_DFS_BIT_ACPU)), reg_addr); } return RET_OK; }
/***************************************************************************** 2 全局变量定义 *****************************************************************************/ u32_t g_aAcpuStoreReg[PWC_STORE_MEM_SIZE] = {0}; u32_t g_aAcpuHwVoteBaseAddr[] = { #if defined(CHIP_BB_HI6210)/*B020 Modify*/ IO_ADDRESS(SOC_AO_SCTRL_SC_MCPU_VOTEEN_ADDR(SOC_AO_SCTRL_BASE_ADDR)), IO_ADDRESS(SOC_AO_SCTRL_SC_PERI_VOTEEN_ADDR(SOC_AO_SCTRL_BASE_ADDR)), IO_ADDRESS(SOC_AO_SCTRL_SC_ACPU_VOTEEN_ADDR(SOC_AO_SCTRL_BASE_ADDR)), IO_ADDRESS(SOC_AO_SCTRL_SC_MCU_VOTEEN_ADDR(SOC_AO_SCTRL_BASE_ADDR)), IO_ADDRESS(SOC_AO_SCTRL_SC_MCU_VOTE1EN_ADDR(SOC_AO_SCTRL_BASE_ADDR)), IO_ADDRESS(SOC_AO_SCTRL_SC_MCU_VOTE2EN_ADDR(SOC_AO_SCTRL_BASE_ADDR)), #else IO_ADDRESS(SOC_AO_SCTRL_SC_MCPU_VOTEEN0_ADDR(SOC_SC_ON_BASE_ADDR)), IO_ADDRESS(SOC_AO_SCTRL_SC_PERI_VOTEEN0_ADDR(SOC_SC_ON_BASE_ADDR)), IO_ADDRESS(SOC_AO_SCTRL_SC_ACPU_VOTEEN0_ADDR(SOC_SC_ON_BASE_ADDR)), IO_ADDRESS(SOC_AO_SCTRL_SC_MCU_VOTEEN0_ADDR(SOC_SC_ON_BASE_ADDR)), IO_ADDRESS(SOC_AO_SCTRL_SC_MCU_VOTE1EN0_ADDR(SOC_SC_ON_BASE_ADDR)), IO_ADDRESS(SOC_AO_SCTRL_SC_MCU_VOTE2EN0_ADDR(SOC_SC_ON_BASE_ADDR)), #endif }; ST_STORE_REG_ADDR_INFO g_aAcpuSocRegTable[] = { #if defined(CHIP_BB_HI6210)