/*****************************************************************************
function name : mali_dfs_to_profile
description : doing dfs action to target profile
input vars : u32 curr
output vars : NA
return value : int
calls :
called :
history :
1.data : 07/05/2014
author : s00250033
modify : new
*****************************************************************************/
int mali_dfs_set_pll(int target)
{
u32 i = 0;
u32 ret = 0;
if (g_mali_dvfs_profile[target].pllNum != g_mali_dvfs_profile[g_mali_dfs_var.dfs_CurrPrf].pllNum)
{
if (g_mali_dvfs_profile[target].freq > MAX_SFT_FREQ) //ASIC下，GPU频率至少100M
{
phy_reg_writel(SOC_MEDIA_SCTRL_BASE_ADDR,SOC_MEDIA_SCTRL_SC_MEDIA_CLKCFG2_ADDR(0),0,31,DVFS_FREQ_DIV(6));
for (i = 0; i < MAX_CUNT; i++)
{
ret = phy_reg_readl(SOC_MEDIA_SCTRL_BASE_ADDR, SOC_MEDIA_SCTRL_SC_MEDIA_CLKCFG2_ADDR(0), 8, 11);
if (MID_DIV == ret)
{
break;
}
udelay(1);
}
if (MAX_CUNT == i)
{
MALI_DEBUG_PRINT(1,("mali dfs: ERROR! set mid div %d failed! Current div is %d!\n", g_mali_dvfs_profile[target].div, ret));
return -1;
}
}
phy_reg_writel(SOC_MEDIA_SCTRL_BASE_ADDR,SOC_MEDIA_SCTRL_SC_MEDIA_SUBSYS_CTRL5_ADDR(0),1,1,g_mali_dvfs_profile[target].pllNum);
}
return 0;
}
static void mali_platform_powerup_no_drv(void)
{
MALI_DEBUG_PRINT(2, ("mali_platform_powerup_no_drv start!\n"));
phy_reg_writel(SOC_AO_SCTRL_BASE_ADDR,SOC_AO_SCTRL_SC_PW_MTCMOS_EN0_ADDR(0),1,1,1);
phy_reg_writel(SOC_PERI_SCTRL_BASE_ADDR,SOC_PERI_SCTRL_SC_PERIPH_CLKEN12_ADDR(0),0,31,0x400);
phy_reg_writel(SOC_PMCTRL_BASE_ADDR,SOC_PMCTRL_GPUPLLCTRL_ADDR(0),0,31,0x7801);
phy_reg_writel(SOC_PMCTRL_BASE_ADDR,SOC_PMCTRL_SYSPLLCTRL_ADDR(0),0,31,0x7801);
phy_reg_writel(SOC_PMCTRL_BASE_ADDR,SOC_PMCTRL_MEDPLLCTRL_ADDR(0),0,31,0x7801);
phy_reg_writel(SOC_MEDIA_SCTRL_BASE_ADDR,SOC_MEDIA_SCTRL_SC_MEDIA_CLKCFG2_ADDR(0),0,31,0x8100);
phy_reg_writel(SOC_MEDIA_SCTRL_BASE_ADDR,SOC_MEDIA_SCTRL_SC_MEDIA_CLKCFG0_ADDR(0),0,31,0x84);//0x84
phy_reg_writel(SOC_AO_SCTRL_BASE_ADDR,SOC_AO_SCTRL_SC_PW_RSTDIS0_ADDR(0),1,1,1);
phy_reg_writel(SOC_AO_SCTRL_BASE_ADDR,SOC_AO_SCTRL_SC_PW_ISODIS0_ADDR(0),1,1,1);
phy_reg_writel(SOC_AO_SCTRL_BASE_ADDR,SOC_AO_SCTRL_SC_PW_CLKEN0_ADDR(0),1,1,1);
phy_reg_writel(SOC_MEDIA_SCTRL_BASE_ADDR,SOC_MEDIA_SCTRL_SC_MEDIA_RSTDIS_ADDR(0),0,0,1);
phy_reg_writel(SOC_MEDIA_SCTRL_BASE_ADDR,SOC_MEDIA_SCTRL_SC_MEDIA_CLKEN_ADDR(0),0,31,0x20002);
MALI_DEBUG_PRINT(2, ("mali_platform_powerup_no_drv end!\n"));
}
int mali_dfs_set_div(int target)
{
u32 i = 0;
u32 ret = 0;
mali_reg_writel(gp_mali_soc_addr_table->soc_media_sctrl_base_addr,SOC_MEDIA_SCTRL_SC_MEDIA_CLKCFG2_ADDR(0),0,31,DVFS_FREQ_DIV(g_mali_dvfs_profile[target].div));
for (i = 0; i < MAX_CUNT; i++)
{
ret = mali_reg_readl(gp_mali_soc_addr_table->soc_media_sctrl_base_addr, SOC_MEDIA_SCTRL_SC_MEDIA_CLKCFG2_ADDR(0), 8, 11);
if (g_mali_dvfs_profile[target].div == ret)
{
return 0;
}
udelay(1);
}
MALI_DEBUG_PRINT(1,("mali dfs: ERROR! target %d set div %d failed! Current div is %d!\n", target,g_mali_dvfs_profile[target].div, ret));
return -1;
}
/*****************************************************************************
function name : init_mali_clock_regulator
description : mali clk and regulator init
input vars : void
output vars : NA
return value : mali_bool
calls : mali_clk_get
called : mali_platform_init
history :
1.data : 04/03/2014
author : s00250033
modify : new
*****************************************************************************/
static mali_bool init_mali_clock_regulator(struct platform_device *pdev)
{
mali_bool ret = MALI_TRUE;
g_swGpuPowerState = MALI_TRUE;
/* regulator init */
mali_regulator = regulator_get(&pdev->dev, "G3D_PD_VDD");
if (IS_ERR(mali_regulator))
{
MALI_PRINT( ("MALI Error : failed to get G3D_PD_VDD\n"));
return MALI_FALSE;
}
mali_regulator_enable();
/* clk init */
if (mali_clock != 0)
{
return ret;
}
if (!mali_clk_get(pdev))
{
MALI_PRINT(("MALI Error: Failed to get Mali clock\n"));
return MALI_FALSE;
}
/*使能媒体外设时钟*/
ret = phy_reg_readl(SOC_PERI_SCTRL_BASE_ADDR, SOC_PERI_SCTRL_SC_PERIPH_CLKSTAT12_ADDR(0), 10, 10);
if(1 != ret)
{
phy_reg_writel(SOC_PERI_SCTRL_BASE_ADDR,SOC_PERI_SCTRL_SC_PERIPH_CLKEN12_ADDR(0),10,10,1);
ret = phy_reg_readl(SOC_PERI_SCTRL_BASE_ADDR, SOC_PERI_SCTRL_SC_PERIPH_CLKSTAT12_ADDR(0), 10, 10);
if(1 != ret)
{
MALI_DEBUG_PRINT(2, (" error: SET SC_PERIPH_CLKEN12 failed!\n"));
}
}
/* CLK on and set rate */
mali_clock_on();
MALI_DEBUG_PRINT(2, (" init mali clock regulator ok\n"));
/*时钟有效指示*/
phy_reg_writel(SOC_MEDIA_SCTRL_BASE_ADDR,SOC_MEDIA_SCTRL_SC_MEDIA_CLKCFG2_ADDR(0),15,15,1);
ret = phy_reg_readl(SOC_MEDIA_SCTRL_BASE_ADDR, SOC_MEDIA_SCTRL_SC_MEDIA_CLKCFG2_ADDR(0), 15, 15);
if(1 != ret)
{
MALI_DEBUG_PRINT(2, (" error: SET SC_MEDIA_CLKCFG2 failed!\n"));
}
mali_domain_powerup_finish();
return MALI_TRUE;
}
