//*****************************************************************************
//
//! \brief xspi 004 test of SPI interrupt register.
//!
//! \return None.
//
//*****************************************************************************
static void xspi004_IntRegister_test(void)
{
unsigned long i, j, ulRegVal;
for(i = 0; i < 2; i++)
{
for(j = 0; j < 3; j++)
{
SPIIntEnable(ulSPI[i],ulIntFlags[j]);
ulRegVal = xHWREGB(ulSPI[i] + SPI_C1) & (ulIntFlags[j] << 4);
TestAssert(ulRegVal == (unsigned char)(ulIntFlags[j] << 4), "xspi API error!");
}
for(j = 3; j < 5; j++)
{
SPIIntEnable(ulSPI[i], ulIntFlags[j]);
ulRegVal = xHWREGB(ulSPI[i] + SPI_C2) & (ulIntFlags[j] << 4);
TestAssert(ulRegVal == (unsigned char)(ulIntFlags[j] << 4), "xspi API error!");
}
for(j = 0; j < 3; j++)
{
SPIIntDisable(ulSPI[i],ulIntFlags[j]);
ulRegVal = xHWREGB(ulSPI[i] + SPI_C1) & (ulIntFlags[j] << 4);
TestAssert(ulRegVal == 0, "xspi API error!");
}
for(j = 3; j < 5; j++)
{
SPIIntDisable(ulSPI[i],ulIntFlags[j]);
ulRegVal = xHWREGB(ulSPI[i] + SPI_C2) & (ulIntFlags[j] << 4);
TestAssert(ulRegVal == 0, "xspi API error!");
}
}
}
static void FlashPageProgram(volatile char *pVrf_Data)
{
volatile char pageProgram[260] = {0};
unsigned int buffLength = 0;
unsigned int index = 0;
volatile char dummy;
/* Set the first 4 bytes of pageProgram with SPI Flash Page
** Program Sequence instructions
*/
pageProgram[0] = SPI_FLASH_PAGE_WRITE;
pageProgram[1] = SPI_FLASH_ADDR_MSB1;
pageProgram[2] = SPI_FLASH_ADDR_MSB0;
pageProgram[3] = SPI_FLASH_ADDR_LSB;
/* Set the remaining bytes of pageProgram with 256 bytes of data */
for(index = 4; index < 260; index++)
{
pageProgram[index] = 259 - index;
pVrf_Data[index] = 259 - index;
}
buffLength = index;
/* Configure the PaRAM registers in EDMA for Transmission.*/
SpiTxEdmaParamSet(EDMA3_CHA_SPI1_TX, EDMA3_CHA_SPI1_TX, pageProgram, buffLength);
/* Registering Callback Function for Transmission. */
cb_Fxn[EDMA3_CHA_SPI1_TX] = &callback;
/* Configure the PaRAM registers in EDMA for Reception.*/
SpiRxEdmaParamSet(EDMA3_CHA_SPI1_RX, EDMA3_CHA_SPI1_RX, &dummy, buffLength, FALSE);
/* Registering Callback Function for Reception. */
cb_Fxn[EDMA3_CHA_SPI1_RX] = &callback;
/* Assert the CSHOLD line corresponding to the SPI Flash. */
CSHoldAssert();
/* Enable SPI controller to generate DMA events */
SPIIntEnable(SOC_SPI_1_REGS, SPI_DMA_REQUEST_ENA_INT);
/* Wait until both the flags are set to 1 in the callback function. */
while((0 == flagTx) || (0 == flagRx));
flagTx = 0;
flagRx = 0;
/* Deassert the CSHOLD line corresponding to the SPI Flash. */
CSHoldDeassert();
/* Wait until the previous write to the SPI Flash if completed. */
IsWriteInProgress();
}
static void ReadFromFlash(volatile char *pReadFlash)
{
volatile char writeFlash[260] = {0};
unsigned int buffLength = 0;
unsigned int index = 0;
/* Set the first 4 bytes of writeFlash with SPI Flash Read
** Instruction Sequence.
*/
writeFlash[0] = SPI_FLASH_READ;
writeFlash[1] = SPI_FLASH_ADDR_MSB1;
writeFlash[2] = SPI_FLASH_ADDR_MSB0;
writeFlash[3] = SPI_FLASH_ADDR_LSB;
/*
** Initializing the remaining bytes of transmit array to zero.
** These are dummy bytes and are transmitted at times when the
** focus will be on receiving data.
*/
for(index = 4; index < 260; index++)
{
writeFlash[index] = 0;
}
buffLength = index;
/* Configure the PaRAM registers in EDMA for Transmission.*/
SpiTxEdmaParamSet(EDMA3_CHA_SPI1_TX, EDMA3_CHA_SPI1_TX, writeFlash, buffLength);
/* Registering Callback Function for Transmission. */
cb_Fxn[EDMA3_CHA_SPI1_TX] = &callback;
/* Configure the PaRAM registers in EDMA for Reception.*/
SpiRxEdmaParamSet(EDMA3_CHA_SPI1_RX, EDMA3_CHA_SPI1_RX, pReadFlash, buffLength, TRUE);
/* Registering Callback Function for Reception. */
cb_Fxn[EDMA3_CHA_SPI1_RX] = &callback;
/* Assert the CSHOLD line corresponding to the SPI Flash. */
CSHoldAssert();
/* Enable SPI controller to generate DMA events */
SPIIntEnable(SOC_SPI_1_REGS, SPI_DMA_REQUEST_ENA_INT);
/* Wait until both the flags are set to 1 in the callback function. */
while((0 == flagTx) || (0 == flagRx));
flagTx = 0;
flagRx = 0;
/* Deassert the CSHOLD line corresponding to the SPI Flash. */
CSHoldDeassert();
}
void SPIIntCfg(SpiNum spiNum, SpiIntInfo *pIntInfo)
{
if ((spiNum > SpiNum_HSPI)
|| (NULL == pIntInfo)) {
return;
}
// Clear the interrupt source and disable all of the interrupt.
CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), 0x3FF);
SPIIntEnable(spiNum, pIntInfo->src);
os_printf("src=%x\r\n,isrFunc=%x", (pIntInfo->src << 5), pIntInfo->isrFunc);
//
ETS_SPI_INTR_ATTACH(pIntInfo->isrFunc, NULL);
// Enable isr
ETS_SPI_INTR_ENABLE();
}
static void FlashSectorErase(void)
{
volatile char sectorErase[4] = {0};
unsigned int buffLength = 4;
volatile char dummy;
sectorErase[0] = SPI_FLASH_SECTOR_ERASE;
sectorErase[1] = SPI_FLASH_ADDR_MSB1;
sectorErase[2] = SPI_FLASH_ADDR_MSB0;
sectorErase[3] = SPI_FLASH_ADDR_LSB;
/* Configure the PaRAM registers in EDMA for Transmission. */
SpiTxEdmaParamSet(EDMA3_CHA_SPI1_TX, EDMA3_CHA_SPI1_TX, sectorErase, buffLength);
/* Registering Callback Function for Transmission. */
cb_Fxn[EDMA3_CHA_SPI1_TX] = &callback;
/* Configure the PaRAM registers in EDMA for Reception. */
SpiRxEdmaParamSet(EDMA3_CHA_SPI1_RX, EDMA3_CHA_SPI1_RX, &dummy, buffLength, FALSE);
/* Registering Callback Function for Reception. */
cb_Fxn[EDMA3_CHA_SPI1_RX] = &callback;
/* Assert the CSHOLD line corresponding to the SPI Flash. */
CSHoldAssert();
/* Enable SPI controller to generate DMA events */
SPIIntEnable(SOC_SPI_1_REGS, SPI_DMA_REQUEST_ENA_INT);
/* Wait until both the flags are set to 1 in the callback function. */
while((0 == flagTx) || (0 == flagRx));
flagTx = 0;
flagRx = 0;
/* Deassert the CSHOLD line corresponding to the SPI Flash. */
CSHoldDeassert();
/* Wait until the previous write to the SPI Flash if completed. */
IsWriteInProgress();
}
static unsigned char FlashStatusRead(void)
{
volatile char writeFlash[2] = {0};
volatile char readFlash[2] = {0};
unsigned int buffLength = 0;
writeFlash[0] = SPI_FLASH_STATUS_RX;
writeFlash[1] = 0;
buffLength = 2;
/* Configure the PaRAM registers in EDMA for Transmission.*/
SpiTxEdmaParamSet(EDMA3_CHA_SPI1_TX, EDMA3_CHA_SPI1_TX, writeFlash, buffLength);
/* Registering Callback Function for Transmission. */
cb_Fxn[EDMA3_CHA_SPI1_TX] = &callback;
/* Configure the PaRAM registers in EDMA for Reception. */
SpiRxEdmaParamSet(EDMA3_CHA_SPI1_RX, EDMA3_CHA_SPI1_RX, readFlash, buffLength, TRUE);
/* Registering Callback Function for Reception. */
cb_Fxn[EDMA3_CHA_SPI1_RX] = &callback;
/* Assert the CSHOLD line corresponding to the SPI Flash. */
CSHoldAssert();
/* Enable SPI controller to generate DMA events */
SPIIntEnable(SOC_SPI_1_REGS, SPI_DMA_REQUEST_ENA_INT);
/* Wait until both the flags are set to 1 in the callback function. */
while((0 == flagTx) || (0 == flagRx));
flagTx = 0;
flagRx = 0;
/* Deassert the CSHOLD line corresponding to the SPI Flash. */
CSHoldDeassert();
return ((unsigned char)readFlash[1]);
}
static void WriteEnable(void)
{
unsigned int buffLength = 1;
volatile char writeEn;
volatile char dummy;
writeEn = SPI_FLASH_WRITE_EN;
/* Configure the PaRAM registers in EDMA for Transmission. */
SpiTxEdmaParamSet(EDMA3_CHA_SPI1_TX, EDMA3_CHA_SPI1_TX, &writeEn, buffLength);
/* Registering Callback Function for Transmission. */
cb_Fxn[EDMA3_CHA_SPI1_TX] = &callback;
/* Configure the PaRAM registers in EDMA for Reception. */
SpiRxEdmaParamSet(EDMA3_CHA_SPI1_RX, EDMA3_CHA_SPI1_RX, &dummy, buffLength, FALSE);
/* Registering Callback Function for Reception. */
cb_Fxn[EDMA3_CHA_SPI1_RX] = &callback;
/* Assert the CSHOLD line corresponding to the SPI Flash. */
CSHoldAssert();
/* Enable SPI controller to generate DMA events */
SPIIntEnable(SOC_SPI_1_REGS, SPI_DMA_REQUEST_ENA_INT);
/* Wait until both the flags are set to 1 in the callback function. */
while((0 == flagTx) || (0 == flagRx));
flagTx = 0;
flagRx = 0;
/* Deassert the CSHOLD line corresponding to the SPI Flash. */
CSHoldDeassert();
/* Wait until SPI Flash is enabled for writing. */
while (IsWriteEnabled() != TRUE);
}
/*!
\brief open spi communication port to be used for communicating with a SimpleLink device
Given an interface name and option flags, this function opens the spi communication port
and creates a file descriptor. This file descriptor can be used afterwards to read and
write data from and to this specific spi channel.
The SPI speed, clock polarity, clock phase, chip select and all other attributes are all
set to hardcoded values in this function.
\param ifName - points to the interface name/path. The interface name is an
optional attributes that the simple link driver receives
on opening the device. in systems that the spi channel is
not implemented as part of the os device drivers, this
parameter could be NULL.
\param flags - option flags
\return upon successful completion, the function shall open the spi channel and return
a non-negative integer representing the file descriptor.
Otherwise, -1 shall be returned
\sa spi_Close , spi_Read , spi_Write
\note
\warning
*/
Fd_t spi_Open(char *ifName, unsigned long flags)
{
unsigned long ulBase;
//NWP master interface
ulBase = LSPI_BASE;
//Enable MCSPIA2
PRCMPeripheralClkEnable(PRCM_LSPI,PRCM_RUN_MODE_CLK|PRCM_SLP_MODE_CLK);
//Disable Chip Select
SPICSDisable(ulBase);
//Disable SPI Channel
SPIDisable(ulBase);
// Reset SPI
SPIReset(ulBase);
//
// Configure SPI interface
//
SPIConfigSetExpClk(ulBase,PRCMPeripheralClockGet(PRCM_LSPI),
SPI_IF_BIT_RATE,SPI_MODE_MASTER,SPI_SUB_MODE_0,
(SPI_SW_CTRL_CS |
SPI_4PIN_MODE |
SPI_TURBO_OFF |
SPI_CS_ACTIVEHIGH |
SPI_WL_32));
if(PRCMPeripheralStatusGet(PRCM_UDMA))
{
g_ucDMAEnabled = (HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0x0) ? 1 : 0;
}
else
{
g_ucDMAEnabled = 0;
}
#ifdef SL_CPU_MODE
g_ucDMAEnabled = 0;
#endif
if(g_ucDMAEnabled)
{
memset(g_ucDinDout,0xFF,sizeof(g_ucDinDout));
//g_ucDout[0]=0xFF;
//Simplelink_UDMAInit();
// Set DMA channel
cc_UDMAChannelSelect(UDMA_CH12_LSPI_RX);
cc_UDMAChannelSelect(UDMA_CH13_LSPI_TX);
SPIFIFOEnable(ulBase,SPI_RX_FIFO);
SPIFIFOEnable(ulBase,SPI_TX_FIFO);
SPIDmaEnable(ulBase,SPI_RX_DMA);
SPIDmaEnable(ulBase,SPI_TX_DMA);
SPIFIFOLevelSet(ulBase,1,1);
#if defined(SL_PLATFORM_MULTI_THREADED)
osi_InterruptRegister(INT_LSPI, (P_OSI_INTR_ENTRY)DmaSpiSwIntHandler,INT_PRIORITY_LVL_1);
SPIIntEnable(ulBase,SPI_INT_EOW);
osi_MsgQCreate(&DMAMsgQ,"DMAQueue",sizeof(int),1);
#else
IntRegister(INT_LSPI,(void(*)(void))DmaSpiSwIntHandler);
IntPrioritySet(INT_LSPI, INT_PRIORITY_LVL_1);
IntEnable(INT_LSPI);
SPIIntEnable(ulBase,SPI_INT_EOW);
g_cDummy = 0x0;
#endif
}
SPIEnable(ulBase);
g_SpiFd = 1;
return g_SpiFd;
}