void RC522Write(uint8 Address,uint8 Data)
{
uint8 ModelAndAddress;
ModelAndAddress=WRITE|(Address<<1); //生成模式/地址数据
RC522TransEnable(); //选中从机
SPISendChar(ModelAndAddress); //传输模式/地址数据
while(!SPI_send); //等待发送
SPISendChar(Data); //发送需要写入的数据
while(!SPI_send); //等待发送
RC522TransDisable(); //取消从机选择
}
uint8 RC522Read(uint8 Address)
{
uint8 ModelAndAddress;
uint8 Re;
ModelAndAddress=READ|(Address<<1); //生成模式/地址数据
RC522TransEnable(); //选中从机
SPISendChar(ModelAndAddress); //传输模式/地址数据
while(!SPI_send); //等待发送
SPIRenEnable(); //允许接收
SPISendChar(0x00); //读取地址中的信息(0x00不代表任何意义,用于换出数据)
while(!SPI_send); //等待发送
RC522TransDisable(); //取消从机选择
SPIRenDisable(); //禁用接收
Re=SPI_re;
return Re; //返回读取的数据
}
/*!
* \brief SPIDrvWrite : Write 1 word to SPI
*
* \param u8Addr - SPI address
* \param u16Content - Data to send
*
*/
void SPIDrvWrite(UINT8 u8Addr, UINT16 u16Content)
{
UINT8 u8TempValue=0;
SPIClearRecieveStatReg(&u8TempValue); /* Clear status register (possible SPRF, SPTEF) */
SPIClearRecieveDataReg(&u8TempValue); /*
* Clear receive data register. SPI entirely ready
* for read or write
*/
MC13192DisableInterrupts(); /* Necessary to prevent double SPI access */
AssertCE(); /* Enables MC13192 SPI */
SPISendChar(u8Addr & 0x3F); /*
* Mask address, 6bit addr.
* Set write bit (i.e. 0).
*/
SPIWaitTransferDone(); /*
* For this bit to be set, SPTED MUST be set.
* Now write content MSB
*/
SPIClearRecieveDataReg(&u8TempValue); /*
* Clear receive data register. SPI entirely
* ready for read or write
*/
SPISendChar((UINT8)(u16Content >> 8)); /* Write MSB */
SPIWaitTransferDone(); /*
* For this bit to be set, SPTED MUST be set.
* Now write content LSB
*/
SPIClearRecieveDataReg(&u8TempValue); /*
* Clear receive data register. SPI entirely
* ready for read or write
*/
SPISendChar((UINT8)(u16Content & 0x00FF)); /* Write LSB */
SPIWaitTransferDone(); /*
* For this bit to be set, SPTED MUST be set.
* Now read last of garbage
*/
SPIClearRecieveDataReg(&u8TempValue); /*
* Clear receive data register. SPI entirely
* ready for read or write
*/
DeAssertCE(); /* Disables MC13192 SPI */
MC13192RestoreInterrupts(); /* Restore MC13192 interrupt status */
}
/*!
* \brief SPIDrvRead : Read 1 word from SPI
*
* \param u8Addr - SPI address
*
* \return u16Data - u16Data[0] is the MSB, u16Data[1] is the LSB
*/
UINT16 SPIDrvRead(UINT8 u8Addr)
{
UINT8 u8TempValue=0;
UINT16 u16Data=0; /* u16Data[0] is MSB, u16Data[1] is LSB */
SPIClearRecieveStatReg(&u8TempValue); /* Clear status register (possible SPRF, SPTEF) */
SPIClearRecieveDataReg(&u8TempValue); /*
* Clear receive data register. SPI entirely
* ready for read or write
*/
MC13192DisableInterrupts(); /* Necessary to prevent double SPI access */
AssertCE(); /* Enables MC13192 SPI */
SPISendChar((u8Addr & 0x3f) | 0x80); /* Mask address, 6bit addr, Set
* read bit.
*/
SPIWaitTransferDone(); /* For this bit to be set, SPTED MUST be set */
SPIClearRecieveDataReg(&u8TempValue); /*
* Clear receive data register. SPI
* entirely ready for read or write
*/
SPISendChar(u8Addr ); /*
* Dummy write. Receive register of SPI
* will contain MSB
*/
SPIWaitTransferDone(); /*
* For this bit to be set, SPTED MUST be
* set. Get MSB
*/
SPIReadMSB(&u16Data); /* MSB */
SPISendChar(u8Addr); /*
* Dummy write. Waiting until after
* reading received data insures no
* overrun
*/
SPIWaitTransferDone(); /*
* For this bit to be set, SPTED MUST be
* set. Get LSB
*/
((UINT8*)&u16Data)[1] = SPIRead(); /* LSB */
DeAssertCE(); /* Disables MC13192 SPI */
MC13192RestoreInterrupts(); /* Restore MC13192 interrupt status */
return u16Data;
}
/*!
* \brief RAMDrvReadRx : Read a block of data from RX packet RAM, whichever is selected
*
* \param *psRxPkt - Packet received
*
* \return u8Status
*/
UINT8 RAMDrvReadRx(tRxPacket *psRxPkt)
{
UINT8 i, u8TempByte=0; /* Temporary counters. */
UINT8 u8MinLen=0;
UINT8 u8TempValue=0; /*
* Used by SPIClearRecieveDataReg to
* flush SPI1D register during read
*/
UINT8 u8Status = 0; /* Holder for the return value */
UINT16 u16RxLength;
if (gsPhyOptions.Bits.u1PromiscuousMode)
u8MinLen = 3;
else
u8MinLen = 5;
u16RxLength = SPIDrvRead(RX_PKT_LEN); /*
* Read the RX packet length
* register contents
*/
u16RxLength &= 0x007F; /* Mask out all but the RX packet length */
/* MC13192 reports length with 2 CRC bytes and 2 Code bytes,
* remove them.
*/
if (u16RxLength >= u8MinLen) {
psRxPkt->u8DataLength = u16RxLength - (u8MinLen - 1); /*
* Less byte code
* and CRC
*/
}
else {
psRxPkt->u8DataLength = 0;
}
if ((psRxPkt->u8DataLength >= 1) && \
(psRxPkt->u8DataLength <= psRxPkt->u8MaxDataLength)) { /*
* If <5, the packet
* is garbage
*/
SPIClearRecieveStatReg(&u8TempValue); /* Clear status register (SPRF, SPTEF) */
SPIClearRecieveDataReg(&u8TempValue); /*
* Clear receive data register.
* SPI entirely ready for read or write
*/
MC13192DisableInterrupts(); /* Necessary to prevent double SPI access */
AssertCE(); /* Enables MC13192 SPI */
SPISendChar(RX_PKT | 0x80); /* SPI RX ram data register */
SPIWaitTransferDone(); /* For this bit to be set, SPTED
* MUST be set.
*/
SPIClearRecieveDataReg(&u8TempValue); /*
* Clear receive data register.
* SPI entirely ready for read or write
*/
SPISendChar(u8TempValue); /*
* Dummy write. Receive register of SPI will
* contain MSB garbage for first read
*/
SPIWaitTransferDone(); /* For this bit to be set, SPTED MUST be set.*/
SPIClearRecieveDataReg(&u8TempValue); /*
* Clear receive data register.
* SPI entirely ready for read or write
*/
SPISendChar(u8TempValue); /*
* Dummy write. Receive register of SPI will
* contain LSB garbage for first read
*/
SPIWaitTransferDone(); /* For this bit to be set, SPTED MUST be set.*/
SPIClearRecieveDataReg(&u8TempValue); /*
* Clear receive data register.
* SPI entirely ready for read or write
*/
if (gsPhyOptions.Bits.u1PromiscuousMode == 0)
{
/* Byte codes */
SPISendChar(u8TempValue); /*
* Dummy write. Receive register of SPI will
* contain LSB garbage for first read
*/
SPIWaitTransferDone(); /* For this bit to be set, SPTED MUST be set.*/
u8TempValue = SPIRead(); /* Read first code byte */
SPISendChar(u8TempValue); /*
* Dummy write. Receive register of SPI will
* contain LSB garbage for first read
*/
SPIWaitTransferDone(); /* For this bit to be set, SPTED MUST be set.*/
u8TempValue = SPIRead(); /* Read second code byte */
}
u8TempByte = 0; /* Byte counter for *contents */
/* Word loop. Round up. Deduct CRC. */
for (i=0; i<((u16RxLength-1)>>1); i++) {
SPISendChar(u8TempValue);/*
* Dummy write. Receive register of SPI
* will contain MSB
*/
SPIWaitTransferDone(); /*
* For this bit to be set, SPTED MUST be
* set. Get MSB
*/
/* For a trailing garbage byte, just read and discard */
if ((u8TempByte + 3) == u16RxLength) {
SPIClearRecieveDataReg(&u8TempValue); /* Discard */
}
else {
psRxPkt->pu8Data[u8TempByte + 1] = SPIRead(); /* Read MSB */
}
SPISendChar(u8TempValue);/*
* Dummy write. Receive register of SPI
* will contain LSB
*/
SPIWaitTransferDone(); /*
* For this bit to be set, SPTED MUST be
* set. Get LSB
*/
psRxPkt->pu8Data[u8TempByte] = SPIRead(); /* Read LSB */
u8TempByte = (UINT8)(u8TempByte + 2); /* Increment byte counter */
}
DeAssertCE(); /* Disables MC13192 SPI */
psRxPkt->u8Status = SUCCESS;
MC13192RestoreInterrupts(); /* Restore MC13192 interrupt status */
}
/*!
* \brief RAMDrvWriteTx : Write a block of data to TX packet RAM, whichever is selected
*
* \param *psTxPkt - Packet to write
*
*/
void RAMDrvWriteTx(tTxPacket *psTxPkt)
{
UINT8 i, u8TempByte=0, u8TempValue=0; /* Temporary counters */
UINT8 u8MinLen=0;
UINT16 u16Reg=0; /* TX packet length register value */
if (gsPhyOptions.Bits.u1PromiscuousMode)
u8MinLen = 3;
else
u8MinLen = 5;
u16Reg = SPIDrvRead(TX_PKT_LEN); /*
* Read the TX packet length register
* contents
*/
u16Reg = (0xFF80 & u16Reg) | (psTxPkt->u8DataLength + (u8MinLen - 1)); /*
* Mask out old
* length setting and
* update. Add 2 for
* CRC and 2 for code bytes
*/
SPIDrvWrite(TX_PKT_LEN, u16Reg); /* Update the TX packet length field */
SPIClearRecieveStatReg(&u8TempValue);/* Clear status register
* (possible SPRF, SPTEF)
*/
SPIClearRecieveDataReg(&u8TempValue); /*
* Clear receive data register. SPI entirely
* ready for read or write
*/
MC13192DisableInterrupts(); /* Necessary to prevent double SPI access */
AssertCE(); /* Enables MC13192 SPI */
SPISendChar(TX_PKT); /* SPI TX ram data register */
SPIWaitTransferDone(); /*
* For this bit to be set, SPTED MUST be set.
* Now write content MSB
*/
SPIClearRecieveDataReg(&u8TempValue); /*
* Clear receive data register. SPI entirely
* ready for read or write
*/
if (!gsPhyOptions.Bits.u1PromiscuousMode)
{
SPISendChar(0xFF); /* Send 1st Code Byte */
SPIWaitTransferDone(); /*
* For this bit to be set, SPTED MUST be set.
* Now write content MSB
*/
SPISendChar(0x7E); /* Send 2nd Code Byte */
SPIWaitTransferDone(); /*
* For this bit to be set, SPTED MUST be set.
* Now write content MSB
*/
SPIClearRecieveDataReg(&u8TempValue); /*
* Clear receive data register. SPI entirely
* ready for read or write
*/
}
u8TempByte = 0; /* Byte counter for *contents */
/* Word loop. Round up. */
for (i=0; i<((psTxPkt->u8DataLength+1) >> 1); i++) {
SPISendChar(psTxPkt->pu8Data[u8TempByte + 1]); /* Write MSB */
SPIWaitTransferDone(); /*
* For this bit to be set, SPTED MUST be set.
* Now write content LSB
*/
SPIClearRecieveDataReg(&u8TempValue);/*
* Clear receive data register. SPI entirely
* ready for read or write
*/
SPISendChar(psTxPkt->pu8Data[u8TempByte]); /* Write LSB */
u8TempByte = (UINT8)(u8TempByte + 2); /* Increment byte counter */
SPIWaitTransferDone(); /* For this bit to be set, SPTED MUST be set.*/
SPIClearRecieveDataReg(&u8TempValue);/*
* Clear receive data register. SPI entirely
* ready for read or write
*/
}
DeAssertCE(); /* Disables MC13192 SPI */
MC13192RestoreInterrupts(); /* Restore MC13192 interrupt status */
}