void i2c_t::Init( I2C_TypeDef *pi2c, GPIO_TypeDef *PGpio, uint16_t SclPin, uint16_t SdaPin, uint32_t BitrateHz, const stm32_dma_stream_t *APDmaTx, const stm32_dma_stream_t *APDmaRx ) { ii2c = pi2c; IPGpio = PGpio; ISclPin = SclPin; ISdaPin = SdaPin; IBitrateHz = BitrateHz; Standby(); Resume(); // ==== DMA ==== // Here only unchanged parameters of the DMA are configured. uint16_t DmaChnl = 3; // I2C3 if (ii2c == I2C1) DmaChnl = 1; else if (ii2c == I2C2) DmaChnl = 7; // Setup Dma TX PDmaTx = APDmaTx; dmaStreamAllocate(PDmaTx, IRQ_PRIO_MEDIUM, i2cDmaIrqHandler, this); dmaStreamSetPeripheral(PDmaTx, &ii2c->DR); dmaStreamSetMode (PDmaTx, STM32_DMA_CR_CHSEL(DmaChnl) | DMA_PRIORITY_LOW | STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MINC | // Memory pointer increase STM32_DMA_CR_DIR_M2P | // Direction is memory to peripheral STM32_DMA_CR_TCIE // Enable Transmission Complete IRQ ); // Setup Dma RX PDmaRx = APDmaRx; dmaStreamAllocate(PDmaRx, IRQ_PRIO_MEDIUM, i2cDmaIrqHandler, this); //dmaStreamAllocate(PDmaRx, 1, i2cDmaRXIrqHandler, NULL); dmaStreamSetPeripheral(PDmaRx, &ii2c->DR); dmaStreamSetMode (PDmaRx, STM32_DMA_CR_CHSEL(DmaChnl) | DMA_PRIORITY_LOW | STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MINC | // Memory pointer increase STM32_DMA_CR_DIR_P2M // Direction is peripheral to memory | STM32_DMA_CR_TCIE // Enable Transmission Complete IRQ ); }
/** * @brief Low level ADC driver initialization. * * @notapi */ void adc_lld_init(void) { ADC->CCR = STM32_ADC_ADCPRE; #if STM32_ADC_USE_ADC1 /* Driver initialization.*/ adcObjectInit(&ADCD1); ADCD1.adc = ADC1; ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM); ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_EN; #endif #if STM32_ADC_USE_ADC2 /* Driver initialization.*/ adcObjectInit(&ADCD2); ADCD2.adc = ADC2; ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM); ADCD2.dmamode = STM32_DMA_CR_CHSEL(ADC2_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_EN; #endif #if STM32_ADC_USE_ADC3 /* Driver initialization.*/ adcObjectInit(&ADCD3); ADCD3.adc = ADC3; ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM); ADCD3.dmamode = STM32_DMA_CR_CHSEL(ADC3_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_EN; #endif /* The shared vector is initialized on driver initialization and never disabled.*/ nvicEnableVector(ADC_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY)); }
/** * @brief Configures and activates the SDC peripheral. * * @param[in] sdcp pointer to the @p SDCDriver object * * @notapi */ void sdc_lld_start(SDCDriver *sdcp) { /* Checking configuration, using a default if NULL has been passed.*/ if (sdcp->config == NULL) { sdcp->config = &sdc_default_cfg; } sdcp->dmamode = STM32_DMA_CR_CHSEL(SDMMC1_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SDC_SDMMC1_DMA_PRIORITY) | STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC; #if STM32_DMA_ADVANCED sdcp->dmamode |= STM32_DMA_CR_PFCTRL | STM32_DMA_CR_PBURST_INCR4 | STM32_DMA_CR_MBURST_INCR4; #endif /* If in stopped state then clocks are enabled and DMA initialized.*/ if (sdcp->state == BLK_STOP) { #if STM32_SDC_USE_SDMMC1 if (&SDCD1 == sdcp) { bool b = dmaStreamAllocate(sdcp->dma, STM32_SDC_SDMMC1_IRQ_PRIORITY, NULL, NULL); osalDbgAssert(!b, "stream already allocated"); dmaStreamSetPeripheral(sdcp->dma, &sdcp->sdmmc->FIFO); #if STM32_DMA_ADVANCED dmaStreamSetFIFO(sdcp->dma, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL); #endif rccEnableSDMMC1(FALSE); } #endif /* STM32_SDC_USE_SDMMC1 */ #if STM32_SDC_USE_SDMMC2 if (&SDCD2 == sdcp) { bool b = dmaStreamAllocate(sdcp->dma, STM32_SDC_SDMMC2_IRQ_PRIORITY, NULL, NULL); osalDbgAssert(!b, "stream already allocated"); dmaStreamSetPeripheral(sdcp->dma, &sdcp->sdmmc->FIFO); #if STM32_DMA_ADVANCED dmaStreamSetFIFO(sdcp->dma, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL); #endif rccEnableSDMMC2(FALSE); } #endif /* STM32_SDC_USE_SDMMC2 */ } /* Configuration, card clock is initially stopped.*/ sdcp->sdmmc->POWER = 0; sdcp->sdmmc->CLKCR = 0; sdcp->sdmmc->DCTRL = 0; sdcp->sdmmc->DTIMER = 0; }
/** * @brief Configures and activates the NAND peripheral. * * @param[in] nandp pointer to the @p NANDDriver object * * @notapi */ void nand_lld_start(NANDDriver *nandp) { bool b; if (FSMCD1.state == FSMC_STOP) fsmc_start(&FSMCD1); if (nandp->state == NAND_STOP) { b = dmaStreamAllocate(nandp->dma, STM32_EMC_FSMC1_IRQ_PRIORITY, (stm32_dmaisr_t)nand_lld_serve_transfer_end_irq, (void *)nandp); osalDbgAssert(!b, "stream already allocated"); nandp->dmamode = STM32_DMA_CR_CHSEL(NAND_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_NAND_NAND1_DMA_PRIORITY) | STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE; /* dmaStreamSetFIFO(nandp->dma, STM32_DMA_FCR_DMDIS | NAND_STM32_DMA_FCR_FTH_LVL); */ nandp->nand->PCR = calc_eccps(nandp) | FSMC_PCR_PTYP | FSMC_PCR_PBKEN; nandp->nand->PMEM = nandp->config->pmem; nandp->nand->PATT = nandp->config->pmem; nandp->isr_handler = nand_isr_handler; nand_ready_isr_enable(nandp); } }
void DbgUart_t::Init(uint32_t ABaudrate) { PWrite = TXBuf; PRead = TXBuf; ICountToSendNext = 0; IDmaIsIdle = true; //PinSetupAlterFunc(GPIOA, 9, omPushPull, pudNone, AF7); // TX1 PinSetupAlterFunc(GPIOA, 2, omPushPull, pudNone, AF7); // TX2 // ==== USART configuration ==== UART_RCC_ENABLE(); UART->BRR = Clk.APB2FreqHz / ABaudrate; UART->CR2 = 0; UART->CR3 = USART_CR3_DMAT; // Enable DMA at transmitter UART->CR1 = USART_CR1_TE; // Transmitter enabled // ==== DMA ==== // Here only the unchanged parameters of the DMA are configured. dmaStreamAllocate (UART_DMA, 1, DbgUartIrq, NULL); dmaStreamSetPeripheral(UART_DMA, &UART->DR); dmaStreamSetMode (UART_DMA, STM32_DMA_CR_CHSEL(UART_DMA_CHNL) | DMA_PRIORITY_LOW | STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MINC | // Memory pointer increase STM32_DMA_CR_DIR_M2P | // Direction is memory to peripheral STM32_DMA_CR_TCIE // Enable Transmission Complete IRQ ); UART->CR1 |= USART_CR1_UE; // Enable USART }
void DbgUart_t::Init(uint32_t ABaudrate) { PWrite = TXBuf; PRead = TXBuf; ICountToSendNext = 0; IDmaIsIdle = true; PinSetupAlterFunc(GPIOA, 9, omPushPull, pudNone, AF7); // TX1 // ==== USART configuration ==== rccEnableUSART1(FALSE); // UART clock, no clock in low-power USART1->BRR = Clk.APB2FreqHz / 115200; USART1->CR2 = 0; USART1->CR3 = USART_CR3_DMAT; // Enable DMA at transmitter USART1->CR1 = USART_CR1_TE; // Transmitter enabled // ==== DMA ==== // Here only the unchanged parameters of the DMA are configured. dmaStreamAllocate (STM32_DMA2_STREAM7, 1, DbgUartIrq, NULL); dmaStreamSetPeripheral(STM32_DMA2_STREAM7, &USART1->DR); dmaStreamSetMode (STM32_DMA2_STREAM7, STM32_DMA_CR_CHSEL(4) | // DMA2 Stream7 Channel4 is USART1_TX request DMA_PRIORITY_LOW | STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MINC | // Memory pointer increase STM32_DMA_CR_DIR_M2P | // Direction is memory to peripheral STM32_DMA_CR_TCIE // Enable Transmission Complete IRQ ); USART1->CR1 |= USART_CR1_UE; // Enable USART }
*/ void sdc_lld_start(SDCDriver *sdcp) { sdcp->dmamode = STM32_DMA_CR_CHSEL(DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) | STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC; #if (defined(STM32F4XX) || defined(STM32F2XX)) sdcp->dmamode |= STM32_DMA_CR_PFCTRL | STM32_DMA_CR_PBURST_INCR4 | STM32_DMA_CR_MBURST_INCR4; #endif if (sdcp->state == BLK_STOP) { /* Note, the DMA must be enabled before the IRQs.*/ bool_t b; b = dmaStreamAllocate(sdcp->dma, STM32_SDC_SDIO_IRQ_PRIORITY, NULL, NULL); chDbgAssert(!b, "i2c_lld_start(), #3", "stream already allocated"); dmaStreamSetPeripheral(sdcp->dma, &SDIO->FIFO); #if (defined(STM32F4XX) || defined(STM32F2XX)) dmaStreamSetFIFO(sdcp->dma, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL); #endif nvicEnableVector(STM32_SDIO_NUMBER, CORTEX_PRIORITY_MASK(STM32_SDC_SDIO_IRQ_PRIORITY)); rccEnableSDIO(FALSE); } /* Configuration, card clock is initially stopped.*/ SDIO->POWER = 0; SDIO->CLKCR = 0; SDIO->DCTRL = 0; SDIO->DTIMER = 0;
/** * @brief Low level DAC driver initialization. * * @notapi */ void dac_lld_init(void) { #if STM32_DAC_USE_CHN1 dacObjectInit(&DACD1); DACD1.dac = DAC1; DACD1.tim = STM32_TIM6; DACD1.irqprio = STM32_DAC_CHN1_IRQ_PRIORITY; DACD1.dma = STM32_DMA_STREAM(STM32_DAC_CHN1_DMA_STREAM); DACD1.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN1_DMA_CHANNEL) | \ STM32_DMA_CR_PL(STM32_DAC_CHN1_DMA_PRIORITY) | \ STM32_DMA_CR_DIR_M2P | \ STM32_DMA_CR_DMEIE | \ STM32_DMA_CR_TEIE | \ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE; #endif #if STM32_DAC_USE_CHN2 dacObjectInit(&DACD2); DACD2.dac = DAC1; DACD2.tim = STM32_TIM7; DACD2.irqprio = STM32_DAC_CHN2_IRQ_PRIORITY; DACD2.dma = STM32_DMA_STREAM(STM32_DAC_CHN2_DMA_STREAM); DACD2.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN2_DMA_CHANNEL) | \ STM32_DMA_CR_PL(STM32_DAC_CHN2_DMA_PRIORITY) | \ STM32_DMA_CR_DIR_M2P | \ STM32_DMA_CR_DMEIE | \ STM32_DMA_CR_TEIE | \ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE; #endif #if STM32_DAC_USE_CHN3 dacObjectInit(&DACD3); DACD3.dac = DAC2; DACD3.tim = STM32_TIM18; DACD3.irqprio = STM32_DAC_CHN3_IRQ_PRIORITY; DACD3.dma = STM32_DMA_STREAM(STM32_DAC_CHN3_DMA_STREAM); DACD3.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN3_DMA_CHANNEL) | \ STM32_DMA_CR_PL(STM32_DAC_CHN2_DMA_PRIORITY) | \ STM32_DMA_CR_DIR_M2P | \ STM32_DMA_CR_DMEIE | \ STM32_DMA_CR_TEIE | \ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE; #endif }
void usart_support_init(void) { SD1.usart = USART1; SD1.tx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART1_TX_DMA_STREAM); dmaStreamAllocate(SD1.tx.dma, STM32_SERIAL_USART1_PRIORITY, (stm32_dmaisr_t)usart_tx_dma_isr, &SD1.tx); SD1.rx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART1_RX_DMA_STREAM); dmaStreamAllocate(SD1.rx.dma, STM32_SERIAL_USART1_PRIORITY, (stm32_dmaisr_t)usart_rx_dma_isr, &SD1.rx); SD1.dmamode = STM32_DMA_CR_CHSEL(USART1_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SERIAL_USART1_DMA_PRIORITY); usart_support_init_tx(&SD1); usart_support_init_rx(&SD1); rccEnableUSART1(FALSE); SD3.usart = USART3; SD3.tx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART3_TX_DMA_STREAM); dmaStreamAllocate(SD3.tx.dma, STM32_SERIAL_USART3_PRIORITY, (stm32_dmaisr_t)usart_tx_dma_isr, &SD3.tx); SD3.rx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART3_RX_DMA_STREAM); dmaStreamAllocate(SD3.rx.dma, STM32_SERIAL_USART3_PRIORITY, (stm32_dmaisr_t)usart_rx_dma_isr, &SD3.rx); SD3.dmamode = STM32_DMA_CR_CHSEL(USART3_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SERIAL_USART3_DMA_PRIORITY); usart_support_init_tx(&SD3); usart_support_init_rx(&SD3); rccEnableUSART3(FALSE); SD6.usart = USART6; SD6.tx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART6_TX_DMA_STREAM); dmaStreamAllocate(SD6.tx.dma, STM32_SERIAL_USART6_PRIORITY, (stm32_dmaisr_t)usart_tx_dma_isr, &SD6.tx); SD6.rx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART6_RX_DMA_STREAM); dmaStreamAllocate(SD6.rx.dma, STM32_SERIAL_USART6_PRIORITY, (stm32_dmaisr_t)usart_rx_dma_isr, &SD6.rx); SD6.dmamode = STM32_DMA_CR_CHSEL(USART6_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SERIAL_USART6_DMA_PRIORITY); usart_support_init_tx(&SD6); usart_support_init_rx(&SD6); rccEnableUSART6(FALSE); }
/** * @brief Low level SPI driver initialization. * * @notapi */ void spi_lld_init(void) { dummytx = 0xFFFF; #if STM32_SPI_USE_SPI1 spiObjectInit(&SPID1); SPID1.spi = SPI1; SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM); SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM); SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; #endif #if STM32_SPI_USE_SPI2 spiObjectInit(&SPID2); SPID2.spi = SPI2; SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM); SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM); SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; #endif #if STM32_SPI_USE_SPI3 spiObjectInit(&SPID3); SPID3.spi = SPI3; SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM); SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM); SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; #endif }
/** * @brief Low level QSPI driver initialization. * * @notapi */ void qspi_lld_init(void) { #if STM32_QSPI_USE_QUADSPI1 qspiObjectInit(&QSPID1); QSPID1.qspi = QUADSPI; QSPID1.dma = STM32_DMA_STREAM(STM32_QSPI_QUADSPI1_DMA_STREAM); QSPID1.dmamode = STM32_DMA_CR_CHSEL(QUADSPI1_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_QSPI_QUADSPI1_DMA_PRIORITY) | STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; nvicEnableVector(STM32_QUADSPI1_NUMBER, STM32_QSPI_QUADSPI1_IRQ_PRIORITY); #endif }
void Infrared_t::TxInit() { // ==== Carrier timer ==== Carrier.Init(); Carrier.Enable(); Carrier.PwmInit(IR_CARRIER_GPIO, IR_CARRIER_PIN, IR_CARRIER_CHNL, invNotInverted); Carrier.SetUpdateFrequency(IR_CARRIER_HZ); MaxPower = Carrier.GetTopValue() / 2; // Setup master-slave Carrier.SetTriggerInput(IR_CARRIER_TRG_IN); // Slave using TIM5 as input (ITR2) Carrier.SlaveModeSelect(smReset); // Slave mode: reset on trigger Carrier.MasterModeSelect(mmReset); // Master mode: trigger output on Reset Carrier.DmaOnTriggerEnable(); // Request DMA on trigger output == req on Reset = req on input //Carrier.PwmSet(MaxPower); // Debug // ==== Modulation timer ==== Modulator.Init(); Modulator.Enable(); Modulator.SetTopValue(IR_TICK_US-1); // Delay in us Modulator.MasterModeSelect(mmUpdate); // Master mode: Update is used as TRGO Modulator.SetupPrescaler(1000000); // Input Freq: 1 MHz => one tick = 1 uS Modulator.Disable(); // Debug // PinSetupAlterFunc(GPIOA, 0, omPushPull, pudNone, AF2); // Debug pin // TIM5->CCMR1 = (0b110<<4); // PWM mode1 // TIM5->CCR1 = IR_TICK_US/2; // TIM5->CCER = TIM_CCER_CC1E; // Enable output1 // ==== DMA ==== Here only the unchanged parameters of the DMA are configured dmaStreamAllocate (IR_TX_DMA_STREAM, IRQ_PRIO_LOW, IrTxcIrq, NULL); dmaStreamSetPeripheral(IR_TX_DMA_STREAM, Carrier.PCCR); dmaStreamSetMemory0 (IR_TX_DMA_STREAM, TxPwrBuf); dmaStreamSetMode (IR_TX_DMA_STREAM, STM32_DMA_CR_CHSEL(IR_TX_DMA_CHNL) | DMA_PRIORITY_MEDIUM | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MINC // Memory pointer increase | STM32_DMA_CR_DIR_M2P // Direction is memory to peripheral // | STM32_DMA_CR_CIRC // Enable circular buffer | STM32_DMA_CR_TCIE // Enable Transmission Complete IRQ ); // ==== Variables ==== IsBusy = false; }
void Infrared_t::Init() { // ==== Carrier timer ==== uint16_t tmp = (uint16_t)(Clk.AHBFreqHz / IR_CARRIER_HZ); // Top timer value Carrier.Init(GPIOA, 8, 1, 1, tmp, IR_TX_INVERTED); IR_CAR_TMR->SMCR = (0b000 << 4) | 0b100; // Slave using TIM5 as input (ITR0), Reset mode IR_CAR_TMR->CR2 = 0; // Reset is trigger output IR_CAR_TMR->DIER = TIM_DIER_TDE; // Request DMA on trigger MaxPower = tmp / 2; //Carrier.On(MaxPower); // Debug // ==== Modulation timer ==== rccEnableTIM5(FALSE); TIM5->ARR = IR_TICK_US-1; // Delay TIM5->CR2 = (0b010<<4); // Master mode: Update is used as TRGO TIM5->PSC = (Clk.APB1FreqHz / 1000000) - 1; // Input Freq: 1 MHz => one tick = 1 uS // Debug // PinSetupAlterFunc(GPIOA, 0, omPushPull, pudNone, AF2); // Debug pin // TIM5->CCMR1 = (0b110<<4); // PWM mode1 // TIM5->CCR1 = IR_TICK_US/2; // TIM5->CCER = TIM_CCER_CC1E; // Enable output1 // ==== DMA ==== Here only the unchanged parameters of the DMA are configured dmaStreamAllocate (IR_TX_DMA_STR, 1, IrTxcIrq, NULL); dmaStreamSetPeripheral(IR_TX_DMA_STR, Carrier.PCCR); dmaStreamSetMemory0(IR_TX_DMA_STR, Buf); //dmaStreamSetPeripheral(IR_TX_DMA_STR, &TIM1->CCR1); dmaStreamSetMode (IR_TX_DMA_STR, STM32_DMA_CR_CHSEL(IR_TX_DMA_CHNL) | DMA_PRIORITY_MEDIUM | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MINC // Memory pointer increase | STM32_DMA_CR_DIR_M2P // Direction is memory to peripheral // | STM32_DMA_CR_CIRC // Enable circular buffer | STM32_DMA_CR_TCIE // Enable Transmission Complete IRQ ); // ==== Variables ==== IsBusy = false; }
static void codec_dma_init(void) { i2sdma=STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM); i2stxdmamode = STM32_DMA_CR_CHSEL(I2S3_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; bool_t b = dmaStreamAllocate(i2sdma, STM32_SPI_SPI3_IRQ_PRIORITY, (stm32_dmaisr_t)dma_i2s_interrupt, (void *)&SPID3); if (!b) chprintf((BaseChannel*)&SD2, "DMA Allocated Successfully to I2S3\r\n"); dmaStreamSetPeripheral(i2sdma, &(SPI3->DR)); }
/** * @brief Configures and activates the SDC peripheral. * * @param[in] sdcp pointer to the @p SDCDriver object * * @notapi */ void sdc_lld_start(SDCDriver *sdcp) { /* Checking configuration, using a default if NULL has been passed.*/ if (sdcp->config == NULL) { sdcp->config = &sdc_default_cfg; } sdcp->dmamode = STM32_DMA_CR_CHSEL(DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SDC_SDMMC1_DMA_PRIORITY) | STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC; #if 1 sdcp->dmamode |= STM32_DMA_CR_PFCTRL | STM32_DMA_CR_PBURST_INCR4 | STM32_DMA_CR_MBURST_INCR4; #endif if (sdcp->state == BLK_STOP) { /* Note, the DMA must be enabled before the IRQs.*/ bool b; b = dmaStreamAllocate(sdcp->dma, STM32_SDC_SDMMC1_IRQ_PRIORITY, NULL, NULL); osalDbgAssert(!b, "stream already allocated"); dmaStreamSetPeripheral(sdcp->dma, &sdcp->sdmmc->FIFO); #if 1 dmaStreamSetFIFO(sdcp->dma, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL); #endif nvicEnableVector(STM32_SDMMC1_NUMBER, STM32_SDC_SDMMC1_IRQ_PRIORITY); rccEnableSDMMC1(FALSE); } /* Configuration, card clock is initially stopped.*/ sdcp->sdmmc->POWER = 0; sdcp->sdmmc->CLKCR = 0; sdcp->sdmmc->DCTRL = 0; sdcp->sdmmc->DTIMER = 0; }
/** * @brief Configures and activates the I2C peripheral. * * @param[in] i2cp pointer to the @p I2CDriver object * * @notapi */ void i2c_lld_start(I2CDriver *i2cp) { I2C_TypeDef *dp = i2cp->i2c; i2cp->dmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE; /* If in stopped state then enables the I2C and DMA clocks.*/ if (i2cp->state == I2C_STOP) { #if STM32_I2C_USE_I2C1 if (&I2CD1 == i2cp) { bool_t b; rccResetI2C1(); b = dmaStreamAllocate(i2cp->dmarx, STM32_I2C_I2C1_IRQ_PRIORITY, (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, (void *)i2cp); chDbgAssert(!b, "i2c_lld_start(), #1", "stream already allocated"); b = dmaStreamAllocate(i2cp->dmatx, STM32_I2C_I2C1_IRQ_PRIORITY, (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, (void *)i2cp); chDbgAssert(!b, "i2c_lld_start(), #2", "stream already allocated"); rccEnableI2C1(FALSE); nvicEnableVector(I2C1_EV_IRQn, CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); nvicEnableVector(I2C1_ER_IRQn, CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); } #endif /* STM32_I2C_USE_I2C1 */ #if STM32_I2C_USE_I2C2 if (&I2CD2 == i2cp) { bool_t b; rccResetI2C2(); b = dmaStreamAllocate(i2cp->dmarx, STM32_I2C_I2C2_IRQ_PRIORITY, (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, (void *)i2cp); chDbgAssert(!b, "i2c_lld_start(), #3", "stream already allocated"); b = dmaStreamAllocate(i2cp->dmatx, STM32_I2C_I2C2_IRQ_PRIORITY, (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, (void *)i2cp); chDbgAssert(!b, "i2c_lld_start(), #4", "stream already allocated"); rccEnableI2C2(FALSE); nvicEnableVector(I2C2_EV_IRQn, CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); nvicEnableVector(I2C2_ER_IRQn, CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); } #endif /* STM32_I2C_USE_I2C2 */ #if STM32_I2C_USE_I2C3 if (&I2CD3 == i2cp) { bool_t b; rccResetI2C3(); b = dmaStreamAllocate(i2cp->dmarx, STM32_I2C_I2C3_IRQ_PRIORITY, (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, (void *)i2cp); chDbgAssert(!b, "i2c_lld_start(), #5", "stream already allocated"); b = dmaStreamAllocate(i2cp->dmatx, STM32_I2C_I2C3_IRQ_PRIORITY, (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, (void *)i2cp); chDbgAssert(!b, "i2c_lld_start(), #6", "stream already allocated"); rccEnableI2C3(FALSE); nvicEnableVector(I2C3_EV_IRQn, CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY)); nvicEnableVector(I2C3_ER_IRQn, CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY)); i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY); } #endif /* STM32_I2C_USE_I2C3 */ } /* DMA streams mode preparation in advance.*/ dmaStreamSetMode(i2cp->dmatx, i2cp->dmamode | STM32_DMA_CR_DIR_M2P); dmaStreamSetMode(i2cp->dmarx, i2cp->dmamode | STM32_DMA_CR_DIR_P2M); /* I2C registers pointed by the DMA.*/ dmaStreamSetPeripheral(i2cp->dmarx, &dp->DR); dmaStreamSetPeripheral(i2cp->dmatx, &dp->DR); /* Reset i2c peripheral.*/ dp->CR1 = I2C_CR1_SWRST; dp->CR1 = 0; dp->CR2 = I2C_CR2_ITERREN | I2C_CR2_DMAEN; /* Setup I2C parameters.*/ i2c_lld_set_clock(i2cp); i2c_lld_set_opmode(i2cp); /* Ready to go.*/ dp->CR1 |= I2C_CR1_PE; }
/** * @brief Configures and activates the I2C peripheral. * * @param[in] i2cp pointer to the @p I2CDriver object * * @notapi */ void i2c_lld_start(I2CDriver *i2cp) { I2C_TypeDef *dp = i2cp->i2c; #if STM32_I2C_USE_DMA == TRUE /* Common DMA modes.*/ i2cp->txdmamode = DMAMODE_COMMON | STM32_DMA_CR_DIR_M2P; i2cp->rxdmamode = DMAMODE_COMMON | STM32_DMA_CR_DIR_P2M; #endif /* Make sure I2C peripheral is disabled */ dp->CR1 &= ~I2C_CR1_PE; /* If in stopped state then enables the I2C and DMA clocks.*/ if (i2cp->state == I2C_STOP) { #if STM32_I2C_USE_I2C1 if (&I2CD1 == i2cp) { rccResetI2C1(); rccEnableI2C1(FALSE); #if STM32_I2C_USE_DMA == TRUE { bool b; b = dmaStreamAllocate(i2cp->dmarx, STM32_I2C_I2C1_IRQ_PRIORITY, NULL, (void *)i2cp); osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(i2cp->dmatx, STM32_I2C_I2C1_IRQ_PRIORITY, NULL, (void *)i2cp); osalDbgAssert(!b, "stream already allocated"); i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C1_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); } #endif /* STM32_I2C_USE_DMA == TRUE */ #if defined(STM32_I2C1_GLOBAL_NUMBER) || defined(__DOXYGEN__) nvicEnableVector(STM32_I2C1_GLOBAL_NUMBER, STM32_I2C_I2C1_IRQ_PRIORITY); #elif defined(STM32_I2C1_EVENT_NUMBER) && defined(STM32_I2C1_ERROR_NUMBER) nvicEnableVector(STM32_I2C1_EVENT_NUMBER, STM32_I2C_I2C1_IRQ_PRIORITY); nvicEnableVector(STM32_I2C1_ERROR_NUMBER, STM32_I2C_I2C1_IRQ_PRIORITY); #else #error "I2C1 interrupt numbers not defined" #endif } #endif /* STM32_I2C_USE_I2C1 */ #if STM32_I2C_USE_I2C2 if (&I2CD2 == i2cp) { rccResetI2C2(); rccEnableI2C2(FALSE); #if STM32_I2C_USE_DMA == TRUE { bool b; b = dmaStreamAllocate(i2cp->dmarx, STM32_I2C_I2C2_IRQ_PRIORITY, NULL, (void *)i2cp); osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(i2cp->dmatx, STM32_I2C_I2C2_IRQ_PRIORITY, NULL, (void *)i2cp); osalDbgAssert(!b, "stream already allocated"); i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C2_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); } #endif /*STM32_I2C_USE_DMA == TRUE */ #if defined(STM32_I2C2_GLOBAL_NUMBER) || defined(__DOXYGEN__) nvicEnableVector(STM32_I2C2_GLOBAL_NUMBER, STM32_I2C_I2C2_IRQ_PRIORITY); #elif defined(STM32_I2C2_EVENT_NUMBER) && defined(STM32_I2C2_ERROR_NUMBER) nvicEnableVector(STM32_I2C2_EVENT_NUMBER, STM32_I2C_I2C2_IRQ_PRIORITY); nvicEnableVector(STM32_I2C2_ERROR_NUMBER, STM32_I2C_I2C2_IRQ_PRIORITY); #else #error "I2C2 interrupt numbers not defined" #endif } #endif /* STM32_I2C_USE_I2C2 */ #if STM32_I2C_USE_I2C3 if (&I2CD3 == i2cp) { rccResetI2C3(); rccEnableI2C3(FALSE); #if STM32_I2C_USE_DMA == TRUE { bool b; b = dmaStreamAllocate(i2cp->dmarx, STM32_I2C_I2C3_IRQ_PRIORITY, NULL, (void *)i2cp); osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(i2cp->dmatx, STM32_I2C_I2C3_IRQ_PRIORITY, NULL, (void *)i2cp); osalDbgAssert(!b, "stream already allocated"); i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY); i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C3_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY); } #endif /*STM32_I2C_USE_DMA == TRUE */ #if defined(STM32_I2C3_GLOBAL_NUMBER) || defined(__DOXYGEN__) nvicEnableVector(STM32_I2C3_GLOBAL_NUMBER, STM32_I2C_I2C3_IRQ_PRIORITY); #elif defined(STM32_I2C3_EVENT_NUMBER) && defined(STM32_I2C3_ERROR_NUMBER) nvicEnableVector(STM32_I2C3_EVENT_NUMBER, STM32_I2C_I2C3_IRQ_PRIORITY); nvicEnableVector(STM32_I2C3_ERROR_NUMBER, STM32_I2C_I2C3_IRQ_PRIORITY); #else #error "I2C3 interrupt numbers not defined" #endif } #endif /* STM32_I2C_USE_I2C3 */ #if STM32_I2C_USE_I2C4 if (&I2CD4 == i2cp) { rccResetI2C4(); rccEnableI2C4(FALSE); #if STM32_I2C_USE_DMA == TRUE { bool b; b = dmaStreamAllocate(i2cp->dmarx, STM32_I2C_I2C4_IRQ_PRIORITY, NULL, (void *)i2cp); osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(i2cp->dmatx, STM32_I2C_I2C4_IRQ_PRIORITY, NULL, (void *)i2cp); osalDbgAssert(!b, "stream already allocated"); i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C4_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2C_I2C4_DMA_PRIORITY); i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C4_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2C_I2C4_DMA_PRIORITY); } #endif /*STM32_I2C_USE_DMA == TRUE */ #if defined(STM32_I2C4_GLOBAL_NUMBER) || defined(__DOXYGEN__) nvicEnableVector(STM32_I2C4_GLOBAL_NUMBER, STM32_I2C_I2C4_IRQ_PRIORITY); #elif defined(STM32_I2C4_EVENT_NUMBER) && defined(STM32_I2C4_ERROR_NUMBER) nvicEnableVector(STM32_I2C4_EVENT_NUMBER, STM32_I2C_I2C4_IRQ_PRIORITY); nvicEnableVector(STM32_I2C4_ERROR_NUMBER, STM32_I2C_I2C4_IRQ_PRIORITY); #else #error "I2C4 interrupt numbers not defined" #endif } #endif /* STM32_I2C_USE_I2C4 */ } #if STM32_I2C_USE_DMA == TRUE /* I2C registers pointed by the DMA.*/ dmaStreamSetPeripheral(i2cp->dmarx, &dp->RXDR); dmaStreamSetPeripheral(i2cp->dmatx, &dp->TXDR); #endif /* Reset i2c peripheral, the TCIE bit will be handled separately.*/ dp->CR1 = i2cp->config->cr1 | #if STM32_I2C_USE_DMA == TRUE I2C_CR1_TXDMAEN | I2C_CR1_RXDMAEN | /* Enable only if using DMA */ #endif I2C_CR1_ERRIE | I2C_CR1_NACKIE; /* Setup I2C parameters.*/ dp->TIMINGR = i2cp->config->timingr; /* Ready to go.*/ dp->CR1 |= I2C_CR1_PE; }
#if (STM32_DAC_USE_DAC2_CH2 && !STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__) DACDriver DACD4; #endif /*===========================================================================*/ /* Driver local variables. */ /*===========================================================================*/ #if STM32_DAC_USE_DAC1_CH1 == TRUE static const dacparams_t dma1_ch1_params = { .dac = DAC1, .dataoffset = 0U, .regshift = 0U, .regmask = 0xFFFF0000U, .dma = STM32_DMA_STREAM(STM32_DAC_DAC1_CH1_DMA_STREAM), .dmamode = STM32_DMA_CR_CHSEL(DAC1_CH1_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_DAC_DAC1_CH1_DMA_PRIORITY) | STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE | STM32_DMA_CR_TCIE, .dmairqprio = STM32_DAC_DAC1_CH1_IRQ_PRIORITY }; #endif #if STM32_DAC_USE_DAC1_CH2 == TRUE static const dacparams_t dma1_ch2_params = { .dac = DAC1, .dataoffset = CHANNEL_DATA_OFFSET, .regshift = 16U, .regmask = 0x0000FFFFU, .dma = STM32_DMA_STREAM(STM32_DAC_DAC1_CH2_DMA_STREAM),
/** * @brief Low level ADC driver initialization. * * @notapi */ void adc_lld_init(void) { #if STM32_ADC_USE_ADC1 /* Driver initialization.*/ adcObjectInit(&ADCD1); ADCD1.adc = ADC1; #if STM32_ADC_USE_SDADC ADCD1.sdadc = NULL; #endif ADCD1.dmastp = STM32_DMA1_STREAM1; ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; nvicEnableVector(ADC1_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_ADC1_IRQ_PRIORITY)); #endif #if STM32_ADC_USE_SDADC1 /* Driver initialization.*/ adcObjectInit(&SDADCD1); #if STM32_ADC_USE_ADC SDADCD1.adc = NULL; #endif SDADCD1.sdadc = SDADC1; SDADCD1.dmastp = STM32_DMA2_STREAM3; SDADCD1.dmamode = STM32_DMA_CR_CHSEL(SDADC1_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_ADC_SDADC1_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; nvicEnableVector(SDADC1_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_SDADC1_IRQ_PRIORITY)); #endif #if STM32_ADC_USE_SDADC2 /* Driver initialization.*/ adcObjectInit(&SDADCD2); #if STM32_ADC_USE_ADC SDADCD2.adc = NULL; #endif SDADCD2.sdadc = SDADC2; SDADCD2.dmastp = STM32_DMA2_STREAM4; SDADCD2.dmamode = STM32_DMA_CR_CHSEL(SDADC2_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_ADC_SDADC2_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; nvicEnableVector(SDADC2_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_SDADC2_IRQ_PRIORITY)); #endif #if STM32_ADC_USE_SDADC3 /* Driver initialization.*/ adcObjectInit(&SDADCD3); #if STM32_ADC_USE_ADC SDADCD3.adc = NULL; #endif SDADCD3.sdadc = SDADC3; SDADCD3.dmastp = STM32_DMA2_STREAM5; SDADCD3.dmamode = STM32_DMA_CR_CHSEL(SDADC3_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_ADC_SDADC3_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; nvicEnableVector(SDADC3_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_SDADC3_IRQ_PRIORITY)); #endif }
/** * @brief Configures and activates the UART peripheral. * * @param[in] uartp pointer to the @p UARTDriver object * * @notapi */ void uart_lld_start(UARTDriver *uartp) { if (uartp->state == UART_STOP) { #if STM32_UART_USE_USART1 if (&UARTD1 == uartp) { bool b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART1_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART1_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); rccEnableUSART1(FALSE); nvicEnableVector(STM32_USART1_NUMBER, STM32_UART_USART1_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); } #endif #if STM32_UART_USE_USART2 if (&UARTD2 == uartp) { bool b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART2_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART2_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); rccEnableUSART2(FALSE); nvicEnableVector(STM32_USART2_NUMBER, STM32_UART_USART2_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); } #endif #if STM32_UART_USE_USART3 if (&UARTD3 == uartp) { bool b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART3_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART3_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); rccEnableUSART3(FALSE); nvicEnableVector(STM32_USART3_NUMBER, STM32_UART_USART3_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); } #endif #if STM32_UART_USE_UART4 if (&UARTD4 == uartp) { bool b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_UART4_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_UART4_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); rccEnableUART4(FALSE); nvicEnableVector(STM32_UART4_NUMBER, STM32_UART_UART4_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY); } #endif #if STM32_UART_USE_UART5 if (&UARTD5 == uartp) { bool b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_UART5_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_UART5_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); rccEnableUART5(FALSE); nvicEnableVector(STM32_UART5_NUMBER, STM32_UART_UART5_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY); } #endif #if STM32_UART_USE_USART6 if (&UARTD6 == uartp) { bool b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART6_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART6_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); rccEnableUSART6(FALSE); nvicEnableVector(STM32_USART6_NUMBER, STM32_UART_USART6_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY); } #endif #if STM32_UART_USE_UART7 if (&UARTD7 == uartp) { bool b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_UART7_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_UART7_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); rccEnableUART7(FALSE); nvicEnableVector(STM32_UART7_NUMBER, STM32_UART_UART7_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(UART7_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_UART7_DMA_PRIORITY); } #endif #if STM32_UART_USE_UART8 if (&UARTD8 == uartp) { bool b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_UART8_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_UART8_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); rccEnableUART8(FALSE); nvicEnableVector(STM32_UART8_NUMBER, STM32_UART_UART8_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(UART8_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_UART8_DMA_PRIORITY); } #endif /* Static DMA setup, the transfer size depends on the USART settings, it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/ if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->RDR); dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->TDR); uartp->rxbuf = 0; } uartp->rxstate = UART_RX_IDLE; uartp->txstate = UART_TX_IDLE; usart_start(uartp); }
/** * @brief Configures and activates the UART peripheral. * * @param[in] uartp pointer to the @p UARTDriver object * * @notapi */ void uart_lld_start(UARTDriver *uartp) { uartp->dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; if (uartp->state == UART_STOP) { #if STM32_UART_USE_USART1 if (&UARTD1 == uartp) { bool_t b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART1_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART1_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated"); rccEnableUSART1(FALSE); nvicEnableVector(STM32_USART1_NUMBER, CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY)); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); } #endif #if STM32_UART_USE_USART2 if (&UARTD2 == uartp) { bool_t b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART2_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART2_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated"); rccEnableUSART2(FALSE); nvicEnableVector(STM32_USART2_NUMBER, CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY)); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); } #endif #if STM32_UART_USE_USART3 if (&UARTD3 == uartp) { bool_t b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART3_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART3_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated"); rccEnableUSART3(FALSE); nvicEnableVector(STM32_USART3_NUMBER, CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY)); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); } #endif /* Static DMA setup, the transfer size depends on the USART settings, it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/ if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->RDR); dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->TDR); uartp->rxbuf = 0; } uartp->rxstate = UART_RX_IDLE; uartp->txstate = UART_TX_IDLE; usart_start(uartp); }
/** * @brief Configures and activates the I2C peripheral. * * @param[in] i2cp pointer to the @p I2CDriver object * * @notapi */ void i2c_lld_start(I2CDriver *i2cp) { I2C_TypeDef *dp = i2cp->i2c; i2cp->txdmamode = DMAMODE_COMMON | STM32_DMA_CR_DIR_M2P; i2cp->rxdmamode = DMAMODE_COMMON | STM32_DMA_CR_DIR_P2M; /* Make sure I2C peripheral is disabled */ dp->CR1 &= ~I2C_CR1_PE; /* If in stopped state then enables the I2C and DMA clocks.*/ if (i2cp->state == I2C_STOP) { #if STM32_I2C_USE_I2C1 if (&I2CD1 == i2cp) { bool_t b; rccResetI2C1(); b = dmaStreamAllocate(i2cp->dmarx, STM32_I2C_I2C1_IRQ_PRIORITY, (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, (void *)i2cp); chDbgAssert(!b, "i2c_lld_start(), #1", "stream already allocated"); b = dmaStreamAllocate(i2cp->dmatx, STM32_I2C_I2C1_IRQ_PRIORITY, (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, (void *)i2cp); chDbgAssert(!b, "i2c_lld_start(), #2", "stream already allocated"); rccEnableI2C1(FALSE); #if defined(STM32_I2C1_GLOBAL_NUMBER) || defined(__DOXYGEN__) nvicEnableVector(STM32_I2C1_GLOBAL_NUMBER, CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); #elif defined(STM32_I2C1_EVENT_NUMBER) && defined(STM32_I2C1_ERROR_NUMBER) nvicEnableVector(STM32_I2C1_EVENT_NUMBER, CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); nvicEnableVector(STM32_I2C1_ERROR_NUMBER, CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); #else #error "I2C1 interrupt numbers not defined" #endif i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C1_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); } #endif /* STM32_I2C_USE_I2C1 */ #if STM32_I2C_USE_I2C2 if (&I2CD2 == i2cp) { bool_t b; rccResetI2C2(); b = dmaStreamAllocate(i2cp->dmarx, STM32_I2C_I2C2_IRQ_PRIORITY, (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, (void *)i2cp); chDbgAssert(!b, "i2c_lld_start(), #3", "stream already allocated"); b = dmaStreamAllocate(i2cp->dmatx, STM32_I2C_I2C2_IRQ_PRIORITY, (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, (void *)i2cp); chDbgAssert(!b, "i2c_lld_start(), #4", "stream already allocated"); rccEnableI2C2(FALSE); #if defined(STM32_I2C2_GLOBAL_NUMBER) || defined(__DOXYGEN__) nvicEnableVector(STM32_I2C2_GLOBAL_NUMBER, CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); #elif defined(STM32_I2C2_EVENT_NUMBER) && defined(STM32_I2C2_ERROR_NUMBER) nvicEnableVector(STM32_I2C2_EVENT_NUMBER, CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); nvicEnableVector(STM32_I2C2_ERROR_NUMBER, CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); #else #error "I2C2 interrupt numbers not defined" #endif i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C2_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); } #endif /* STM32_I2C_USE_I2C2 */ } /* I2C registers pointed by the DMA.*/ dmaStreamSetPeripheral(i2cp->dmarx, &dp->RXDR); dmaStreamSetPeripheral(i2cp->dmatx, &dp->TXDR); /* Reset i2c peripheral, the TCIE bit will be handled separately.*/ dp->CR1 = i2cp->config->cr1 | I2C_CR1_ERRIE | I2C_CR1_STOPIE | I2C_CR1_NACKIE | I2C_CR1_TXDMAEN | I2C_CR1_RXDMAEN; /* Set slave address field (master mode) */ dp->CR2 = (i2cp->config->cr2 & ~I2C_CR2_SADD); /* Setup I2C parameters.*/ dp->TIMINGR = i2cp->config->timingr; /* Ready to go.*/ dp->CR1 |= I2C_CR1_PE; }
/** * @brief Low level I2S driver initialization. * * @notapi */ void i2s_lld_init(void) { #if STM32_I2S_USE_SPI2 i2sObjectInit(&I2SD2); I2SD2.spi = SPI2; I2SD2.cfg = STM32_I2S2_CFGR_CFG; #if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) I2SD2.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI2_RX_DMA_STREAM); I2SD2.rxdmamode = STM32_DMA_CR_CHSEL(I2S2_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_HTIE | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; #else I2SD2.dmarx = NULL; I2SD2.rxdmamode = 0; #endif #if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) I2SD2.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI2_TX_DMA_STREAM); I2SD2.txdmamode = STM32_DMA_CR_CHSEL(I2S2_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_HTIE | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; #else I2SD2.dmatx = NULL; I2SD2.txdmamode = 0; #endif #endif #if STM32_I2S_USE_SPI3 i2sObjectInit(&I2SD3); I2SD3.spi = SPI3; I2SD3.cfg = STM32_I2S3_CFGR_CFG; #if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) I2SD3.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI3_RX_DMA_STREAM); I2SD3.rxdmamode = STM32_DMA_CR_CHSEL(I2S3_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_HTIE | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; #else I2SD3.dmarx = NULL; I2SD3.rxdmamode = 0; #endif #if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) I2SD3.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI3_TX_DMA_STREAM); I2SD3.txdmamode = STM32_DMA_CR_CHSEL(I2S3_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_HTIE | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; #else I2SD3.dmatx = NULL; I2SD3.txdmamode = 0; #endif #endif }
/** * @brief Low level SPI driver initialization. * * @notapi */ void spi_lld_init(void) { #if STM32_SPI_USE_SPI1 spiObjectInit(&SPID1); SPID1.spi = SPI1; SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM); SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM); SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; #endif #if STM32_SPI_USE_SPI2 spiObjectInit(&SPID2); SPID2.spi = SPI2; SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM); SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM); SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; #endif #if STM32_SPI_USE_SPI3 spiObjectInit(&SPID3); SPID3.spi = SPI3; SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM); SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM); SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; #endif #if STM32_SPI_USE_SPI4 spiObjectInit(&SPID4); SPID4.spi = SPI4; SPID4.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI4_RX_DMA_STREAM); SPID4.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI4_TX_DMA_STREAM); SPID4.rxdmamode = STM32_DMA_CR_CHSEL(SPI4_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; SPID4.txdmamode = STM32_DMA_CR_CHSEL(SPI4_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) | STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; #endif #if STM32_SPI_USE_SPI5 spiObjectInit(&SPID5); SPID5.spi = SPI5; SPID5.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI5_RX_DMA_STREAM); SPID5.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI5_TX_DMA_STREAM); SPID5.rxdmamode = STM32_DMA_CR_CHSEL(SPI5_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; SPID5.txdmamode = STM32_DMA_CR_CHSEL(SPI5_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) | STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; #endif #if STM32_SPI_USE_SPI6 spiObjectInit(&SPID6); SPID6.spi = SPI6; SPID6.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI6_RX_DMA_STREAM); SPID6.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI6_TX_DMA_STREAM); SPID6.rxdmamode = STM32_DMA_CR_CHSEL(SPI6_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; SPID6.txdmamode = STM32_DMA_CR_CHSEL(SPI6_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) | STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; #endif }
/** * @brief Configures and activates the UART peripheral. * * @param[in] uartp pointer to the @p UARTDriver object * * @notapi */ void uart_lld_start(UARTDriver *uartp) { if (uartp->state == UART_STOP) { #if STM32_UART_USE_USART1 if (&UARTD1 == uartp) { bool_t b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART1_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART1_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated"); rccEnableUSART1(FALSE); nvicEnableVector(STM32_USART1_NUMBER, CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY)); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); } #endif #if STM32_UART_USE_USART2 if (&UARTD2 == uartp) { bool_t b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART2_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART2_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated"); rccEnableUSART2(FALSE); nvicEnableVector(STM32_USART2_NUMBER, CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY)); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); } #endif #if STM32_UART_USE_USART3 if (&UARTD3 == uartp) { bool_t b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART3_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART3_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated"); rccEnableUSART3(FALSE); nvicEnableVector(STM32_USART3_NUMBER, CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY)); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); } #endif #if STM32_UART_USE_UART4 if (&UARTD4 == uartp) { bool_t b; chDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0, "uart_lld_start(), #7", "specified invalid bits in UART4 CR2 register settings"); chDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0, "uart_lld_start(), #8", "specified invalid bits in UART4 CR3 register settings"); b = dmaStreamAllocate(uartp->dmarx, STM32_UART_UART4_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #9", "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_UART4_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #10", "stream already allocated"); rccEnableUART4(FALSE); nvicEnableVector(STM32_UART4_NUMBER, CORTEX_PRIORITY_MASK(STM32_UART_UART4_IRQ_PRIORITY)); uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY); } #endif #if STM32_UART_USE_UART5 if (&UARTD5 == uartp) { bool_t b; chDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0, "uart_lld_start(), #11", "specified invalid bits in UART5 CR2 register settings"); chDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0, "uart_lld_start(), #12", "specified invalid bits in UART5 CR3 register settings"); b = dmaStreamAllocate(uartp->dmarx, STM32_UART_UART5_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #13", "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_UART5_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #14", "stream already allocated"); rccEnableUART5(FALSE); nvicEnableVector(STM32_UART5_NUMBER, CORTEX_PRIORITY_MASK(STM32_UART_UART5_IRQ_PRIORITY)); uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY); } #endif #if STM32_UART_USE_USART6 if (&UARTD6 == uartp) { bool_t b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART6_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #15", "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART6_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #16", "stream already allocated"); rccEnableUSART6(FALSE); nvicEnableVector(STM32_USART6_NUMBER, CORTEX_PRIORITY_MASK(STM32_UART_USART6_IRQ_PRIORITY)); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY); } #endif /* Static DMA setup, the transfer size depends on the USART settings, it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/ if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->DR); dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->DR); uartp->rxbuf = 0; } uartp->rxstate = UART_RX_IDLE; uartp->txstate = UART_TX_IDLE; usart_start(uartp); }