void HWI_handleEDMAInterrupt(){ if(EDMA_intTest(tccTrxPing)) { EDMA_intClear(tccTrxPing); SWI_post(&procPing); } else if(EDMA_intTest(tccTrxPong)) { EDMA_intClear(tccTrxPong); SWI_post(&procPong); } }
void c_int11() //ISR - AD535 codec interrupts at 8kHz { x[0] = (float)(input_left_sample()); //get new input into delay line output_left_sample((short)(yn)); //output to codec SWI_post(&SWI_fir_isr); return; }
void c_int11(void) { input[bufferindex] = (fixedp)input_left_sample(); output_left_sample((short)output[bufferindex]); if(++bufferindex >= N) { bufferindex = 0; bufferflag = 1; SWI_post(&SWI_process_isr); } return; }
//extern Int16 gpio02State; // debug void gpt1Isr(void) { /* Clear TIAFR flag */ CSL_SYSCTRL_REGS->TIAFR = 0x2; //gpio02State ^= 0x1; // debug //GpioWrite02(gpio02State); /* Perform USB frame rate processing */ SWI_post(&SWI_UserInterface); }
void EDMA_ISR(void) { static int rcvPingDone=0; //static static int rcvPongDone=0; static int xmtPingDone=0; static int xmtPongDone=0; if(EDMA_intTest(tccRcvPing)) { EDMA_intClear(tccRcvPing); // clear is mandatory rcvPingDone=1; } else if(EDMA_intTest(tccRcvPong)) { EDMA_intClear(tccRcvPong); rcvPongDone=1; } if(EDMA_intTest(tccXmtPing)) { EDMA_intClear(tccXmtPing); xmtPingDone=1; } else if(EDMA_intTest(tccXmtPong)) { EDMA_intClear(tccXmtPong); xmtPongDone=1; } if(rcvPingDone && xmtPingDone) { rcvPingDone=0; xmtPingDone=0; // processing in SWI SWI_post(&SWI_Ping); } else if(rcvPongDone && xmtPongDone) { rcvPongDone=0; xmtPongDone=0; // processing in SWI SWI_post(&SWI_Pong); } }
void PRU_HWI(void) { VPIF_beginning_line = 1; SWI_post(&SWI_vision); EVTCLR0 |= PRU_INTCLR; }
void EDMA_interrupt_service(void) { //LOG_printf(&myLog, "EDMA interrupt"); static volatile int rcvPingDone=0; static volatile int rcvPongDone=0; static volatile int rcvPengDone=0; static volatile int xmtPingDone=0; static volatile int xmtPongDone=0; static volatile int xmtPengDone=0; if(EDMA_intTest(tccRcvPing)) { EDMA_intClear(tccRcvPing); /* clear is mandatory */ rcvPingDone=1; } else if(EDMA_intTest(tccRcvPong)) // EIGEN!!!: Richtiges Flag verwendet? { EDMA_intClear(tccRcvPong); rcvPongDone=1; } else if(EDMA_intTest(tccRcvPeng)) // EIGEN!!!: Richtiges Flag verwendet? { EDMA_intClear(tccRcvPeng); rcvPengDone=1; } if(EDMA_intTest(tccXmtPing)) // EIGEN!!!: Richtiges Flag verwendet? { EDMA_intClear(tccXmtPing); xmtPingDone=1; } else if(EDMA_intTest(tccXmtPong)) // EIGEN!!!: Richtiges Flag verwendet? { EDMA_intClear(tccXmtPong); xmtPongDone=1; } else if(EDMA_intTest(tccXmtPeng)) // EIGEN!!!: Richtiges Flag verwendet? { EDMA_intClear(tccXmtPeng); xmtPengDone=1; } if(rcvPingDone && xmtPingDone) { rcvPingDone=0; xmtPingDone=0; // processing in SWI SWI_post(&Ping_SWI); } else if(rcvPongDone && xmtPongDone) { rcvPongDone=0; xmtPongDone=0; // processing in SWI SWI_post(&Pong_SWI); } else if(rcvPengDone && xmtPengDone) { rcvPengDone=0; xmtPengDone=0; // processing in SWI SWI_post(&Peng_SWI); } }
void SPI_RXint(void) { GpioDataRegs.GPASET.bit.GPIO9 = 1; GpioDataRegs.GPASET.bit.GPIO10 = 1; GpioDataRegs.GPASET.bit.GPIO11 = 1; GpioDataRegs.GPASET.bit.GPIO22 = 1; GpioDataRegs.GPASET.bit.GPIO19 = 1; switch (SPIenc_state) { case 1: SPIbyte1 = SpiaRegs.SPIRXBUF; SPIbyte2 = SpiaRegs.SPIRXBUF; // these reads are not needed except to add some delay SPIbyte3 = SpiaRegs.SPIRXBUF; SPIbyte4 = SpiaRegs.SPIRXBUF; SPIbyte5 = SpiaRegs.SPIRXBUF; SpiaRegs.SPIFFRX.bit.RXFFIL = 5; SPIenc_state = 2; GpioDataRegs.GPACLEAR.bit.GPIO9 = 1; SpiaRegs.SPITXBUF = ((unsigned)0x68)<<8; SpiaRegs.SPITXBUF = 0; SpiaRegs.SPITXBUF = 0; SpiaRegs.SPITXBUF = 0; SpiaRegs.SPITXBUF = 0; break; case 2: SPIbyte1 = SpiaRegs.SPIRXBUF; SPIbyte2 = SpiaRegs.SPIRXBUF & 0xFF; SPIbyte3 = SpiaRegs.SPIRXBUF & 0xFF; SPIbyte4 = SpiaRegs.SPIRXBUF & 0xFF; SPIbyte5 = SpiaRegs.SPIRXBUF & 0xFF; SPIenc1_reading = (SPIbyte2<<24) | (SPIbyte3<<16) | (SPIbyte4<<8) | SPIbyte5; SpiaRegs.SPIFFRX.bit.RXFFIL = 5; SPIenc_state = 3; GpioDataRegs.GPACLEAR.bit.GPIO10 = 1; SpiaRegs.SPITXBUF = ((unsigned)0x68)<<8; SpiaRegs.SPITXBUF = 0; SpiaRegs.SPITXBUF = 0; SpiaRegs.SPITXBUF = 0; SpiaRegs.SPITXBUF = 0; break; case 3: SPIbyte1 = SpiaRegs.SPIRXBUF; SPIbyte2 = SpiaRegs.SPIRXBUF & 0xFF; SPIbyte3 = SpiaRegs.SPIRXBUF & 0xFF; SPIbyte4 = SpiaRegs.SPIRXBUF & 0xFF; SPIbyte5 = SpiaRegs.SPIRXBUF & 0xFF; SPIenc2_reading = (SPIbyte2<<24) | (SPIbyte3<<16) | (SPIbyte4<<8) | SPIbyte5; SpiaRegs.SPIFFRX.bit.RXFFIL = 5; SPIenc_state = 4; GpioDataRegs.GPACLEAR.bit.GPIO11 = 1; SpiaRegs.SPITXBUF = ((unsigned)0x68)<<8; SpiaRegs.SPITXBUF = 0; SpiaRegs.SPITXBUF = 0; SpiaRegs.SPITXBUF = 0; SpiaRegs.SPITXBUF = 0; break; case 4: SPIbyte1 = SpiaRegs.SPIRXBUF; SPIbyte2 = SpiaRegs.SPIRXBUF & 0xFF; SPIbyte3 = SpiaRegs.SPIRXBUF & 0xFF; SPIbyte4 = SpiaRegs.SPIRXBUF & 0xFF; SPIbyte5 = SpiaRegs.SPIRXBUF & 0xFF; SPIenc3_reading = (SPIbyte2<<24) | (SPIbyte3<<16) | (SPIbyte4<<8) | SPIbyte5; SpiaRegs.SPIFFRX.bit.RXFFIL = 5; SPIenc_state = 5; GpioDataRegs.GPACLEAR.bit.GPIO22 = 1; SpiaRegs.SPITXBUF = ((unsigned)0x68)<<8; SpiaRegs.SPITXBUF = 0; SpiaRegs.SPITXBUF = 0; SpiaRegs.SPITXBUF = 0; SpiaRegs.SPITXBUF = 0; break; case 5: SPIbyte1 = SpiaRegs.SPIRXBUF; SPIbyte2 = SpiaRegs.SPIRXBUF & 0xFF; SPIbyte3 = SpiaRegs.SPIRXBUF & 0xFF; SPIbyte4 = SpiaRegs.SPIRXBUF & 0xFF; SPIbyte5 = SpiaRegs.SPIRXBUF & 0xFF; SPIenc4_reading = (SPIbyte2<<24) | (SPIbyte3<<16) | (SPIbyte4<<8) | SPIbyte5; SWI_post(&SWI_control); break; case 6: SPIbyte1 = SpiaRegs.SPIRXBUF; SPIbyte1 = SpiaRegs.SPIRXBUF; SPIbyte1 = SpiaRegs.SPIRXBUF; SPIenc_state = 7; // Output to DAC Ch2 SpiaRegs.SPIFFRX.bit.RXFFIL = 3; SPIenc_state = 7; GpioDataRegs.GPACLEAR.bit.GPIO19 = 1; SpiaRegs.SPIFFRX.bit.RXFFIL = 3; SpiaRegs.SPITXBUF = ((unsigned)0x12)<<8; SpiaRegs.SPITXBUF = (int)(dac2data << 4); SpiaRegs.SPITXBUF = ((int)(dac2data))<<12; break; case 7: SPIbyte1 = SpiaRegs.SPIRXBUF; SPIbyte1 = SpiaRegs.SPIRXBUF; SPIbyte1 = SpiaRegs.SPIRXBUF; SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; // set for LS7366 SpiaRegs.SPICTL.bit.CLK_PHASE = 1; SPIenc_state = 0; // Debug to see how long 4 SPI enc read takes // GpioDataRegs.GPACLEAR.bit.GPIO6 = 1; break; default: SPIbyte1 = SpiaRegs.SPIRXBUF; SPIbyte2 = SpiaRegs.SPIRXBUF; // these reads are not needed except to add some delay SPIbyte3 = SpiaRegs.SPIRXBUF; SPIbyte4 = SpiaRegs.SPIRXBUF; SPIbyte5 = SpiaRegs.SPIRXBUF; SPIenc_state_errors++; break; } SpiaRegs.SPIFFRX.bit.RXFFOVFCLR=1; // Clear Overflow flag SpiaRegs.SPIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; // Acknowledge interrupt to PIE }