//------------------------------------------------------------------------------ /// After POR, at91sam3u device is running on 4MHz internal RC /// At the end of the LowLevelInit procedure MCK = 48MHz PLLA = 96 CPU=48MHz /// Performs the low-level initialization of the chip. This includes EFC, master /// clock, IRQ & watchdog configuration. //------------------------------------------------------------------------------ void LowLevelInit(void) { unsigned int timeout = 0; /* Set 2 WS for Embedded Flash Access ************************************/ AT91C_BASE_EFC0->EFC_FMR = AT91C_EFC_FWS_2WS; AT91C_BASE_EFC1->EFC_FMR = AT91C_EFC_FWS_2WS; /* Watchdog initialization *************************/ AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; /* Select external slow clock ****************************/ if ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_SR_OSCSEL_CRYST) != AT91C_SUPC_SR_OSCSEL_CRYST) { AT91C_BASE_SUPC->SUPC_CR = AT91C_SUPC_CR_XTALSEL_CRYSTAL_SEL | (0xA5UL << 24UL); timeout = 0; while (!(AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_SR_OSCSEL_CRYST) && (timeout++ < CLOCK_TIMEOUT)); } /* Initialize main oscillator ****************************/ if(!(AT91C_BASE_PMC->PMC_MOR & AT91C_CKGR_MOSCSEL)) { AT91C_BASE_PMC->PMC_MOR = (0x37 << 16) | BOARD_OSCOUNT | AT91C_CKGR_MOSCRCEN | AT91C_CKGR_MOSCXTEN; timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCXTS) && (timeout++ < CLOCK_TIMEOUT)); } else { AT91C_BASE_PMC->PMC_MOR = (0x37 << 16) | BOARD_OSCOUNT | AT91C_CKGR_MOSCRCEN | AT91C_CKGR_MOSCXTEN | AT91C_CKGR_MOSCSEL; timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCRCS) && (timeout++ < CLOCK_TIMEOUT)); AT91C_BASE_PMC->PMC_MOR = (0x37 << 16) | BOARD_OSCOUNT | AT91C_CKGR_MOSCRCEN | AT91C_CKGR_MOSCXTEN; timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCSELS) && (timeout++ < CLOCK_TIMEOUT)); } /* Switch to moscsel */ AT91C_BASE_PMC->PMC_MOR = (0x37 << 16) | BOARD_OSCOUNT | AT91C_CKGR_MOSCRCEN | AT91C_CKGR_MOSCXTEN | AT91C_CKGR_MOSCSEL; timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCSELS) && (timeout++ < CLOCK_TIMEOUT)); AT91C_BASE_PMC->PMC_MCKR = (AT91C_BASE_PMC->PMC_MCKR & ~AT91C_PMC_CSS) | AT91C_PMC_CSS_MAIN_CLK; timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); /* Initialize PLLA */ AT91C_BASE_PMC->PMC_PLLAR = BOARD_PLLR; timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA) && (timeout++ < CLOCK_TIMEOUT)); /* Initialize UTMI for USB usage */ AT91C_BASE_CKGR->CKGR_UCKR |= (AT91C_CKGR_UPLLCOUNT & (3 << 20)) | AT91C_CKGR_UPLLEN; timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKU) && (timeout++ < CLOCK_TIMEOUT)); /* Switch to fast clock **********************/ AT91C_BASE_PMC->PMC_MCKR = (BOARD_MCKR & ~AT91C_PMC_CSS) | AT91C_PMC_CSS_MAIN_CLK; timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); AT91C_BASE_PMC->PMC_MCKR = BOARD_MCKR; timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); /* Enable clock for UART ************************/ AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_DBGU); /* Optimize CPU setting for speed */ SetDefaultMaster(1); }
//------------------------------------------------------------------------------ /// After POR, at91sam3u device is running on 4MHz internal RC /// At the end of the LowLevelInit procedure MCK = 48MHz PLLA = 96 CPU=48MHz /// Performs the low-level initialization of the chip. This includes EFC, master /// clock, IRQ & watchdog configuration. //------------------------------------------------------------------------------ void LowLevelInit(void) { unsigned int timeout = 0; /* Enable NRST reset ************************************/ AT91C_BASE_RSTC->RSTC_RMR |= (0xA5 << 24) | AT91C_RSTC_URSTEN; #if defined(SAM_BA) { asm volatile ("cpsid i"); } #endif /* Set 2 WS for Embedded Flash Access ************************************/ AT91C_BASE_EFC0->EFC_FMR = (0x6 << 8); #if defined(AT91C_BASE_EFC1) AT91C_BASE_EFC1->EFC_FMR = (0x6 << 8); #endif /* Watchdog initialization *************************/ AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; /* Select external slow clock ****************************/ if ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_SR_OSCSEL_CRYST) != AT91C_SUPC_SR_OSCSEL_CRYST) { AT91C_BASE_SUPC->SUPC_CR = AT91C_SUPC_CR_XTALSEL_CRYSTAL_SEL | (0xA5 << 24); timeout = 0; while (!(AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_SR_OSCSEL_CRYST) && (timeout++ < CLOCK_TIMEOUT)); } /* Initialize main oscillator ****************************/ if(!(AT91C_BASE_PMC->PMC_MOR & AT91C_CKGR_MOSCSEL)) { AT91C_BASE_PMC->PMC_MOR = (0x37 << 16) | BOARD_OSCOUNT | AT91C_CKGR_MOSCRCEN | AT91C_CKGR_MOSCXTEN; timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCXTS) && (timeout++ < CLOCK_TIMEOUT)); } /* Switch to 3-20MHz Xtal oscillator */ AT91C_BASE_PMC->PMC_MOR = (0x37 << 16) | BOARD_OSCOUNT | AT91C_CKGR_MOSCRCEN | AT91C_CKGR_MOSCXTEN | AT91C_CKGR_MOSCSEL; timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCSELS) && (timeout++ < CLOCK_TIMEOUT)); AT91C_BASE_PMC->PMC_MCKR = (AT91C_BASE_PMC->PMC_MCKR & ~AT91C_PMC_CSS) | AT91C_PMC_CSS_MAIN_CLK; timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); /* Initialize PLLA */ AT91C_BASE_PMC->PMC_PLLAR = BOARD_PLLR; timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA) && (timeout++ < CLOCK_TIMEOUT)); /* Initialize UTMI for USB usage, can be disabled if not using USB for the sake of saving power*/ AT91C_BASE_CKGR->CKGR_UCKR |= (AT91C_CKGR_UPLLCOUNT & (3 << 20)) | AT91C_CKGR_UPLLEN; timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKU) && (timeout++ < CLOCK_TIMEOUT)); /* Switch to fast clock **********************/ AT91C_BASE_PMC->PMC_MCKR = (BOARD_MCKR & ~AT91C_PMC_CSS) | AT91C_PMC_CSS_MAIN_CLK; timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); AT91C_BASE_PMC->PMC_MCKR = BOARD_MCKR; timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); /* Enable clock for UART ************************/ AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_DBGU); /* Optimize CPU setting for speed, for engineering samples only */ SetDefaultMaster(1); }
//------------------------------------------------------------------------------ /// Performs the low-level initialization of the chip. This includes EFC, master /// clock, IRQ & watchdog configuration. //------------------------------------------------------------------------------ void LowLevelInit(void) { unsigned int timeout = 0; /* Set 2 WS for Embedded Flash Access ************************************/ AT91C_BASE_EFC0->EFC_FMR = AT91C_EFC_FWS_2WS; AT91C_BASE_EFC1->EFC_FMR = AT91C_EFC_FWS_2WS; /* Watchdog initialization *************************/ AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; /* Select external slow clock ****************************/ if ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_OSCSEL) != AT91C_SUPC_OSCSEL) { AT91C_BASE_SUPC->SUPC_CR = AT91C_SUPC_XTALSEL | (0xA5u << 24); timeout = 0; while (!(AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_OSCSEL) && (timeout++ < CLOCK_TIMEOUT)); } /* Initialize main oscillator ****************************/ AT91C_BASE_PMC->PMC_MOR = (0x37 << 16) | BOARD_OSCOUNT | AT91C_CKGR_MOSCXTEN | AT91C_CKGR_MOSCSEL; timeout = 0; #if (0) // debug failed without these nops __asm { nop; nop; nop; }; #endif while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCXTS) && (timeout++ < CLOCK_TIMEOUT)); /* Switch to main oscillator */ AT91C_BASE_PMC->PMC_MCKR = (AT91C_BASE_PMC->PMC_MCKR & ~AT91C_PMC_CSS) | AT91C_PMC_CSS_MAIN_CLK; timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); /* Initialize PLLA */ //AT91C_BASE_PMC->PMC_PLLAR = BOARD_PLLR; // PLLA freq = 24Mhz * (3 + 1) / 1 = 96Mhz AT91C_BASE_PMC->PMC_PLLAR = ((1 << 29) | (3 << AT91C_CKGR_MUL_SHIFT) | (0x3f << AT91C_CKGR_PLLCOUNT_SHIFT) | (0x1 << AT91C_CKGR_DIV_SHIFT)); timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA) && (timeout++ < CLOCK_TIMEOUT)); /* Initialize UTMI for USB usage */ //AT91C_BASE_CKGR->CKGR_UCKR |= (AT91C_CKGR_UPLLCOUNT & (3 << 20)) | AT91C_CKGR_UPLLEN; AT91C_BASE_CKGR->CKGR_UCKR |= (AT91C_CKGR_UPLLCOUNT & (0xf << 20)) | AT91C_CKGR_UPLLEN; timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKU) && (timeout++ < CLOCK_TIMEOUT)); /* Switch to fast clock **********************/ // MCLK = PLLA = 96Mhz, processor clock = PLLA / 1 = 96Mhz AT91C_BASE_PMC->PMC_MCKR = (BOARD_MCKR & ~AT91C_PMC_CSS) | AT91C_PMC_CSS_MAIN_CLK; timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); AT91C_BASE_PMC->PMC_MCKR = BOARD_MCKR; timeout = 0; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); /* Enable clock for UART ************************/ //AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_DBGU); //AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA); #ifdef psram unsigned int tmp; const Pin pinPsram[] = {BOARD_PSRAM_PINS}; AT91PS_HSMC4_CS pSMC = AT91C_BASE_HSMC4_CS0; // Open EBI clock AT91C_BASE_PMC->PMC_PCER = (1<< AT91C_ID_HSMC4); // Configure I/O PIO_Configure(pinPsram, PIO_LISTSIZE(pinPsram)); // Setup the PSRAM (HSMC4_EBI.CS0, 0x60000000 ~ 0x60FFFFFF) pSMC->HSMC4_SETUP = 0 | ((1 << 0) & AT91C_HSMC4_NWE_SETUP) | ((1 << 8) & AT91C_HSMC4_NCS_WR_SETUP) | ((1 << 16) & AT91C_HSMC4_NRD_SETUP) | ((1 << 24) & AT91C_HSMC4_NCS_RD_SETUP) ; pSMC->HSMC4_PULSE = 0 | ((5 << 0) & AT91C_HSMC4_NWE_PULSE) | ((5 << 8) & AT91C_HSMC4_NCS_WR_PULSE) | ((5 << 16) & AT91C_HSMC4_NRD_PULSE) | ((5 << 24) & AT91C_HSMC4_NCS_RD_PULSE) ; pSMC->HSMC4_CYCLE = 0 | ((6 << 0) & AT91C_HSMC4_NWE_CYCLE) | ((6 << 16) & AT91C_HSMC4_NRD_CYCLE) ; tmp = pSMC->HSMC4_TIMINGS & (AT91C_HSMC4_OCMSEN | AT91C_HSMC4_RBNSEL | AT91C_HSMC4_NFSEL); pSMC->HSMC4_TIMINGS = tmp | ((0 << 0) & AT91C_HSMC4_TCLR) // CLE to REN | ((0 << 4) & AT91C_HSMC4_TADL) // ALE to Data | ((0 << 8) & AT91C_HSMC4_TAR) // ALE to REN | ((0 << 16) & AT91C_HSMC4_TRR) // Ready to REN | ((0 << 24) & AT91C_HSMC4_TWB) // WEN to REN ; tmp = pSMC->HSMC4_MODE & ~(AT91C_HSMC4_DBW); pSMC->HSMC4_MODE = tmp | (AT91C_HSMC4_READ_MODE) | (AT91C_HSMC4_WRITE_MODE) | (AT91C_HSMC4_DBW_WIDTH_SIXTEEN_BITS) ; #endif // #ifndef psram /* Optimize CPU setting for speed */ SetDefaultMaster(1); //SetFlashWaitState(10); }