void forceOOB(UINT32 ddBar5){
UINT8 dbPortNum;
for (dbPortNum=0;dbPortNum<=5;dbPortNum++)
RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01);
Stall(2000);
for (dbPortNum=0;dbPortNum<=5;dbPortNum++)
RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00);
Stall(2000);// Wait for 2ms
}
bool SendChar(char c,char next,int inputCount)
{
static char lastChar = 0;
bool answer = true;
int delay;
if ( c == ' ') delay = spaceDelays[delayIndex++];
else if ( c == '.' || c == ',') delay = spaceDelays[delayIndex];
else if ( c == '-') delay = 300;
else delay = spaceDelays[delayIndex++];
delay = (delay * 2) / 3; // speed it up a bit
if (lastChar == '.' || lastChar == ',') delay += spaceDelays[delayIndex] / 5;
if ( (inputCount % 7) == 0) delay += spaceDelays[delayIndex] / 2;
lastChar = c;
if (delayIndex == 30) delayIndex = 0;
delay = (4 * delay) / 5; // 20% faster
Stall(delay);// uneven typing delays
int returnValue;
char word[1000];
int i = 0;
while (specialChar[i])
{
if (c == specialChar[i])
{
sprintf(word,"%s\\%010d.%s.other",pathname,sequence++,specialName[i]);
returnValue = CreateDirectory(word, NULL);
// hesitate after sentences conjoined
if ((c == '.' || c == '!' || c == '?') && next == ' ') Stall(200);
return answer;
}
++i;
}
// not a special character
if ( c >= 'A' && c <= 'Z');
else if ( c >= 'a' && c <= 'z');
else if ( c >= '0' && c <= '9');
else return answer; // a nonalpha char we dont care about
sprintf(word,"%s\\%010d.%c.other",pathname,sequence++,c);
returnValue = CreateDirectory(word, NULL);
return answer;
}
//This patch is to workaround the SATA PHY logic hardware issue in the SB700.
//Internally this workaround is called as 7NewA
void sataPhyWorkaround(AMDSBCFG* pConfig, UINT32 ddBar5){
UINT8 dbPortNum, dbVar0;
if (pConfig->Gen1DeviceShutdownDuringPhyWrknd == 0x01){
for (dbPortNum=0;dbPortNum<=5;dbPortNum++){
ReadMEM(ddBar5+ SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint8, &dbVar0);
if ( (dbVar0 & 0xF0) == 0x10){
RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+2, AccWidthUint8 | S3_SAVE, 0xFF, (01 << dbPortNum));
}
}
}
RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)(BIT4+BIT3), BIT4+BIT3);//set PMIO_D0[4:3] = 11b // this is to tell SATA PHY to use the internal 100MHz clock
RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG86, AccWidthUint8 | S3_SAVE, 0x00, 0x40);// set SATA PCI_CFG 0x86[7:0] = 0x40 //after the reset is done, perform this to turn on the diff clock path into SATA PHY
Stall(2000);// Wait for 2ms
RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)(BIT4+BIT3), 00);//13. set PMIO_D0[4:3] = 00b
Stall(20000);// Wait 20ms
forceOOB(ddBar5);// Force OOB
RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+2, AccWidthUint8 | S3_SAVE, ~(0x03F), 00);
}
void USBSetupInterrupt()
{
SetEP(0);
if (!ReceivedSetupInt())
return;
Setup& setup = _setup; // global saves ~30 bytes
Recv((u8*)&setup,8);
ClearSetupInt();
if (setup.bmRequestType & DEVICETOHOST)
WaitIN();
else
ClearIN();
bool ok = true;
u8 r = setup.bRequest;
if (SET_ADDRESS == r)
{
WaitIN();
UDADDR = setup.wValueL | (1<<ADDEN);
}
else if (SET_CONFIGURATION == r)
{
_usbConfiguration = setup.wValueL;
InitEndpoints();
}
else if (GET_CONFIGURATION == r)
{
Send8(_usbConfiguration);
}
else if (GET_STATUS == r)
{
Send8(0); // All good as far as I know
}
else if (GET_DESCRIPTOR == r)
{
ok = SendDescriptor();
}
else
{
ok = USBHook();
}
if (ok)
ClearIN();
else
Stall();
}
void sataDriveDetection(AMDSBCFG* pConfig, UINT32 ddBar5){
UINT32 ddVar0;
UINT8 dbPortNum, dbVar0;
UINT32 dwIoBase, dwVar0;
TRACE((DMSG_SB_TRACE, "CIMx - Entering sata drive detection procedure\n\n"));
TRACE((DMSG_SB_TRACE, "SATA BAR5 is %X \n", ddBar5));
if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) ){
for (dbPortNum=0;dbPortNum<4;dbPortNum++){
ReadMEM(ddBar5+ SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0);
if ( ( ddVar0 & 0x0F ) == 0x03){
if ( dbPortNum & BIT0)
//this port belongs to secondary channel
ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase);
else
//this port belongs to primary channel
ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase);
//if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them
if (pConfig->SataClass == LEGACY_IDE_MODE)
dwIoBase = ( (0x170) | ( (~((dbPortNum & BIT0) << 7)) & 0x80 ) );
if ( dbPortNum & BIT1)
//this port is slave
dbVar0=0xB0;
else
//this port is master
dbVar0=0xA0;
dwIoBase &= 0xFFF8;
WriteIO(dwIoBase+6, AccWidthUint8, &dbVar0);
//Wait in loop for 30s for the drive to become ready
for (dwVar0=0;dwVar0<3000;dwVar0++){
ReadIO(dwIoBase+7, AccWidthUint8, &dbVar0);
if ( (dbVar0 & 0x88) == 0)
break;
Stall(10000);
}
} //end of if ( ( ddVar0 & 0x0F ) == 0x03)
} //for (dbPortNum=0;dbPortNum<4;dbPortNum++)
} //if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) )
}
void CCar::PhDataUpdate(float step)
{
if(m_repairing)Revert();
LimitWheels();
UpdateFuel(step);
//if(fwp)
{
UpdatePower();
if(b_engine_on&&!b_starting && m_current_rpm<m_min_rpm)Stall();
}
if(bkp)
{
UpdateBack();
}
if(brp)
HandBreak();
//////////////////////////////////////////////////////////
for (int k=0; k<(int)m_doors_update.size(); ++k){
SDoor* D = m_doors_update[k];
if (!D->update)
{
m_doors_update.erase(m_doors_update.begin()+k);
--k;
}
else
{
D->Update();
}
}
m_steer_angle=m_steering_wheels.begin()->GetSteerAngle()*0.1f+m_steer_angle*0.9f;
VERIFY(_valid(m_steer_angle));
}
void sataInitAfterPciEnum(AMDSBCFG* pConfig){
UINT32 ddAndMask=0, ddOrMask=0, ddBar5=0;
UINT8 dbVar, dbPortNum;
if (pConfig->SataController == 0) return; //return if SATA controller is disabled.
//Enable write access to pci header, pm capabilities
RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
//Disable AHCI enhancement function (RPR 7.2)
RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0xFF, BIT7);
restrictSataCapabilities(pConfig);
ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
if ( (ddBar5 == 0) || (ddBar5 == -1) ) {
//assign temporary BAR5
if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == -1))
ddBar5 = 0xFEC01000;
else
ddBar5=pConfig->TempMMIO;
WritePCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
}
ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
RWPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8,0xFF, 0x03); //memory and io access enable
ddBar5 &= 0xFFFFFC00; //Clear Bits 9:0
if (!pConfig->SataPortMultCap)
ddAndMask |= BIT12;
if (!pConfig->SataAggrLinkPmCap)
ddAndMask |= BIT11;
if (pConfig->SataSscPscCap)
ddOrMask |= BIT1;
RWMEM((ddBar5 + SB_SATA_BAR5_REGFC),AccWidthUint32 | S3_SAVE, ~ddAndMask, ddOrMask);
//Clear HPCP and ESP by default
RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, 0xFFFC0FC0, 0);
if (pConfig->SataHpcpButNonESP !=0) {
RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, 0xFFFFFFC0, pConfig->SataHpcpButNonESP);
}
// SATA ESP port setting
// These config bits are set for SATA driver to identify which ports are external SATA ports and need to
// support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will
// not enable power management(HIPM & DIPM) for these ports.
if (pConfig->SataEspPort !=0) {
RWMEM((ddBar5 + SB_SATA_BAR5_REGFC),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT20);
RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, ~(pConfig->SataEspPort), 0);
RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT17+BIT16+BIT15+BIT14+BIT13+BIT12),(pConfig->SataEspPort << 12));
}
if ( ((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE) )
RWPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50+2), AccWidthUint8, ~(UINT32)(BIT3+BIT2+BIT1), BIT2+BIT1); //set MSI to 8 messages
if ( ((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE) && ((pConfig->SataIdeCombinedMode) == CIMX_OPTION_DISABLED) ){
RWMEM((ddBar5 + SB_SATA_BAR5_REG00),AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), BIT2+BIT0);
RWMEM((ddBar5 + SB_SATA_BAR5_REG0C),AccWidthUint8 | S3_SAVE, 0xC0, 0x3F);
}
for (dbPortNum=0;dbPortNum<=5;dbPortNum++){
if (pConfig->SataPortMode & (1 << dbPortNum)){
//downgrade to GEN1
RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x10);
RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01);
Stall(1000);
RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00);
}
}
//If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround.
if ( !(pConfig->S3Resume) && ( ((pConfig->SataClass) != AHCI_MODE) && ((pConfig->SataClass) != RAID_MODE) && ((pConfig->SataClass) != AMD_AHCI_MODE) ) )
sataDriveDetection(pConfig, ddBar5);
if ( (pConfig->SataPhyWorkaround==1) || ( (pConfig->SataPhyWorkaround==0) && (getRevisionID() < SB700_A13)) )
sataPhyWorkaround(pConfig, ddBar5);
// Set the handshake bit for IDE driver to detect the disabled IDE channel correctly.
// Set IDE PCI Config 0x63 [3] if primary channel disabled, [4] if secondary channel disabled.
if (pConfig->SataIdeCombinedMode == CIMX_OPTION_DISABLED)
RWPCI( ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG63), AccWidthUint8 , 0xF9, (0x02 << (pConfig->SataIdeCombMdPriSecOpt)) );
WritePCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
//Disable write access to pci header, pm capabilities
RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0);
}
void FGTurbine::Calculate(void)
{
double thrust;
RunPreFunctions();
ThrottlePos = in.ThrottlePos[EngineNumber];
if (ThrottlePos > 1.0) {
AugmentCmd = ThrottlePos - 1.0;
ThrottlePos -= AugmentCmd;
} else {
AugmentCmd = 0.0;
}
// When trimming is finished check if user wants engine OFF or RUNNING
if ((phase == tpTrim) && (in.TotalDeltaT > 0)) {
if (Running && !Starved) {
phase = tpRun;
N1_factor = MaxN1 - IdleN1;
N2_factor = MaxN2 - IdleN2;
N2 = IdleN2 + ThrottlePos * N2_factor;
N1 = IdleN1 + ThrottlePos * N1_factor;
OilTemp_degK = 366.0;
Cutoff = false;
} else {
phase = tpOff;
Cutoff = true;
EGT_degC = in.TAT_c;
}
}
if (!Running && Cutoff && Starter) {
if (phase == tpOff) phase = tpSpinUp;
}
// start
if ((Starter == true) || (in.qbar > 30.0)) {
if (!Running && !Cutoff && (N2 > 15.0)) phase = tpStart;
}
if (Cutoff && (phase != tpSpinUp)) phase = tpOff;
if (in.TotalDeltaT == 0) phase = tpTrim;
if (Starved) phase = tpOff;
if (Stalled) phase = tpStall;
if (Seized) phase = tpSeize;
switch (phase) {
case tpOff: thrust = Off(); break;
case tpRun: thrust = Run(); break;
case tpSpinUp: thrust = SpinUp(); break;
case tpStart: thrust = Start(); break;
case tpStall: thrust = Stall(); break;
case tpSeize: thrust = Seize(); break;
case tpTrim: thrust = Trim(); break;
default: thrust = Off();
}
Thruster->Calculate(thrust); // allow thruster to modify thrust (i.e. reversing)
RunPostFunctions();
}
