static void test_bitMaskNrBits(void)
{
TEST_ASSERT_EQUAL_HEX32(0x1, makeBitmask(1, 0));
TEST_ASSERT_EQUAL_HEX32(0x3, makeBitmask(2, 0));
TEST_ASSERT_EQUAL_HEX32(0x1f, makeBitmask(5, 0));
TEST_ASSERT_EQUAL_HEX32(0xffffffff, makeBitmask(32, 0));
}
void test_pwm_channel_alignment() {
pwm_reset_peripheral();
pwm_set_channel_alignment(PWM_CHANNEL_3, PWM_CHANNEL_ALIGN_CENTER);
TEST_ASSERT_EQUAL_HEX32(0b100000000, pwm_get_channel_alignment(PWM_CHANNEL_3));
pwm_set_channel_alignment(PWM_CHANNEL_3, PWM_CHANNEL_ALIGN_LEFT);
TEST_ASSERT_EQUAL_HEX32(0x0, pwm_get_channel_alignment(PWM_CHANNEL_3));
}
void test_vga_get_offset_column_79_eq_80_eq_81()
{
const vga_offset_t offset1 = vga_get_offset(79, 0);
const vga_offset_t offset2 = vga_get_offset(80, 0);
const vga_offset_t offset3 = vga_get_offset(81, 0);
TEST_ASSERT_EQUAL_HEX32(offset1, offset2);
TEST_ASSERT_EQUAL_HEX32(offset2, offset3);
}
/*
* Checking that an PWM channel is enabled.
*/
void test_pwm_channel_enabled() {
pmc_enable_peripheral_clock(ID_PWM);
pwm_reset_peripheral();
pwm_enable_channel(PWM_CHANNEL_3);
TEST_ASSERT_EQUAL_HEX32(0x00000008, PWM->PWM_SR);
pwm_enable_channel(PWM_CHANNEL_4);
TEST_ASSERT_EQUAL_HEX32(0x00000018, PWM->PWM_SR);
}
static void test_bitMaskShift(void)
{
TEST_ASSERT_EQUAL_HEX32(0x2, makeBitmask(1, 1));
TEST_ASSERT_EQUAL_HEX32(0x80, makeBitmask(1, 7));
TEST_ASSERT_EQUAL_HEX32(0x100, makeBitmask(1, 8));
TEST_ASSERT_EQUAL_HEX32(0x38000, makeBitmask(3, 15));
TEST_ASSERT_EQUAL_HEX32(0xC0000000, makeBitmask(8, 30));
}
void test_vga_get_offset_inverse()
{
for (vga_position_t column = 0; column < 80; column++)
{
for (vga_position_t row = 0; row < 25; row++)
{
const vga_offset_t offset = vga_get_offset(column, row);
TEST_ASSERT_EQUAL_HEX32(vga_get_column_from_offset(offset), column);
TEST_ASSERT_EQUAL_HEX32(vga_get_row_from_offset(offset), row);
}
}
}
void test_binary_32()
{
TEST_ASSERT_EQUAL_HEX32(0x00000000, BIN32(00000000, 00000000, 00000000, 00000000));
TEST_ASSERT_EQUAL_HEX32(0x0000000f, BIN32(00000000, 00000000, 00000000, 00001111));
TEST_ASSERT_EQUAL_HEX32(0x000000f0, BIN32(00000000, 00000000, 00000000, 11110000));
TEST_ASSERT_EQUAL_HEX32(0x00000f00, BIN32(00000000, 00000000, 00001111, 00000000));
TEST_ASSERT_EQUAL_HEX32(0x0000f000, BIN32(00000000, 00000000, 11110000, 00000000));
TEST_ASSERT_EQUAL_HEX32(0x000f0000, BIN32(00000000, 00001111, 00000000, 00000000));
TEST_ASSERT_EQUAL_HEX32(0x00f00000, BIN32(00000000, 11110000, 00000000, 00000000));
TEST_ASSERT_EQUAL_HEX32(0x0f000000, BIN32(00001111, 00000000, 00000000, 00000000));
TEST_ASSERT_EQUAL_HEX32(0xf0000000, BIN32(11110000, 00000000, 00000000, 00000000));
TEST_ASSERT_EQUAL_HEX32(0xffffffff, BIN32(11111111, 11111111, 11111111, 11111111));
}
static void testthread(void *arg) {
intr_handle_t handle;
in_int_context=0;
int_handled=0;
TEST_ASSERT(!xPortInIsrContext());
xthal_set_ccompare(1, xthal_get_ccount()+8000000);
esp_err_t err = esp_intr_alloc(ETS_INTERNAL_TIMER1_INTR_SOURCE, 0, &testint, NULL, &handle);
TEST_ASSERT_EQUAL_HEX32(ESP_OK, err);
vTaskDelay(100 / portTICK_PERIOD_MS);
TEST_ASSERT(int_handled);
TEST_ASSERT(in_int_context);
TEST_ASSERT_EQUAL_HEX32( ESP_OK, esp_intr_free(handle) );
vTaskDelete(NULL);
}
void test_spi_correct_transmission(void) {
delay_ms(1);
// We wish to see if the byte transmitted is the same as the one received.
uint16_t data1 = 0b10101010;
uint16_t data2 = 0b10101011;
spi_write(SPI0, data1);
delay_ms(1);
TEST_ASSERT_EQUAL_HEX32(~data1, ~spi_read(SPI0));
// We also want to see the behavior when an overrun is occurred.
spi_write(SPI0, data1);
spi_write(SPI0, data2);
delay_ms(1);
TEST_ASSERT_EQUAL_HEX32(data2, spi_read(SPI0));
}
void test_pwm_channel_polarity() {
pwm_reset_peripheral();
pwm_set_channel_polarity(PWM_CHANNEL_3, PWM_CHANNEL_POLARITY_HIGH);
TEST_ASSERT_EQUAL_UINT32(512, (PWM->PWM_CMR3 & PWM_CMRx_CPOL_MASK ));
pwm_set_channel_polarity(PWM_CHANNEL_3, PWM_CHANNEL_POLARITY_LOW);
TEST_ASSERT_EQUAL_HEX32(0x0, (PWM->PWM_CMR3 & PWM_CMRx_CPOL_MASK ));
}
void test_spi_baud_rate_change(void) {
delay_ms(1);
uint16_t data1 = 0b0101011101001001;
spi_set_selector_bit_length(SPI0, SPI_SELECTOR_0, SPI_BITS_16);
spi_set_selector_clk_polarity(SPI0, SPI_SELECTOR_0, SPI_POLARITY_LOW);
spi_set_selector_clk_phase(SPI0, SPI_SELECTOR_0, SPI_PHASE_LOW);
// test case begin
spi_set_selector_baud_rate(SPI0, SPI_SELECTOR_0, 1);
spi_write(SPI0, data1); // We send both bytes as 16 consecutive bits
delay_ms(1);
TEST_ASSERT_EQUAL_HEX32(data1, spi_read(SPI0));
// new test
spi_set_selector_baud_rate(SPI0, SPI_SELECTOR_0, 2);
spi_write(SPI0, data1); // We send both bytes as 16 consecutive bits
delay_ms(1);
TEST_ASSERT_EQUAL_HEX32(data1, spi_read(SPI0));
}
void test_stringDel_should_delete_and_not_reduce_text_reference(void) {
String *toCompare;
Text *text = t"SelNon";
String *str = stringNew(text);
String *str1 = stringAssign(str);
String *str2 = stringAssign(str);
toCompare = stringDel(str);
TEST_ASSERT_EQUAL(2,toCompare->reference);
TEST_ASSERT_EQUAL_HEX32(0x80000000,str->text->reference);
}
void test_stringNew_should_create_string_with_static_text(void) {
int toCompare;
Text *text = t"DreFick";
String *str = stringNew(text);
toCompare = strcmp(str->text->string,text->string);
TEST_ASSERT_EQUAL(0,toCompare);
TEST_ASSERT_EQUAL(1,str->reference);
TEST_ASSERT_EQUAL(0,str->start);
TEST_ASSERT_EQUAL(7,str->length);
TEST_ASSERT_EQUAL_HEX32(0x80000000,str->text->reference);
}
void testNotEqualHex32sIfSigned(void)
{
_US32 v0, v1;
v0 = -900000;
v1 = 900001;
EXPECT_ABORT_BEGIN
TEST_ASSERT_EQUAL_HEX32(v0, v1);
VERIFY_FAILS_END
}
void test_spi_variable_bit_lenght_transmission(void) {
delay_ms(1);
uint16_t data1 = 0b0101011101001001;
// Now we test sending a double byte and see if one byte is returned while
// the bits_pr_transfer is set to 8 bits.
spi_set_selector_bit_length(SPI0, SPI_SELECTOR_0, SPI_BITS_8);
spi_write(SPI0, data1); // We send both bytes as 16 consecutive bits
delay_ms(1);
// We expect only 1 byte of course (see mask)
TEST_ASSERT_EQUAL_HEX32(0x00FF & data1, spi_read(SPI0));
// Now we test to see if we can change bits_pr_transfer to 9 bits
spi_set_selector_bit_length(SPI0, SPI_SELECTOR_0, SPI_BITS_9);
spi_write(SPI0, data1); // We send both bytes as 16 consecutive bits
delay_ms(1);
// added a bit to mask
TEST_ASSERT_EQUAL_HEX32(0x01FF & data1, spi_read(SPI0));
// Now we test to see if we can change bits_pr_transfer to 14 bits
spi_set_selector_bit_length(SPI0, SPI_SELECTOR_0, SPI_BITS_14);
spi_write(SPI0, data1); // We send both bytes as 16 consecutive bits
delay_ms(1);
TEST_ASSERT_EQUAL_HEX32(0x3FFF & data1, spi_read(SPI0));
}
void test_getProgramCounter_should_able_to_retrive_current_value_0xff00ff(){
clearAllFileRegisters();
fileRegisters[PCLATU] = 0xff;
fileRegisters[PCLATH] = 0x0;
fileRegisters[PCL] = 0xff;
int pc = getProgramCounter();
TEST_ASSERT_EQUAL_HEX32(0xff00ff,pc);
}
HAL_StatusTypeDef mock_uartex_recv_success(UARTEX_HandleTypeDef * hue, uint8_t *pData, uint16_t Size)
{
struct uart_device * udev;
countdown--;
TEST_ASSERT_NOT_NULL(hue);
udev = (struct uart_device*)hue->testdata;
TEST_ASSERT_EQUAL_HEX32(udev->rbuf[0], pData);
TEST_ASSERT_EQUAL(udev->rbuf_size, Size);
return HAL_OK;
}
void test_memoryReadWord_should_read_memory_and_return_data_in_word(void)
{
int size = WORD_SIZE;
uint32_t dataRead = 0, address = 0x20000000;
uint8_t data[] = {0xEF, 0xBE, 0xAD, 0xDE};
readMemory_ExpectAndReturn(_session, address, size, data);
int result = memoryRead(address, &dataRead, WORD_SIZE);
TEST_ASSERT_EQUAL(1, result);
TEST_ASSERT_EQUAL_HEX32(0xDEADBEEF, dataRead);
}
void test_memoryReadByte_should_read_memory_and_return_data_in_byte(void)
{
int size = BYTE_SIZE;
uint32_t address = 0x20000000, dataRead = 0;
uint8_t data[] = {0xAA, 0xBB, 0xCC, 0xDD};
readMemory_ExpectAndReturn(_session, address, size, data);
int result = memoryRead(address, &dataRead, BYTE_SIZE);
TEST_ASSERT_EQUAL(1, result);
TEST_ASSERT_EQUAL_HEX32(0xAA, dataRead);
}
void test_fsfd_should_mock_and_move_to_operand2_0x02480154(void){
int value;
Text *text = textNew("71");
String *str = stringNew(text);
extractValue_ExpectAndReturn(str, 0x154);
extractValue_ExpectAndReturn(str, 0x248);
value = FSFD(str);
TEST_ASSERT_EQUAL_HEX32(value, 0x02480154);
}
/*! @brief Test that init set up routines correctly.
* @param Group name
* @param Test name */
TEST(lcd_driver, init) {
lcd_driver_init();
/* Init 4 bit interface */
TEST_ASSERT_EQUAL_HEX32((1<<LCD_D_DB5)|(1<<LCD_D_DB4)|(1<<LCD_D_DB1)|(1<<LCD_D_DB0), spy_read_lcd_driver_cmd(0));
TEST_ASSERT_EQUAL_HEX32((1<<LCD_D_DB5)|(1<<LCD_D_DB4)|(1<<LCD_D_DB1), spy_read_lcd_driver_cmd(1));
TEST_ASSERT_EQUAL_HEX32(LCD_D_FUNCTION_SET_INIT, spy_read_lcd_driver_cmd(2));
TEST_ASSERT_EQUAL_HEX32(LCD_D_SET_OFF, spy_read_lcd_driver_cmd(3));
TEST_ASSERT_EQUAL_HEX32(LCD_D_CLEAR_DISPLAY, spy_read_lcd_driver_cmd(4));
TEST_ASSERT_EQUAL_HEX32(LCD_D_ENTRY_INIT, spy_read_lcd_driver_cmd(5));
TEST_ASSERT_EQUAL_HEX32(LCD_D_SET_ON, spy_read_lcd_driver_cmd(6));
}
void test_memoryReadWord_should_continute_wait_until_data_is_return(void)
{
int size = WORD_SIZE;
uint32_t dataRead = 0, address = 0x20000000;
uint8_t data[] = {0xEF, 0xBE, 0xAD, 0xDE};
readMemory_ExpectAndReturn(_session, address, size, 0);
tlvService_Expect(_session);
readMemory_ExpectAndReturn(_session, address, size, data);
int result = memoryRead(address, &dataRead, WORD_SIZE);
TEST_ASSERT_EQUAL(1, result);
TEST_ASSERT_EQUAL_HEX32(0xDEADBEEF, dataRead);
}
void test_NS_operand1_should_mock_and_return_0x02670067(void){
int value;
int e;
Text *text = textNew("135");
String *str = stringNew(text);
extractValue_ExpectAndReturn(str, 0x267);
extractValue_ExpectAndReturn(str, 0);
value = NS(str);
TEST_ASSERT_EQUAL_HEX32(value, 0x02670067);
}
void testNotEqualHex32sIfSigned(void)
{
int failed;
_US32 v0, v1;
v0 = -900000;
v1 = 900001;
EXPECT_ABORT_BEGIN
TEST_ASSERT_EQUAL_HEX32(v0, v1);
EXPECT_ABORT_END
failed = Unity.CurrentTestFailed;
Unity.CurrentTestFailed = 0;
TEST_ASSERT_MESSAGE(1U == failed, "This is expected");
}
void test_ONFI_Features_CouldBeChange(void)
{
ONFI_SetFeatures(1, 0x05000000);
TEST_ASSERT_EQUAL_HEX8(0xe0, ONFI_ReadStatus());
//----------------------------------------------------------------
// !!! need to check if set to mode 4 successfully here !!!
//----------------------------------------------------------------
uint8_t buff[5];
buff[4] = 0;
ONFI_GetFeatures(1);
ONFI_receive8(buff, 4);
TEST_ASSERT_EQUAL_HEX8(0x05, buff[0]);
TEST_ASSERT_EQUAL_HEX32(0, get_count(NFC_REG[NFC_FMICFF_SLOT]));
TEST_ASSERT_EQUAL_HEX8(0xe0, ONFI_ReadStatus());
}
tusb_error_t stub_hidd_init(uint8_t coreid, tusb_descriptor_interface_t const* p_interface_desc, uint16_t* p_length, int num_call)
{
switch(num_call)
{
case 0:
TEST_ASSERT_EQUAL_HEX(&app_tusb_desc_configuration.keyboard_interface, p_interface_desc);
break;
case 1:
TEST_ASSERT_EQUAL_HEX32(&app_tusb_desc_configuration.mouse_interface, p_interface_desc);
break;
default:
TEST_FAIL();
return TUSB_ERROR_FAILED;
}
return TUSB_ERROR_NONE;
}
void testEqualHex32s(void)
{
_UU32 v0, v1;
_UU32 *p0, *p1;
v0 = 0x98765432ul;
v1 = 0x98765432ul;
p0 = &v0;
p1 = &v1;
TEST_ASSERT_EQUAL_HEX32(0x98765432ul, 0x98765432ul);
TEST_ASSERT_EQUAL_HEX32(v0, v1);
TEST_ASSERT_EQUAL_HEX32(0x98765432ul, v1);
TEST_ASSERT_EQUAL_HEX32(v0, 0x98765432ul);
TEST_ASSERT_EQUAL_HEX32(*p0, v1);
TEST_ASSERT_EQUAL_HEX32(*p0, *p1);
TEST_ASSERT_EQUAL_HEX32(*p0, 0x98765432ul);
}
void test_ONFI_ReadPage_ShouldWork(void)
{
unsigned const int data_bytes = kKLEN_DATA << 1;
unsigned const int data_pack = kNLEN_DATA << 1;
unsigned const int aux_bytes = kKLEN_AUX << 1;
unsigned const int aux_pack = kNLEN_AUX << 1;
setup_page_buff();
setup_NFC_FTL();
TEST_ASSERT_EQUAL_HEX32(0x40, NFC_REG[NFC_DMARFF_SLOT]);
//----------------------------------------------------------------
// Set up DMAR
NFC_REG[NFC_DMAR_ENDCNT] = (data_bytes / 8) - 1;
//----------------------------------------------------------------
// Enable Paths
NFC_REG[NFC_ENABLE] |= NFC_ENABLE_DMAR | NFC_ENABLE_F2H | NFC_ENABLE_BCHD;
ONFI_ReadPage(0x010004, 0x0);
ONFI_dma_read((data_pack / 2), 0);
ONFI_ChangeReadColumn(0x010D);
ONFI_dma_read((aux_pack / 2), ONFI_AUX_DATA);
receive(page_buff, data_bytes);
//----------------------------------------------------------------
// Check FLASH data
DBGPRINTF("ReadPage_via_RSDM1:\n");
for (int i = 0; i < 2; i++)
DBGPRINTF("%08x, ", page_buff[i]);
DBGPRINTF("\n");
for (int i = 0; i < 4; i++)
DBGPRINTF("%08x, ", page_buff[(data_bytes / 4) - 2 + i]);
DBGPRINTF("\n");
//----------------------------------------------------------------
// Disable Paths
NFC_REG[NFC_ENABLE] &= (~NFC_ENABLE_DMAR);
// Writing FTLRAM
//----------------------------------------------------------------
// Enable Paths
NFC_REG[NFC_ENABLE] |= NFC_ENABLE_FTLWR;
//----------------------------------------------------------------
// wait for FTL_DONE
while ((NFC_REG[NFC_STATE] >> 24) != 1) {}
//----------------------------------------------------------------
// Disable Paths
NFC_REG[NFC_ENABLE] &= (~NFC_ENABLE_FTLWR);
NFC_DMARFFRD[0] = 2; // pop
NFC_DMARFFRD[0] = 0; // lower DOWRD
DBGPRINTF("%x, ", NFC_DMAWFFRD[0]);
NFC_DMARFFRD[0] = 1; // upper DWORD
DBGPRINTF("%x, ", NFC_DMAWFFRD[0]);
TEST_ASSERT_EQUAL_HEX32(0x40, NFC_REG[NFC_DMARFF_SLOT]);
}
TEST(UsartIO_DMA, ReadWhenBytesToReadMoreThanBytesInBufferAndHalReady)
{
const char soft[] = "test";
const char hard[] = "driven";
char buf[64];
int read;
struct uart_device huio = { .rbuf_size = 64, .tbuf_size = 64, };
UARTEX_HandleTypeDef hue;
uio_testdata_t td;
// struct UARTEX_Operations uart_ops;
char rxbuf0[64];
char rxbuf1[64];
memset(&huio, 0, sizeof(huio));
memset(&hue, 0, sizeof(hue));
hue.huart.State = HAL_UART_STATE_RESET;
huio.handle = &hue;
huio.rbuf[0] = rxbuf0;
huio.rbuf[1] = rxbuf1;
// memset(&uart_ops, 0, sizeof(uart_ops));
// uart_ops.swap = swap_mock_hal_ok;
// huio.handle->ops = &uart_ops;
memset(&huio.handle->ops, 0, sizeof(struct UARTEX_Operations));
huio.handle->ops.swap = swap_mock_hal_ok;
memset(&td, 0, sizeof(td));
huio.handle->testdata = &td;
fill_rx_testdata(&huio, 0, 1, soft, strlen(soft), hard, strlen(hard), UART_IO_BUFFER_SIZE);
memset(buf, 0, sizeof(buf));
read = UART_IO_Read(&huio, buf, sizeof(buf));
TEST_ASSERT_EQUAL(strlen(soft) + strlen(hard), read);
TEST_ASSERT_EQUAL_STRING("testdriven", buf);
}
static HAL_StatusTypeDef swap_mock_hal_error(UARTEX_HandleTypeDef* h, uint8_t* buf, size_t size, uint32_t* m0ar, int* ndtr)
{
return HAL_ERROR;
}
static HAL_StatusTypeDef swap_mock_hal_busy(UARTEX_HandleTypeDef* h, uint8_t* buf, size_t size, uint32_t* m0ar, int* ndtr)
{
return HAL_BUSY;
}
static HAL_StatusTypeDef swap_mock_hal_timeout(UARTEX_HandleTypeDef* h, uint8_t* buf, size_t size, uint32_t* m0ar, int* ndtr)
{
return HAL_TIMEOUT;
}
TEST(UsartIO_DMA, ReadWhenBytesToReadMoreThanBytesInBufferAndHalErrorBusyTimeoutAndBufferNotEmpty)
{
const char soft[] = "test";
const char hard[] = "driven";
char buf[64];
int read;
struct uart_device huio = { .rbuf_size = 64, .tbuf_size = 64, };
UARTEX_HandleTypeDef hue;
uio_testdata_t td;
// struct UARTEX_Operations uart_ops;
char rxbuf0[64];
char rxbuf1[64];
memset(&huio, 0, sizeof(huio));
memset(&hue, 0, sizeof(hue));
hue.huart.State = HAL_UART_STATE_RESET;
huio.handle = &hue;
huio.rbuf[0] = rxbuf0;
huio.rbuf[1] = rxbuf1;
// memset(&uart_ops, 0, sizeof(uart_ops));
// huio.handle->ops = &uart_ops;
memset(&huio.handle->ops, 0, sizeof(huio.handle->ops));
memset(&td, 0, sizeof(td));
huio.handle->testdata = &td;
// fill and mock
fill_rx_testdata(&huio, 0, 1, soft, strlen(soft), hard, strlen(hard), UART_IO_BUFFER_SIZE);
// uart_ops.swap = swap_mock_hal_error; // swap_mock_hal_ok;
huio.handle->ops.swap = swap_mock_hal_error;
memset(buf, 0, sizeof(buf));
read = UART_IO_Read(&huio, buf, sizeof(buf));
TEST_ASSERT_EQUAL(strlen(soft), read);
TEST_ASSERT_EQUAL_STRING(soft, buf);
// refill and remock
fill_rx_testdata(&huio, 1, 1, soft, strlen(soft), hard, strlen(hard), UART_IO_BUFFER_SIZE);
// uart_ops.swap = swap_mock_hal_busy;
huio.handle->ops.swap = swap_mock_hal_busy;
memset(buf, 0, sizeof(buf));
read = UART_IO_Read(&huio, buf, sizeof(buf));
TEST_ASSERT_EQUAL(strlen(soft), read);
TEST_ASSERT_EQUAL_STRING(soft, buf);
// refill and remock
fill_rx_testdata(&huio, 1, 2, soft, strlen(soft), hard, strlen(hard), UART_IO_BUFFER_SIZE);
// uart_ops.swap = swap_mock_hal_timeout;
huio.handle->ops.swap = swap_mock_hal_timeout;
memset(buf, 0, sizeof(buf));
read = UART_IO_Read(&huio, buf, sizeof(buf));
TEST_ASSERT_EQUAL(strlen(soft), read);
TEST_ASSERT_EQUAL_STRING(soft, buf);
}
TEST(UsartIO_DMA, ReadWhenBytesToReadMoreThanBytesInBufferAndHalErrorBusyTimeoutAndBufferEmpty)
{
/** This case says if upper buffer is empty and HAL in error state, the function should return error **/
char buf[64];
int read;
struct uart_device huio = { .rbuf_size = 64, .tbuf_size = 64, };
UARTEX_HandleTypeDef hue;
uio_testdata_t td;
// struct UARTEX_Operations uart_ops;
char rxbuf0[64];
char rxbuf1[64];
memset(&huio, 0, sizeof(huio));
memset(&hue, 0, sizeof(hue));
hue.huart.State = HAL_UART_STATE_RESET;
huio.handle = &hue;
huio.rbuf[0] = rxbuf0;
huio.rbuf[1] = rxbuf1;
// memset(&uart_ops, 0, sizeof(uart_ops));
// huio.handle->ops = &uart_ops;
memset(&huio.handle->ops, 0, sizeof(huio.handle->ops));
memset(&td, 0, sizeof(td));
huio.handle->testdata = &td;
fill_rx_testdata(&huio, 1, 1, 0, 0, 0, 0, 0);
huio.handle->ops.swap = swap_mock_hal_error;
memset(buf, 0, sizeof(buf));
read = UART_IO_Read(&huio, buf, sizeof(buf));
TEST_ASSERT_EQUAL(-1, read);
TEST_ASSERT_EQUAL(EINVAL, errno);
fill_rx_testdata(&huio, 1, 1, 0, 0, 0, 0, 0);
huio.handle->ops.swap = swap_mock_hal_busy;
memset(buf, 0, sizeof(buf));
read = UART_IO_Read(&huio, buf, sizeof(buf));
TEST_ASSERT_EQUAL(-1, read);
TEST_ASSERT_EQUAL(EBUSY, errno);
fill_rx_testdata(&huio, 1, 1, 0, 0, 0, 0, 0);
huio.handle->ops.swap = swap_mock_hal_timeout;
memset(buf, 0, sizeof(buf));
read = UART_IO_Read(&huio, buf, sizeof(buf));
TEST_ASSERT_EQUAL(-1, read);
TEST_ASSERT_EQUAL(EIO, errno);
}
///////////////////////////////////////////////////////////////////////////////
#if 0 // open tests commented out
/******************************************************************************
*
* Test Cases for USART_IO_Open
*
*****************************************************************************/
//TEST(UsartIO_DMA, OpenInvalidArgs)
//{
// TEST_ASSERT_EQUAL(0, UART_IO_Open(0));
// TEST_ASSERT_EQUAL(EINVAL, errno);
// TEST_ASSERT_EQUAL(0, UART_IO_Open(7));
// TEST_ASSERT_EQUAL(EINVAL, errno);
//}
//TEST(UsartIO_DMA, OpenPortUnavailable) /** handle does not exist **/
//{
// UART_IO_SetHandle(6, 0);
//
// TEST_ASSERT_EQUAL(0, UART_IO_Open(6));
// TEST_ASSERT_EQUAL(ENODEV, errno);
//}
//TEST(UsartIO_DMA, OpenInvalidHandle)
//{
// m_huio.handle = 0;
// UART_IO_SetHandle(6, &m_huio);
// TEST_ASSERT_EQUAL(0, UART_IO_Open(6));
//}
//TEST(UsartIO_DMA, OpenHalNotResetState)
//{
// m_huio.handle->State = HAL_UART_STATE_READY;
//
// UART_IO_SetHandle(6, &m_huio);
//
// TEST_ASSERT_EQUAL(0, UART_IO_Open(6));
// TEST_ASSERT_EQUAL(EBUSY, errno);
//}
//TEST(UsartIO_DMA, OpenHalInitOkReceiveOk)
//{
// UART_IO_SetHandle(6, &m_huio);
// usart_apis.HAL_UART_Init = m_init_hal_ok;
// usart_apis.HAL_UART_Receive_DMA = m_receive_hal_ok;
//
// TEST_ASSERT_EQUAL(&m_huio, UART_IO_Open(6));
//
// /** should we check HAL state? I don't think so, cause
// the function trust the return value, rather than
// checking state **/
//
// /** all following should be checked since they ARE
// the results of action of the function under test **/
// TEST_ASSERT_TRUE(m_rx_m0ar == (uint32_t)m_huio.rbuf[0]);
// TEST_ASSERT_TRUE(m_rx_ndtr == UART_IO_BUFFER_SIZE);
//
// TEST_ASSERT_TRUE(m_huio.rx_upper == m_huio.rbuf[1]);
// TEST_ASSERT_TRUE(m_huio.rx_tail == &m_huio.rx_upper[UART_IO_BUFFER_SIZE]);
// TEST_ASSERT_TRUE(m_huio.rx_head == m_huio.rx_tail);
//
// TEST_ASSERT_TRUE(m_huio.tx_head == &m_huio.tbuf[1][0]);
// TEST_ASSERT_TRUE(m_huio.tx_tail == m_huio.tx_head);
//}
#endif
///////////////////////////////////////////////////////////////////////////////
// Write
//
TEST(UsartIO_DMA, WriteInvalidArgs)
{
char c;
struct uart_device huio = { .rbuf_size = 64, .tbuf_size = 64, };
TEST_ASSERT_EQUAL(-1, UART_IO_Write(0, &c, 1));
TEST_ASSERT_EQUAL(EINVAL, errno);
TEST_ASSERT_EQUAL(-1, UART_IO_Write(&huio, 0, 1));
TEST_ASSERT_EQUAL(EINVAL, errno);
/** no effect for errno**/
/** may be changed future, man page write **/
TEST_ASSERT_EQUAL(0, UART_IO_Write(&huio, &c, 0));
}
TEST(UsartIO_DMA, WriteHalStateTimeoutErrorReset)
{
// HAL_UART_STATE_TIMEOUT means hardware error.
// HAL_UART_STATE_RESET should not happen.
// HAL_UART_STATE_ERROR are not used in firmware 1.1
char c;
UARTEX_HandleTypeDef huartex;
struct uart_device huio = { .rbuf_size = 64, .tbuf_size = 64, };
huio.handle = &huartex;
errno = 0;
huio.handle->huart.State = HAL_UART_STATE_TIMEOUT;
TEST_ASSERT_EQUAL(-1, UART_IO_Write(&huio, &c, 1));
TEST_ASSERT_EQUAL(EIO, errno);
errno = 0;
huio.handle->huart.State = HAL_UART_STATE_RESET;
TEST_ASSERT_EQUAL(-1, UART_IO_Write(&huio, &c, 1));
TEST_ASSERT_EQUAL(EIO, errno);
errno = 0;
huio.handle->huart.State = HAL_UART_STATE_ERROR;
TEST_ASSERT_EQUAL(-1, UART_IO_Write(&huio, &c, 1));
TEST_ASSERT_EQUAL(EIO, errno);
}
static HAL_StatusTypeDef send_mock_hal_ok(UARTEX_HandleTypeDef *huartex, uint8_t *pData, uint16_t Size)
{
uio_testdata_t* td = huartex->testdata;
// memset(tx_dma_buffer, 0, UART_IO_BUFFER_SIZE);
// memmove(tx_dma_buffer, pData, Size);
// memset(td->txdma_buf, 0, UART_IO_BUFFER_SIZE);
// memmove(td->txdma_buf, pData, Size);
td->txdma_buf = (char*)pData;
// m_tx_m0ar = (uint32_t)pData;
// m_tx_ndtr = Size;
td->tx_m0ar = (uint32_t)pData;
td->tx_ndtr = Size;
return HAL_OK;
}
static HAL_StatusTypeDef send_mock_hal_busy(UARTEX_HandleTypeDef *huartex, uint8_t *pData, uint16_t Size)
{
return HAL_BUSY;
}
TEST(UsartIO_DMA, WriteBufferSpaceAdequateAndHalReady) // write
{
char s1[] = "test";
char s2[] = "driven";
char s3[] = "testdriven";
int written;
///////////////////////////
struct uart_device huio = { .rbuf_size = 64, .tbuf_size = 64, };
UARTEX_HandleTypeDef hue;
uio_testdata_t td;
// struct UARTEX_Operations uart_ops;
char txbuf0[64];
char txbuf1[64];
memset(&huio, 0, sizeof(huio));
memset(&hue, 0, sizeof(hue));
hue.huart.State = HAL_UART_STATE_RESET;
huio.handle = &hue;
huio.tbuf[0] = txbuf0;
huio.tbuf[1] = txbuf1;
// memset(&uart_ops, 0, sizeof(uart_ops));
// huio.handle->ops = &uart_ops;
memset(&huio.handle->ops, 0, sizeof(huio.handle->ops));
memset(&td, 0, sizeof(td));
huio.handle->testdata = &td;
//////////////////////////////
// HAL_UART_Transmit_DMA
fill_tx_testdata(&huio, 1, s1, strlen(s1), 0, 0, 0);
// uart_ops.send = send_mock_hal_ok;
huio.handle->ops.send = send_mock_hal_ok;
huio.handle->huart.State = HAL_UART_STATE_READY;
written = UART_IO_Write(&huio, s2, strlen(s2));
TEST_ASSERT_EQUAL(strlen(s2), written);
TEST_ASSERT_EQUAL_MEMORY(s3, td.txdma_buf, strlen(s3));
TEST_ASSERT_EQUAL_HEX32(huio.tbuf[1], (char*)td.tx_m0ar);
TEST_ASSERT_EQUAL(strlen(s3), td.tx_ndtr);
TEST_ASSERT_EQUAL_HEX32(huio.tbuf[0], huio.tx_head);
TEST_ASSERT_EQUAL_HEX32(huio.tbuf[0], huio.tx_tail);
}
TEST(UsartIO_DMA, WriteBufferSpaceAdequateAndHalBusy)
{
char s1[] = "test";
char s2[] = "driven";
char s3[] = "testdriven";
int written;
///////////////////////////
struct uart_device huio = { .rbuf_size = 64, .tbuf_size = 64, };
UARTEX_HandleTypeDef hue;
uio_testdata_t td;
// struct UARTEX_Operations uart_ops;
char txbuf0[64];
char txbuf1[64];
memset(&huio, 0, sizeof(huio));
memset(&hue, 0, sizeof(hue));
hue.huart.State = HAL_UART_STATE_RESET;
huio.handle = &hue;
huio.tbuf[0] = txbuf0;
huio.tbuf[1] = txbuf1;
// memset(&uart_ops, 0, sizeof(uart_ops));
// huio.handle->ops = &uart_ops;
memset(&huio.handle->ops, 0, sizeof(huio.handle->ops));
memset(&td, 0, sizeof(td));
huio.handle->testdata = &td;
//////////////////////////////
// uart_ops.send = send_mock_hal_busy;
huio.handle->ops.send = send_mock_hal_busy;
hue.huart.State = HAL_UART_STATE_READY;
fill_tx_testdata(&huio, 1, s1, strlen(s1), 0, 0, 0);
written = UART_IO_Write(&huio, s2, strlen(s2));
TEST_ASSERT_EQUAL(strlen(s2), written);
TEST_ASSERT_EQUAL_MEMORY(s3, huio.tbuf[1], strlen(s3));
TEST_ASSERT_EQUAL_HEX32(huio.tbuf[1], huio.tx_head);
TEST_ASSERT_EQUAL(strlen(s3), huio.tx_tail - huio.tx_head);
// usart_apis.HAL_UART_Transmit_DMA = m_transmit_hal_busy;
// fill_tx_upper(1, s1, strlen(s1));
// m_huio.handle->huart.State = HAL_UART_STATE_READY; /** otherwise trapped **/
//
// written = UART_IO_Write(&m_huio, s2, strlen(s2));
// TEST_ASSERT_EQUAL(strlen(s2), written);
//
// TEST_ASSERT_EQUAL_MEMORY(s3, m_huio.tbuf[1], strlen(s3));
// TEST_ASSERT_EQUAL_HEX32(m_huio.tbuf[1], m_huio.tx_head);
// TEST_ASSERT_EQUAL(strlen(s3), m_huio.tx_tail - m_huio.tx_head);
}
TEST(UsartIO_DMA, WriteBufferSpaceInadequateAndHalReady)
{
char s1[UART_IO_BUFFER_SIZE/2];
char s2[UART_IO_BUFFER_SIZE];
char s3[UART_IO_BUFFER_SIZE*2];
int written;
///////////////////////////
struct uart_device huio = { .rbuf_size = 64, .tbuf_size = 64, };
UARTEX_HandleTypeDef hue;
uio_testdata_t td;
// struct UARTEX_Operations uart_ops;
char txbuf0[64];
char txbuf1[64];
memset(&huio, 0, sizeof(huio));
memset(&hue, 0, sizeof(hue));
hue.huart.State = HAL_UART_STATE_RESET;
huio.handle = &hue;
huio.tbuf[0] = txbuf0;
huio.tbuf[1] = txbuf1;
// memset(&uart_ops, 0, sizeof(uart_ops));
// huio.handle->ops = &uart_ops;
memset(&huio.handle->ops, 0, sizeof(huio.handle->ops));
memset(&td, 0, sizeof(td));
huio.handle->testdata = &td;
//////////////////////////////
memset(s1, 'a', sizeof(s1));
memset(s2, 'b', sizeof(s2));
memset(s3, 0, sizeof(s3));
memset(s3, 'a', sizeof(s1));
memset(&s3[sizeof(s1)], 'b', sizeof(s2));
// uart_ops.send = send_mock_hal_ok;
huio.handle->ops.send = send_mock_hal_ok;
hue.huart.State = HAL_UART_STATE_READY;
fill_tx_testdata(&huio, 1, s1, sizeof(s1), 0, 0, 0);
written = UART_IO_Write(&huio, s2, sizeof(s2));
TEST_ASSERT_EQUAL(sizeof(s2), written);
/** the dma buffer **/
TEST_ASSERT_EQUAL_MEMORY(s3, td.txdma_buf, UART_IO_BUFFER_SIZE);
TEST_ASSERT_EQUAL_HEX32(huio.tbuf[1], (char*)td.tx_m0ar);
TEST_ASSERT_EQUAL(UART_IO_BUFFER_SIZE, td.tx_ndtr);
/** the upper buffer **/
TEST_ASSERT_EQUAL_HEX32(huio.tbuf[0], huio.tx_head);
TEST_ASSERT_EQUAL(UART_IO_BUFFER_SIZE - UART_IO_BUFFER_SIZE/2, huio.tx_tail - huio.tx_head);
TEST_ASSERT_EQUAL_MEMORY(&s3[UART_IO_BUFFER_SIZE], huio.tx_head, UART_IO_BUFFER_SIZE/2);
// usart_apis.HAL_UART_Transmit_DMA = m_transmit_hal_ok;
// fill_tx_upper(1, s1, sizeof(s1));
// m_huio.handle->huart.State = HAL_UART_STATE_READY; /** otherwise trapped **/
//
// written = UART_IO_Write(&m_huio, s2, sizeof(s2));
// TEST_ASSERT_EQUAL(sizeof(s2), written);
//
// TEST_ASSERT_EQUAL_MEMORY(s3, tx_dma_buffer, UART_IO_BUFFER_SIZE);
// TEST_ASSERT_EQUAL_HEX32(m_huio.tbuf[1], (char*)m_tx_m0ar);
// TEST_ASSERT_EQUAL(UART_IO_BUFFER_SIZE, m_tx_ndtr);
//
// TEST_ASSERT_EQUAL_HEX32(m_huio.tbuf[0], m_huio.tx_head);
// TEST_ASSERT_EQUAL(UART_IO_BUFFER_SIZE - UART_IO_BUFFER_SIZE/2, m_huio.tx_tail-m_huio.tx_head);
// TEST_ASSERT_EQUAL_MEMORY(&s3[UART_IO_BUFFER_SIZE], m_huio.tx_head, UART_IO_BUFFER_SIZE/2);
}
TEST(UsartIO_DMA, WriteBufferSpaceInadequateAndHalBusy)
{
char s1[UART_IO_BUFFER_SIZE/2];
char s2[UART_IO_BUFFER_SIZE];
char s3[UART_IO_BUFFER_SIZE*2];
int written;
memset(s1, 'a', sizeof(s1));
memset(s2, 'b', sizeof(s2));
memset(s3, 0, sizeof(s3));
memset(s3, 'a', sizeof(s1));
memset(&s3[sizeof(s1)], 'b', sizeof(s2));
///////////////////////////
struct uart_device huio = { .rbuf_size = 64, .tbuf_size = 64, };
UARTEX_HandleTypeDef hue;
uio_testdata_t td;
char txbuf0[64];
char txbuf1[64];
memset(&huio, 0, sizeof(huio));
memset(&hue, 0, sizeof(hue));
hue.huart.State = HAL_UART_STATE_RESET;
huio.handle = &hue;
huio.tbuf[0] = txbuf0;
huio.tbuf[1] = txbuf1;
// memset(&uart_ops, 0, sizeof(uart_ops));
// huio.handle->ops = &uart_ops;
memset(&huio.handle->ops, 0, sizeof(huio.handle->ops));
memset(&td, 0, sizeof(td));
huio.handle->testdata = &td;
//////////////////////////////
// uart_ops.send = send_mock_hal_busy;
huio.handle->ops.send = send_mock_hal_busy;
hue.huart.State = HAL_UART_STATE_READY;
fill_tx_testdata(&huio, 1, s1, sizeof(s1), 0, 0, 0);
written = UART_IO_Write(&huio, s2, sizeof(s2));
// usart_apis.HAL_UART_Transmit_DMA = m_transmit_hal_busy;
// fill_tx_upper(1, s1, sizeof(s1));
// m_huio.handle->huart.State = HAL_UART_STATE_READY; /** otherwise trapped **/
//
// written = UART_IO_Write(&m_huio, s2, sizeof(s2));
TEST_ASSERT_EQUAL(UART_IO_BUFFER_SIZE - sizeof(s1), written);
TEST_ASSERT_EQUAL_HEX32(huio.tbuf[1], huio.tx_head);
TEST_ASSERT_EQUAL_HEX32(&huio.tbuf[1][UART_IO_BUFFER_SIZE], huio.tx_tail); // full
TEST_ASSERT_EQUAL_MEMORY(s3, huio.tx_head, UART_IO_BUFFER_SIZE); // content
// TEST_ASSERT_EQUAL_HEX32(m_huio.tbuf[1], m_huio.tx_head);
// TEST_ASSERT_EQUAL_HEX32(&m_huio.tbuf[1][UART_IO_BUFFER_SIZE], m_huio.tx_tail);
// TEST_ASSERT_EQUAL_MEMORY(s3, m_huio.tx_head, UART_IO_BUFFER_SIZE);
}
///////////////////////////////////////////////////////////////////////////////
// Open Test
// 1. all success
// 2. create uartex handle failed
// 3. uartex init failed (NO this case !)
// 4. malloc failed x 4
// 5. recv failed (NO this case !)
//
UARTEX_HandleTypeDef* mock_huartex_create_success(struct msp_factory * msp, int num)
{
struct uart_device * udev;
countdown--;
TEST_ASSERT_NOT_NULL(msp);
udev = (struct uart_device*)msp->testdata;
TEST_ASSERT_EQUAL(udev->dev.number, num);
return (UARTEX_HandleTypeDef*)udev->testdata; // the fake handle
}
UARTEX_HandleTypeDef* mock_huartex_create_fail(struct msp_factory * msp, int num)
{
struct uart_device * udev;
countdown--;
TEST_ASSERT_NOT_NULL(msp);
udev = (struct uart_device*)msp->testdata;
TEST_ASSERT_EQUAL(udev->dev.number, num);
return NULL;
}
HAL_StatusTypeDef mock_uartex_init_success(UARTEX_HandleTypeDef * hue)
{
countdown--;
TEST_ASSERT_EQUAL(HAL_UART_STATE_RESET, hue->huart.State);
hue->huart.State = HAL_UART_STATE_READY;
return HAL_OK;
}
///////////////////////////////////////////////////////////////////////////////
// The func should
// 1) create uartex handle
// 2) init uart with the handle
// 3) if OK, allocate and init buffer
// 4) start to receive
// 5) init file
TEST(UsartIO_DMA, OpenWhenDeviceNotOpenedAllSuccess)
{
int ret;
struct file file = {0};
struct msp_factory msp = {0};
struct UARTEX_HandleTypeDef huartex = {0};
struct uart_device udev =
{
.dev = { .name = "UART2", .number = 2, },
.msp = &msp,
.rbuf_size = 13,
.tbuf_size = 17,
};
udev.testdata = &huartex;
huartex.testdata = &udev; //
msp.testdata = &udev;
msp.create_uartex_handle_by_port = mock_huartex_create_success; // create uartex handle
huartex.ops.init = mock_uartex_init_success; // init uart (hardware)
huartex.ops.recv = mock_uartex_recv_success; // start recv
countdown = 3;
ret = UART_IO_Open(&udev.dev, &file);
TEST_ASSERT_EQUAL(0, countdown); // all three func called
/////////////////////////////////////////////////////////////////////////////
// handle created.
TEST_ASSERT_EQUAL(0, ret); // return success
TEST_ASSERT_NOT_NULL(udev.handle); // udev handle set
TEST_ASSERT_EQUAL_HEX32(&huartex, udev.handle); // udev handle mocked
/////////////////////////////////////////////////////////////////////////////
// hal inited.
TEST_ASSERT_EQUAL(HAL_UART_STATE_READY, udev.handle->huart.State);
/////////////////////////////////////////////////////////////////////////////
// device internals
TEST_ASSERT_MEMSIZE(udev.rbuf_size, udev.rbuf[0]);
TEST_ASSERT_MEMSIZE(udev.rbuf_size, udev.rbuf[1]);
TEST_ASSERT_EQUAL_HEX32(udev.rbuf[1], udev.rx_upper); // rbuf 1 as upper, 0 as dma
TEST_ASSERT_EQUAL_HEX32(udev.rbuf[1], udev.rx_head);
TEST_ASSERT_EQUAL_HEX32(udev.rbuf[1], udev.rx_tail);
TEST_ASSERT_MEMSIZE(udev.tbuf_size, udev.tbuf[0]);
TEST_ASSERT_MEMSIZE(udev.tbuf_size, udev.tbuf[1]);
TEST_ASSERT_EQUAL_HEX32(udev.tbuf[1], udev.tx_head);
TEST_ASSERT_EQUAL_HEX32(udev.tbuf[1], udev.tx_tail);
TEST_ASSERT_EQUAL(1, udev.open_count);
/////////////////////////////////////////////////////////////////////////////
// file initialized
TEST_ASSERT_EQUAL(&udev, file.private_data);
TEST_ASSERT_EQUAL(udev.dev.f_ops, file.f_ops);
/////////////////////////////////////////////////////////////////////////////
// clean up
free(udev.rbuf[0]);
free(udev.rbuf[1]);
free(udev.tbuf[0]);
free(udev.tbuf[1]);
}
