static int threshold_check_intr_both(struct hwtest_ctx *ctx, struct therm_threshold *thrs) {
/* enable the IRQs on both sides */
threshold_set_intr_dir(ctx, thrs, 3);
threshold_gen_intr_dir(ctx, thrs, 1);
TEST_READ_MASK(0x1100, 1 << thrs->pbus_irq_bit, 1 << thrs->pbus_irq_bit,
"rising: unexpected pbus intr bit, expected bit %i",
thrs->pbus_irq_bit);
threshold_gen_intr_dir(ctx, thrs, -1);
TEST_READ_MASK(0x1100, 1 << thrs->pbus_irq_bit, 1 << thrs->pbus_irq_bit,
"falling: unexpected pbus intr bit, expected bit %i",
thrs->pbus_irq_bit);
return HWTEST_RES_PASS;
}
static int threshold_check_state(struct hwtest_ctx *ctx, const struct therm_threshold *thrs) {
int i, dir, temp, exp_state;
threshold_reset(ctx);
nva_mask(ctx->cnum, 0x20010, 0x80000000, 0x80000000);
i = 1;
dir = 1;
while (i > 0) {
/* set the threshold */
threshold_set(ctx, thrs, i);
/* calculate the expected state */
do {
temp = nva_rd32(ctx->cnum, 0x20014) & 0x3fff;
if (thrs->dir_inverted)
exp_state = (temp < i);
else
exp_state = (temp > i);
} while (temp != (nva_rd32(ctx->cnum, 0x20014) & 0x3fff));
/* check the state */
TEST_READ_MASK(thrs->dir_addr, exp_state << thrs->dir_status_bit, 1 << thrs->dir_status_bit,
"invalid state at temperature %i: dir (%i), threshold (%i)", temp, dir, i);
if (i == 0x3fff)
dir = -1;
i += dir;
}
return HWTEST_RES_PASS;
}
static int threshold_check_intr_both(struct hwtest_ctx *ctx, struct therm_threshold *thrs) {
uint32_t intr_dir;
/* enable the IRQs on both sides */
intr_dir = 3;
nva_wr32(ctx->cnum, thrs->dir_addr, intr_dir << (thrs->dir_lshift));
threshold_gen_intr_dir(ctx, thrs, 1);
TEST_READ_MASK(0x1100, 1 << thrs->pbus_irq_bit, 1 << thrs->pbus_irq_bit,
"rising: unexpected pbus intr bit, expected bit %i",
thrs->pbus_irq_bit);
threshold_gen_intr_dir(ctx, thrs, -1);
TEST_READ_MASK(0x1100, 1 << thrs->pbus_irq_bit, 1 << thrs->pbus_irq_bit,
"falling: unexpected pbus intr bit, expected bit %i",
thrs->pbus_irq_bit);
return HWTEST_RES_PASS;
}
static int threshold_check_intr_falling(struct hwtest_ctx *ctx, struct therm_threshold *thrs) {
uint32_t intr_dir;
/* enable the falling IRQs */
if (thrs->dir_inverted)
intr_dir = 2;
else
intr_dir = 1;
threshold_set_intr_dir(ctx, thrs, intr_dir);
threshold_gen_intr_dir(ctx, thrs, -1);
TEST_READ_MASK(0x1100, 1 << thrs->pbus_irq_bit, 1 << thrs->pbus_irq_bit,
"falling: unexpected pbus intr bit, expected bit %i",
thrs->pbus_irq_bit);
threshold_gen_intr_dir(ctx, thrs, 1);
TEST_READ_MASK(0x1100, 0x0, 1 << thrs->pbus_irq_bit,
"rising: unexpected pbus intr bit, didn't expect an IRQ%s", "");
return HWTEST_RES_PASS;
}
static int test_clock_gating_thermal_protect_crit(struct hwtest_ctx *ctx) {
int temp, lower_thrs;
uint8_t rnd_div = 1 + (rand() % 6);
uint8_t rnd_pwm = 1 + (rand() % 0xfe);
clock_gating_reset(ctx);
temp = nva_rd32(ctx->cnum, 0x20014) & 0x3fff;
lower_thrs = temp - 0x200; /* just to be sure the threshold is under the current temp */
if (lower_thrs < 0)
lower_thrs = 0;
nva_mask(ctx->cnum, 0x20010, 0x80003fff, 0x80000000 | lower_thrs);
nva_wr32(ctx->cnum, 0x20060, (rnd_pwm << 8) | rnd_div); /* div = rnd_div */
TEST_READ_MASK(0x20048, 0x800, 0x800, "THERMAL_PROTECT_DIV_ACTIVE is not active!%s", "");
TEST_READ_MASK(0x20048, rnd_pwm, 0xff, "PWM isn't %i", rnd_pwm);
TEST_READ_MASK(0x20048, rnd_div << 12, 0x7000, "divisor isn't %i", rnd_div);
return HWTEST_RES_PASS;
}
static int test_clock_gating_force_div_pwm(struct hwtest_ctx *ctx) {
int i;
clock_gating_reset(ctx);
for (i = 0; i < 0x100; i++) {
nva_wr32(ctx->cnum, 0x20064, (i << 8) | 2);
TEST_READ_MASK(0x20048, 0x2200 | i, 0xffff, "iteration %i/255 failed", i);
}
return HWTEST_RES_PASS;
}
static int test_clock_gating_force_div_only(struct hwtest_ctx *ctx) {
int i;
clock_gating_reset(ctx);
for (i = 1; i < 4; i++) {
nva_wr32(ctx->cnum, 0x20064, i);
TEST_READ_MASK(0x20048, (i << 12) | 0x200, 0xffff, "iteration %i/4 failed", i);
}
return HWTEST_RES_PASS;
}
