/**
* Support routine for F15OrPmNbAfterReset to perform MSR initialization on one
* core of each die in a family 15h socket.
*
* This function implements steps 1 - 13 on each core.
*
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
F15OrPmNbAfterResetOnCore (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 NbPsCtrlOnEntry;
UINT32 NbPsCtrlOnExit;
UINT64 LocalMsrRegister;
PCI_ADDR PciAddress;
// 1. Temp1 = D18F5x170[SwNbPstateLoDis].
// 2. Temp2 = D18F5x170[NbPstateDisOnP0].
// 3. Temp3 = D18F5x170[NbPstateThreshold].
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
PciAddress.Address.Function = FUNC_5;
PciAddress.Address.Register = NB_PSTATE_CTRL;
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnEntry, StdHeader);
// Check if NB P-states were disabled, and if so, prevent any changes from occurring.
if (((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateMaxVal != 0) {
// 4. If MSRC001_0070[NbPstate] = 1, go to step 9
LibAmdMsrRead (MSR_COFVID_CTL, &LocalMsrRegister, StdHeader);
if (((COFVID_CTRL_MSR *) &LocalMsrRegister)->NbPstate == 0) {
// 5. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
// 6. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
TransitionToNbLow (PciAddress, StdHeader);
// 7. Set D18F5x170[SwNbPstateLoDis] = 1.
// 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
// Go to step 13.
TransitionToNbHigh (PciAddress, StdHeader);
} else {
// 9. Set D18F5x170[SwNbPstateLoDis] = 1.
// 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
TransitionToNbHigh (PciAddress, StdHeader);
// 11. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
// 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
TransitionToNbLow (PciAddress, StdHeader);
}
// 13. Set D18F5x170[SwNbPstateLoDis] = Temp1, D18F5x170[NbPstateDisOnP0] = Temp2, and
// D18F5x170[NbPstateThreshold] = Temp3.
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->SwNbPstateLoDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->SwNbPstateLoDis;
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateDisOnP0 = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateDisOnP0;
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateThreshold = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateThreshold;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
}
}
/**
* Support routine for F15KvPmNbAfterReset to perform MSR initialization on one
* core of each die in a family 15h socket.
*
* This function implements steps 1 - 15 on each core.
*
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
F15KvPmNbAfterResetOnCore (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 NbPsCtrlOnEntry;
UINT32 NbPsCtrlOnExit;
UINT64 LocalMsrRegister;
PCI_ADDR PciAddress;
IDS_HDT_CONSOLE (CPU_TRACE, " F15KvPmNbAfterResetOnCore\n");
// 1. Temp1 = D18F5x170[SwNbPstateLoDis].
// 2. Temp2 = D18F5x170[NbPstateDisOnP0].
// 3. Temp3 = D18F5x170[NbPstateThreshold].
// 4. Temp4 = D18F5x170[NbPstateGnbSlowDis].
PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnEntry, StdHeader);
// Check if NB P-states were disabled, and if so, prevent any changes from occurring.
if (((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->SwNbPstateLoDis == 0) {
// 5. If MSRC001_0070[NbPstate] = 1, go to step 11
LibAmdMsrRead (MSR_COFVID_CTL, &LocalMsrRegister, StdHeader);
if (((COFVID_CTRL_MSR *) &LocalMsrRegister)->NbPstate == 0) {
// 6. Write 1 to D18F5x170[NbPstateGnbSlowDis].
PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateGnbSlowDis = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
// 7. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
// 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
TransitionToNbLow (PciAddress, StdHeader);
// 9. Set D18F5x170[SwNbPstateLoDis] = 1.
// 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
// Go to step 15.
TransitionToNbHigh (PciAddress, StdHeader);
} else {
// 11. Set D18F5x170[SwNbPstateLoDis] = 1.
// 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
TransitionToNbHigh (PciAddress, StdHeader);
// 13. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
// 14. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
TransitionToNbLow (PciAddress, StdHeader);
}
// 15. Set D18F5x170[SwNbPstateLoDis]=Temp1, D18F5x170[NbPstateDisOnP0]=Temp2, D18F5x170[NbP-
// stateThreshold]=Temp3, and D18F5x170[NbPstateGnbSlowDis]=Temp4.
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->SwNbPstateLoDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->SwNbPstateLoDis;
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateDisOnP0 = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateDisOnP0;
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateThreshold = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateThreshold;
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateGnbSlowDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateGnbSlowDis;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
}
}
/**
* Family 15h Trinity core 0 entry point for performing the necessary Nb P-state VID adjustment
* after a cold reset has occurred.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F15TnNbPstateVidAdjustAfterReset (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
BOOLEAN NeitherHiNorLo;
NB_PSTATE_REGISTER NbPsReg;
UINT32 NbPsVid;
UINT32 i;
NB_PSTATE_CTRL_REGISTER NbPsCtrl;
NB_PSTATE_CTRL_REGISTER NbPsCtrlSave;
NB_PSTATE_STS_REGISTER NbPsSts;
CLK_PWR_TIMING_CTRL_5_REGISTER ClkPwrTimgCtrl5;
D0F0xBC_x1F400_STRUCT D0F0xBC_x1F400;
// Check if D18F5x188[NbOffsetTrim] has been programmed to 01b (-25mV)
PciAddress.AddressValue = CPTC5_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimgCtrl5, StdHeader);
if (ClkPwrTimgCtrl5.NbOffsetTrim == 1) {
return;
}
// Add 25mV (-4 VID steps) to all VddNb VIDs.
PciAddress.AddressValue = NB_PSTATE_0_PCI_ADDR;
for (i = 0; i < NM_NB_PS_REG; i++) {
PciAddress.Address.Register = NB_PSTATE_0 + (i * 4);
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsReg, StdHeader);
if (NbPsReg.NbPstateEn == 1) {
NbPsVid = GetF15TnNbVid (&NbPsReg);
NbPsVid -= 4;
SetF15TnNbVid (&NbPsReg, &NbPsVid);
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsReg, StdHeader);
}
}
// Check if D18F5x174[CurNbPstate] equals NbPstateHi or NbPstateLo
PciAddress.Address.Register = NB_PSTATE_STATUS;
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsSts, StdHeader);
PciAddress.Address.Register = NB_PSTATE_CTRL;
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
// Save NB P-state control setting
NbPsCtrlSave = NbPsCtrl;
// Force a NB P-state Transition.
NeitherHiNorLo = FALSE;
if (NbPsSts.CurNbPstate == NbPsCtrl.NbPstateHi) {
TransitionToNbLow (PciAddress, StdHeader);
} else if (NbPsSts.CurNbPstate == NbPsCtrl.NbPstateLo) {
TransitionToNbHigh (PciAddress, StdHeader);
} else {
NeitherHiNorLo = TRUE;
}
// Set OffsetTrim to -25mV:
// D18F5x188[NbOffsetTrim]=01b (-25mV)
// D0F0xBC_x1F400[SviLoadLineOffsetVddNB]=01b (-25mV)
PciAddress.Address.Register = CPTC5_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimgCtrl5, StdHeader);
ClkPwrTimgCtrl5.NbOffsetTrim = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimgCtrl5, StdHeader);
GnbRegisterReadTN (D0F0xBC_x1F400_TYPE, D0F0xBC_x1F400_ADDRESS, &D0F0xBC_x1F400, 0, StdHeader);
D0F0xBC_x1F400.Field.SviLoadLineOffsetVddNB = 1;
GnbRegisterWriteTN (D0F0xBC_x1F400_TYPE, D0F0xBC_x1F400_ADDRESS, &D0F0xBC_x1F400, 0, StdHeader);
// Unforce NB P-state back to CurNbPstate value upon entry.
if (NeitherHiNorLo || (NbPsSts.CurNbPstate == NbPsCtrl.NbPstateHi)) {
TransitionToNbHigh (PciAddress, StdHeader);
} else {
// if (NbPsSts.CurNbPstate == NbPsCtrl.NbPstateLo)
TransitionToNbLow (PciAddress, StdHeader);
}
// Restore NB P-state control setting
PciAddress.Address.Register = NB_PSTATE_CTRL;
NbPsCtrl = NbPsCtrlSave;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
}
