int eth_init(bd_t *bis)
{
ETH *eth = &m_eth;
/* store our MAC address */
eth->m_mac = bis->bi_enetaddr;
/* setup DBMA and MAC */
PUT_REG( REG_BDMARXCON, ETH_BRxRS); /* reset BDMA RX machine */
PUT_REG( REG_BDMATXCON, ETH_BTxRS); /* reset BDMA TX machine */
PUT_REG( REG_MACCON , ETH_SwReset); /* reset MAC machine */
PUT_REG( REG_BDMARXLSZ, sizeof(MACFrame));
PUT_REG( REG_MACCON , 0); /* reset MAC machine */
/* init frame descriptors */
TxFDinit( eth);
RxFDinit( eth);
/* init the CAM with our MAC address */
PUT_REG( REG_CAM_BASE, (eth->m_mac[0] << 24) |
(eth->m_mac[1] << 16) |
(eth->m_mac[2] << 8) |
(eth->m_mac[3]));
PUT_REG( REG_CAM_BASE + 0x4, (eth->m_mac[4] << 24) |
(eth->m_mac[5] << 16));
/* enable CAM address 1 -- the MAC we just loaded */
PUT_REG( REG_CAMEN, 0x1);
PUT_REG( REG_CAMCON,
ETH_BroadAcc | /* accept broadcast packetes */
ETH_CompEn); /* enable compare mode (check against the CAM) */
/* configure the BDMA Transmitter control */
PUT_REG( REG_BDMATXCON,
ETH_BTxBRST | /* BDMA Tx burst size 16 words */
ETH_BTxMSL110 | /* BDMA Tx wait to fill 6/8 of the BDMA */
ETH_BTxSTSKO | /* BDMA Tx interrupt(Stop) on non-owner TX FD */
ETH_BTxEn); /* BDMA Tx Enable */
/* configure the MAC Transmitter control */
PUT_REG( REG_MACTXCON,
ETH_EnComp | /* interrupt when the MAC transmits or discards packet */
ETH_TxEn); /* MAC transmit enable */
/* configure the BDMA Receiver control */
PUT_REG( REG_BDMARXCON,
ETH_BRxBRST | /* BDMA Rx Burst Size 16 words */
ETH_BRxSTSKO | /* BDMA Rx interrupt(Stop) on non-owner RX FD */
ETH_BRxMAINC | /* BDMA Rx Memory Address increment */
ETH_BRxDIE | /* BDMA Rx Every Received Frame Interrupt Enable */
ETH_BRxNLIE | /* BDMA Rx NULL List Interrupt Enable */
ETH_BRxNOIE | /* BDMA Rx Not Owner Interrupt Enable */
ETH_BRxLittle | /* BDMA Rx Little endian */
ETH_BRxEn); /* BDMA Rx Enable */
/* configure the MAC Receiver control */
PUT_REG( REG_MACRXCON,
ETH_RxEn); /* MAC ETH_RxEn */
return 0;
}
static int __s3c4510b_open(struct net_device *dev)
{
unsigned long status;
/* Disable interrupts */
INT_DISABLE(INT_BDMARX);
INT_DISABLE(INT_MACTX);
/**
** install RX ISR
**/
__rx_irqaction.dev_id = (void *)dev;
status = setup_irq( INT_BDMARX, &__rx_irqaction);
if ( unlikely(status)) {
printk( KERN_ERR "Unabled to hook irq %d for ethernet RX\n", INT_BDMARX);
return status;
}
/**
** install TX ISR
**/
__tx_irqaction.dev_id = (void *)dev;
status = setup_irq( INT_MACTX, &__tx_irqaction);
if ( unlikely(status)) {
printk( KERN_ERR "Unabled to hook irq %d for ethernet TX\n", INT_MACTX);
return status;
}
/* setup DBMA and MAC */
outl( ETH_BRxRS, REG_BDMARXCON); /* reset BDMA RX machine */
outl( ETH_BTxRS, REG_BDMATXCON); /* reset BDMA TX machine */
outl( ETH_SwReset, REG_MACCON); /* reset MAC machine */
outl( sizeof( ETHFrame), REG_BDMARXLSZ);
outl( ETH_FullDup, REG_MACCON); /* enable full duplex */
/* init frame descriptors */
TxFDinit( dev);
RxFDinit( dev);
outl( (dev->dev_addr[0] << 24) |
(dev->dev_addr[1] << 16) |
(dev->dev_addr[2] << 8) |
(dev->dev_addr[3]) , REG_CAM_BASE);
outl( (dev->dev_addr[4] << 24) |
(dev->dev_addr[5] << 16) , REG_CAM_BASE + 4);
outl( 0x0001, REG_CAMEN);
outl( ETH_CompEn | /* enable compare mode (check against the CAM) */
ETH_BroadAcc, /* accept broadcast packetes */
REG_CAMCON);
INT_ENABLE(INT_BDMARX);
INT_ENABLE(INT_MACTX);
/* enable RX machinery */
outl( ETH_BRxBRST | /* BDMA Rx Burst Size 16 words */
ETH_BRxSTSKO | /* BDMA Rx interrupt(Stop) on non-owner RX FD */
ETH_BRxMAINC | /* BDMA Rx Memory Address increment */
ETH_BRxDIE | /* BDMA Rx Every Received Frame Interrupt Enable */
ETH_BRxNLIE | /* BDMA Rx NULL List Interrupt Enable */
ETH_BRxNOIE | /* BDMA Rx Not Owner Interrupt Enable */
ETH_BRxLittle | /* BDMA Rx Little endian */
ETH_BRxWA10 | /* BDMA Rx Word Alignment- two invalid bytes */
ETH_BRxEn, /* BDMA Rx Enable */
REG_BDMARXCON);
outl( ETH_RxEn | /* enable MAC RX */
ETH_StripCRC | /* check and strip CRC */
ETH_EnCRCErr | /* interrupt on CRC error */
ETH_EnOver | /* interrupt on overflow error */
ETH_EnLongErr | /* interrupt on long frame error */
ETH_EnRxPar, /* interrupt on MAC FIFO parity error */
REG_MACRXCON);
netif_start_queue(dev);
return 0;
}