PHY_INT32 phy_change_pipe_phase_c60802(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase){
PHY_INT32 drv_reg_value;
PHY_INT32 phase_reg_value;
PHY_INT32 temp;
drv_reg_value = phy_drv << PHY_DRV_SHIFT;
phase_reg_value = (pipe_phase << PHY_PHASE_SHIFT) | (phy_drv << PHY_PHASE_DRV_SHIFT);
temp = U3PhyReadReg8(((PHY_UINT32)&info->sifslv_chip_regs_c->gpio_ctla)+2);
temp &= ~(0x3 << PHY_DRV_SHIFT);
temp |= drv_reg_value;
U3PhyWriteReg8(((PHY_UINT32)&info->sifslv_chip_regs_c->gpio_ctla)+2, temp);
temp = U3PhyReadReg8(((PHY_UINT32)&info->sifslv_chip_regs_c->gpio_ctla)+3);
temp &= ~((0x3 << PHY_PHASE_DRV_SHIFT) | (0x1f << PHY_PHASE_SHIFT));
temp |= phase_reg_value;
U3PhyWriteReg8(((PHY_UINT32)&info->sifslv_chip_regs_c->gpio_ctla)+3, temp);
return PHY_TRUE;
}
PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
PHY_INT8 cur_value;
PHY_INT8 new_value;
cur_value = U3PhyReadReg8(addr);
new_value = (cur_value & (~mask)) | (value << offset);
//udelay(i2cdelayus);
U3PhyWriteReg8(addr, new_value);
return PHY_TRUE;
}
PHY_INT32 phy_init_c60802(struct u3phy_info *info)
{
PHY_UINT8 temp;
//****** u2phy part *******//
//RG_USB20_BGR_EN = 1
U3PhyWriteField32((PHY_UINT32)(&info->u2phy_regs_c->u2phyac0)
, C60802_RG_SIFSLV_BGR_EN_OFST, C60802_RG_SIFSLV_BGR_EN, 1);
//RG_USB20_REF_EN = 1
U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs_c->u2phyac0)
, C60802_RG_USB20_REF_EN_OFST, C60802_RG_USB20_REF_EN, 1);
//RG_USB20_SW_PLLMODE = 2
U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs_c->u2phydcr1)
, C60802_RG_USB20_SW_PLLMODE_OFST, C60802_RG_USB20_SW_PLLMODE, 0x2);
//****** u3phyd part *******//
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs_c->phyd_lfps0)
, C60802_RG_SSUSB_RXLFPS_UPB_OFST, C60802_RG_SSUSB_RXLFPS_UPB, 0x19);
//turn off phy clock gating, marked in normal case
//U3PhyWriteReg8(&info->u3phyd_regs_c->phyd_mix1+2,0x0);
//mdelay(100);
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs_c->phyd_lfps0)
, C60802_RG_SSUSB_LOCK5G_BLOCK_OFST, C60802_RG_SSUSB_LOCK5G_BLOCK, 0x1);
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs_c->phyd_pll_0)
, C60802_RG_SSUSB_PLLBAND_RECAL_OFST, C60802_RG_SSUSB_PLLBAND_RECAL, 1);
//****** u3phyd bank2 part *******//
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs_c->b2_phyd_top1)
, C60802_RG_SSUSB_FORCE_TX_EIDLE_LP_EN_OFST, C60802_RG_SSUSB_FORCE_TX_EIDLE_LP_EN, 1);
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs_c->b2_phyd_top1)
, C60802_RG_SSUSB_TX_EIDLE_LP_EN_OFST, C60802_RG_SSUSB_TX_EIDLE_LP_EN, 0);
//****** u3phya part *******//
//reserved reg, only ACD know what it is
temp = U3PhyReadReg8(((PHY_UINT32)&info->u3phya_regs_c->reg7)+1);
temp &= (~0x40);
U3PhyWriteReg8(((PHY_UINT32)&info->u3phya_regs_c->reg7)+1, temp);
//****** u3phya_da part *******//
// set SSC to pass electrical compliance SSC min
U3PhyWriteField32(((PHY_UINT32)&info->u3phya_da_regs_c->reg21)
, C60802_reg21_FLD_RG_SSUSB_PLL_SSC_DELTA_U3_OFST, C60802_reg21_FLD_RG_SSUSB_PLL_SSC_DELTA_U3
, 0x47);
//****** u3phy chip part *******//
#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
U3PhyWriteField32(((PHY_UINT32)&info->sifslv_chip_regs_c->syspll1)
, (24), (0x1<<24), 0x1);
#endif
//phase set
U3PhyWriteReg8(((PHY_UINT32)&info->sifslv_chip_regs_c->gpio_ctla)+2, 0x10);
//U3PhyWriteReg8(((PHY_UINT32)&info->sifslv_chip_regs_c->gpio_ctla)+3, 0x74);
U3PhyWriteReg8(((PHY_UINT32)&info->sifslv_chip_regs_c->gpio_ctla)+3, 0x8c);
#ifdef SUPPORT_OTG
U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs_c->u2phydtm1)
, C60802_FORCE_IDPULLUP_OFST, C60802_FORCE_IDPULLUP, 1);
U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs_c->u2phydtm1)
, C60802_RG_IDPULLUP_OFST, C60802_RG_IDPULLUP, 1);
//U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs_c->u2phyacr2)
// ,C60802_RG_USB20_OTG_VBUSCMP_EN_OFST,C60802_RG_USB20_OTG_VBUSCMP_EN, 0x1);
#endif
return PHY_TRUE;
}
PHY_INT32 phy_init_d60802(struct u3phy_info *info)
{
/**********u2phy part******************/
//manual set U2 slew rate ctrl = 4
U3PhyWriteField32(((phys_addr_t)&info->u2phy_regs_d->usbphyacr5)
,D60802_RG_USB20_HSTX_SRCTRL_OFST,D60802_RG_USB20_HSTX_SRCTRL, 0x4);
//fine tune SQTH to gain margin in U2 Rx sensitivity compliance test
U3PhyWriteField32(((phys_addr_t)&info->u2phy_regs_d->usbphyacr6)
,D60802_RG_USB20_SQTH_OFST,D60802_RG_USB20_SQTH,0x4);
phy_hsrx_set();
//disable VBUS CMP to save power since no OTG function
U3PhyWriteField32(((phys_addr_t)&info->u2phy_regs_d->usbphyacr6)
,D60802_RG_USB20_OTG_VBUSCMP_EN_OFST,D60802_RG_USB20_OTG_VBUSCMP_EN, 0x1);
/*********phyd part********************/
//shorten Tx drive stable delay time from 82us -> 25us
U3PhyWriteField32(((phys_addr_t)&info->u3phyd_regs_d->phyd_mix1)
,D60802_RG_SSUSB_TX_DRV_DLY_OFST,D60802_RG_SSUSB_TX_DRV_DLY, 0x13);
//The same Rx LFPS detect period rxlfps_upb as A ver
U3PhyWriteField32(((phys_addr_t)&info->u3phyd_regs_d->phyd_lfps0)
,D60802_RG_SSUSB_RXLFPS_UPB_OFST,D60802_RG_SSUSB_RXLFPS_UPB, 0x19);
//No switch to Lock 5g @tx_lfps enable
U3PhyWriteField32(((phys_addr_t)&info->u3phyd_regs_d->phyd_lfps0)
,D60802_RG_SSUSB_LOCK5G_BLOCK_OFST,D60802_RG_SSUSB_LOCK5G_BLOCK, 0x1);
//disable DFE to improve Rx JT
U3PhyWriteField32(((phys_addr_t)&info->u3phyd_regs_d->phyd_rx0)
,D60802_RG_SSUSB_RX_DFE_RST_OFST,D60802_RG_SSUSB_RX_DFE_RST, 0);
//calibrate CDR offset every time enter TSEQ
U3PhyWriteField32(((phys_addr_t)&info->u3phyd_regs_d->phyd_mix2)
,D60802_RG_SSUSB_CDROS_EN_OFST,D60802_RG_SSUSB_CDROS_EN, 0x1);
//Re-Calibration after exit P3 state
U3PhyWriteField32(((phys_addr_t)&info->u3phyd_regs_d->phyd_pll_0)
, D60802_RG_SSUSB_PLLBAND_RECAL_OFST, D60802_RG_SSUSB_PLLBAND_RECAL, 0x1);
/**************phyd bank2 part************/
//Disable E-Idle Low power mode
U3PhyWriteField32(((phys_addr_t)&info->u3phyd_bank2_regs_d->b2_phyd_top1)
,D60802_RG_SSUSB_FORCE_TX_EIDLE_LP_EN_OFST ,D60802_RG_SSUSB_FORCE_TX_EIDLE_LP_EN, 0x1);
U3PhyWriteField32(((phys_addr_t)&info->u3phyd_bank2_regs_d->b2_phyd_top1)
,D60802_RG_SSUSB_TX_EIDLE_LP_EN_OFST,D60802_RG_SSUSB_TX_EIDLE_LP_EN, 0);
/**************phya part******************/
//modify Tx det Rx Vth to work around the threshold back to 200mV
U3PhyWriteField32(((phys_addr_t)&info->u3phya_regs_d->reg5)
,D60802_reg5_FLD_RG_SSUSB_RXDET_VTHSEL_L_OFST,D60802_reg5_FLD_RG_SSUSB_RXDET_VTHSEL_L,0x2);
//modify Tx det Rx Vth to work around the threshold back to 200mV
U3PhyWriteField32(((phys_addr_t)&info->u3phya_regs_d->reg5)
,D60802_reg5_FLD_RG_SSUSB_RXDET_VTHSEL_H_OFST,D60802_reg5_FLD_RG_SSUSB_RXDET_VTHSEL_H,0x2);
/*************phya da part*****************/
//set to pass SSC min in electrical compliance
U3PhyWriteField32(((phys_addr_t)&info->u3phya_da_regs_d->reg21)
,D60802_reg21_FLD_RG_SSUSB_PLL_SSC_DELTA_U3_OFST,D60802_reg21_FLD_RG_SSUSB_PLL_SSC_DELTA_U3,0x47);
//set R step 1 = 2 to improve Rx JT
U3PhyWriteField32(((phys_addr_t)&info->u3phya_da_regs_d->reg32)
,D60802_reg32_FLD_RG_SSUSB_EQ_RSTEP1_U3_OFST,D60802_reg32_FLD_RG_SSUSB_EQ_RSTEP1_U3, 0x2);
/*************phy chip part******************/
//Power down bias at P3, p3 bias _pwd
#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
U3PhyWriteField32(((phys_addr_t)&info->sifslv_chip_regs_d->syspll1)
, (24), (0x1<<24), 0x1);
#endif
// PIPE drv = 2
U3PhyWriteReg8(((phys_addr_t)&info->sifslv_chip_regs_d->gpio_ctla+2), 0x10);
// PIPE phase
//U3PhyWriteReg8(((PHY_UINT32)&info->sifslv_chip_regs_d->gpio_ctla+3), 0x44);
U3PhyWriteReg8(((phys_addr_t)&info->sifslv_chip_regs_d->gpio_ctla+3), 0xd4);
return PHY_TRUE;
}
