/* ===================================================================*/ LDD_TDeviceData* UART_Init(LDD_TUserData *UserDataPtr) { /* Allocate device structure */ UART_TDeviceDataPtr DeviceDataPrv; /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; /* Clear the receive counters and pointer */ DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */ DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */ DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */ /* Clear the transmit counters and pointer */ DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */ DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */ DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */ DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ /* Allocate interrupt vectors */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_UART0__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv; /* SIM_SCGC4: UART0=1 */ SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; /* PORTA_PCR1: ISF=0,MUX=2 */ PORTA_PCR1 = (uint32_t)((PORTA_PCR1 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x05) )) | (uint32_t)( PORT_PCR_MUX(0x02) )); /* PORTA_PCR2: ISF=0,MUX=2 */ PORTA_PCR2 = (uint32_t)((PORTA_PCR2 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x05) )) | (uint32_t)( PORT_PCR_MUX(0x02) )); /* NVIC_IPR3: PRI_12=0x80 */ NVIC_IPR3 = (uint32_t)((NVIC_IPR3 & (uint32_t)~(uint32_t)( NVIC_IP_PRI_12(0x7F) )) | (uint32_t)( NVIC_IP_PRI_12(0x80) )); /* NVIC_ISER: SETENA|=0x1000 */ NVIC_ISER |= NVIC_ISER_SETENA(0x1000); UART0_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */ UART0_PDD_EnableReceiver(UART0_BASE_PTR, PDD_DISABLE); /* Disable receiver. */ DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */ /* UART0_C1: LOOPS=0,DOZEEN=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */ UART0_C1 = 0x00U; /* Set the C1 register */ /* UART0_C3: R8T9=0,R9T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */ UART0_C3 = 0x00U; /* Set the C3 register */ /* UART0_C4: MAEN1=0,MAEN2=0,M10=0,OSR=0 */ UART0_C4 = UART0_C4_OSR(0x00); /* Set the C4 register */ /* UART0_S2: LBKDIF=0,RXEDGIF=0,MSBF=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */ UART0_S2 = 0x00U; /* Set the S2 register */ UART_SetClockConfiguration(DeviceDataPrv, Cpu_GetClockConfiguration()); /* Initial speed CPU mode is high */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_UART_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); }
/* ===================================================================*/ LDD_TDeviceData* IO1_Init(LDD_TUserData *UserDataPtr) { /* Allocate device structure */ IO1_TDeviceDataPtr DeviceDataPrv; /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; /* Clear the receive counters and pointer */ DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */ DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */ DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */ /* Clear the transmit counters and pointer */ DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */ DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */ DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */ DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ /* SIM_SCGC4: UART0=1 */ SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; /* PORTA_PCR1: ISF=0,MUX=2 */ PORTA_PCR1 = (uint32_t)((PORTA_PCR1 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x05) )) | (uint32_t)( PORT_PCR_MUX(0x02) )); /* PORTA_PCR2: ISF=0,MUX=2 */ PORTA_PCR2 = (uint32_t)((PORTA_PCR2 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x05) )) | (uint32_t)( PORT_PCR_MUX(0x02) )); UART0_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */ UART0_PDD_EnableReceiver(UART0_BASE_PTR, PDD_DISABLE); /* Disable receiver. */ DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */ DeviceDataPrv->EventMask = 0x00u; /* Initialization of the event mask variable */ DeviceDataPrv->EnUser = TRUE; /* Enable device */ /* UART0_C1: LOOPS=0,DOZEEN=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */ UART0_C1 = 0x00U; /* Set the C1 register */ /* UART0_C3: R8T9=0,R9T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */ UART0_C3 = 0x00U; /* Set the C3 register */ /* UART0_C4: MAEN1=0,MAEN2=0,M10=0,OSR=0 */ UART0_C4 = UART0_C4_OSR(0x00); /* Set the C4 register */ /* UART0_S2: LBKDIF=0,RXEDGIF=0,MSBF=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */ UART0_S2 = 0x00U; /* Set the S2 register */ UART0_PDD_SetClockSource(UART0_BASE_PTR, UART0_PDD_PLL_FLL_CLOCK); UART0_PDD_SetBaudRate(UART0_BASE_PTR, 52U); /* Set the baud rate register. */ UART0_PDD_SetOversamplingRatio(UART0_BASE_PTR, 3U); UART0_PDD_EnableSamplingOnBothEdges(UART0_BASE_PTR, PDD_ENABLE); UART0_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_ENABLE); /* Enable transmitter */ UART0_PDD_EnableReceiver(UART0_BASE_PTR, PDD_ENABLE); /* Enable receiver */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_IO1_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); }
void uart_init(void) { /* Supply the clock for UART0 and PORTA */ SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Set PORTA1 as Rx and PORTA2 as Tx */ PORTA->PCR[1] &= ~PORT_PCR_MUX_MASK; // Make sure that MUX is clear PORTA->PCR[1] |= PORT_PCR_MUX(2); PORTA->PCR[2] &= ~PORT_PCR_MUX_MASK; // Make sure that MUX is clear PORTA->PCR[2] |= PORT_PCR_MUX(2); /* Choose external 8MHz crystal as a reference clock for UART0 */ /* Asynch Module Clock = 8 MHz */ SIM->SOPT2 |= SIM_SOPT2_UART0SRC(2); /* Disable the reciever and transmitter of UART0 */ UART0->C2 &= ~(UART0_C2_TE_MASK | UART0_C2_RE_MASK); // turn off the Tx and Rx /* Set the oversampling ratio to 4 */ UART0->C4 = UART0_C4_OSR(3); /* Set SBr to 139 in order to achieve Baud Rate euqal to 14400 */ UART0->BDH |= UART0_BDH_SBR(0); UART0->BDL &= ~UART0_BDL_SBR_MASK; // clear BDL first UART0->BDL |= UART0_BDL_SBR(139); /* Set 1 Stop Bit */ UART0->BDH &= ~UART0_BDH_SBNS_MASK; /* Choose 8-bits long data */ UART0->C1 &= ~UART0_C1_M_MASK; /* Disable hardware parity check */ UART0->C1 &= ~UART0_C1_PE_MASK; /* Initialize the queues for the interrupts-driven serial communication */ q_init(&TxQ); q_init(&RxQ); /* Configure the interrupts from the UART0 */ NVIC_ClearPendingIRQ(UART0_IRQn); NVIC_EnableIRQ(UART0_IRQn); /* Enable the interrupt when receiver buffer gets full */ UART0->C2 |= UART0_C2_RIE_MASK; /* Turn on the receiver and transmitter */ UART0->C2 |= UART0_C2_TE_MASK | UART0_C2_RE_MASK; // turn on the Tx and Rx }
/* * Initialize the uart for 8N1 operation, interrupts disabled, and * no hardware flow-control * * NOTE: Since the uarts are pinned out in multiple locations on most * Kinetis devices, this driver does not enable uart pin functions. * The desired pins should be enabled before calling this init function. * * Parameters: * uart0clk uart module Clock in Hz(used to calculate baud) * baud uart baud rate */ status_t uart0_init (uint32_t uart0clk, uint32_t baud, uart0_data_sink_func_t function) { // Calculate SBR rounded to nearest whole number, 14.4 = 14, 14.6 = 15 // This gives the least error possible uint32_t sbr = (uint32_t)(((uart0clk * 10)/(baud * kUART0_OSR_Value)) + 5) / 10; uint32_t calculatedBaud = (uint32_t)(uart0clk/(sbr * kUART0_OSR_Value)); uint32_t baudDiff = MAX(calculatedBaud, baud) - MIN(calculatedBaud, baud); if (baudDiff < ((baud / 100) * 3)) { s_uart0_data_sink_callback = function; // Enable clocking to UART0 SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; // Disable UART0 before changing registers UART0->C2 &= ~(UART0_C2_TE_MASK | UART0_C2_RE_MASK); // Enable both edge since we are using a OSR value between 3 and 8 UART0->C5 |= UART0_C5_BOTHEDGE_MASK; // Setup OSR value uint32_t temp = UART0->C4; temp &= ~UART0_C4_OSR_MASK; temp |= UART0_C4_OSR(kUART0_OSR_Value - 1); // BaudRate = UARTClk / ((OSR + 1) * SBR) // Write temp to C4 register UART0->C4 = temp; // Save off the current value of the uartx_BDH except for the SBR field temp = UART0->BDH & ~(UART0_BDH_SBR(0x1F)); UART0->BDH = temp | UART0_BDH_SBR(((sbr & 0x1F00) >> 8)); UART0->BDL = (uint8_t)(sbr & UART0_BDL_SBR_MASK); // Enable receive interrupts UART0->C2 |= UART0_C2_RIE_MASK; NVIC_EnableIRQ(UART0_IRQn); // Enable receiver and transmitter UART0->C2 |= (UART0_C2_TE_MASK | UART0_C2_RE_MASK ); return kStatus_Success; }
void DrvUART0_Config(void) { uint32_t divisor; // enable clock SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_SHIFT ; SIM->SOPT2 |= SIM_SOPT2_UART0SRC(0x01); PORTA->PCR[1] = PORT_PCR_MUX(0x2); PORTA->PCR[2] = PORT_PCR_MUX(0x2); SIM->SCGC4 |= 1UL<<10; //disabled tx and rx before configuration UART0->C2 &= ~UART0_C2_TE_MASK ; UART0->C2 &= ~UART0_C2_RE_MASK ; // Data bit: 8; Parity: None; Stop bits: 1; Flow Control: None UART0->C1 = 00U; UART0->C3 = 00U; UART0->C4 = UART0_C4_OSR(15); UART0->S2 = 00U; UART0->S1 = 00U; // Set baud rate 115200 divisor = 23; UART0->BDH = UART0_BDH_SBR(divisor>>8); UART0->BDL = (uint8_t)(divisor); // Tx & Rx are enable UART0->C2 |= UART0_C2_TE_MASK ; UART0->C2 |= UART0_C2_RE_MASK ; UART0->C2 |= UART0_C2_RIE_MASK ; NVIC_EnableIRQ(UART0_IRQn); NVIC_ClearPendingIRQ(UART0_IRQn); }
PUBLIC_FCT void UART0_Init (T_ULONG bd_value) { const T_ULONG cul_mcg_clk_hz = 24000000; //PLL/2 Source Clock for UART T_ULONG lul_baud_rate = 0; //Variable to store baud rate T_ULONG lul_br_value = 0; //Variable to store BD dividers float lf_br_float = 0; //Auxiliary variable to save the result of division float lf_residue = 0; //Variable to store the minimum residue T_UBYTE lub_temp = 4; //Auxiliary Variable T_UWORD luw_osr_value = 4; //Variable to store OSR dividers register T_UBYTE lub_i = 0; //Auxiliary Variable PORTA_PCR1 = PORT_PCR_MUX(2); //Enable the UART_TXD function on PTA1 PORTA_PCR2 = PORT_PCR_MUX(2); //Enable the UART_TXD function on PTA2 SIM_SOPT2 |= SIM_SOPT2_UART0SRC(1); //Select the PLLFLLCLK as UART0 clock source SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; //Enable Clock signal for UART0 UART0_Stop(); //Disable UART0 before changing registers lul_baud_rate = bd_value; //Store Baud rate desired /* * Calculate BR registers depends on Baud Rate = Baud Clock / (BR * (OSR + 1)) according to datasheet */ lul_br_value = cul_mcg_clk_hz / (lul_baud_rate * (luw_osr_value + 1)); lf_br_float = (float)cul_mcg_clk_hz / ((float)lul_baud_rate * ((float)luw_osr_value + 1)); lf_residue = lf_br_float - (float)lul_br_value; /* * Calculate it for all OSR possible values to find the minimum error */ for(lub_i = 5; lub_i <= 32; lub_i++) { lul_br_value = cul_mcg_clk_hz / (lul_baud_rate * (lub_i + 1)); lf_br_float = (float)cul_mcg_clk_hz / ((float)lul_baud_rate * ((float)lub_i + 1)); lf_br_float -= (float)lul_br_value; if(lf_br_float <= lf_residue) //If a new "minimum error" is found { lf_residue = lf_br_float; //Store new minimum error lub_temp = lub_i; //Store OSR value for this minimum error } } luw_osr_value = lub_temp; //Assign the found OSR value to calculate the minimum error lul_br_value = cul_mcg_clk_hz / (lul_baud_rate * (luw_osr_value + 1)); //Calculate BR value UART0_BDH |= UART0_BDH_SBR(((lul_br_value & 0x1F00) >> 8)); //Setting BD dividers UART0_BDL = (T_UBYTE)(lul_br_value & UART0_BDL_SBR_MASK); //Setting BD dividers UART0_C4 = UART0_C4_OSR(luw_osr_value); //Setting OSR for Sampling Ratio if(luw_osr_value < 8) //If Sampling Ratio is less than 8 { UART0_C5|= UART0_C5_BOTHEDGE_MASK; //Enable both edges of baud clock for receiving data } else { } UART0_C1 &=~(UART0_C1_M_MASK | UART0_C1_PE_MASK); //8 Bit for data, No parity Selected UART0_BDH &= ~(UART0_BDH_SBNS_MASK); //Configure One Stop Bit: 0 One stop bit. UART0_Start(); //Enable receiver and transmitter }
/* ===================================================================*/ LDD_TDeviceData* ASerialLdd1_Init(LDD_TUserData *UserDataPtr) { /* Allocate device structure */ ASerialLdd1_TDeviceDataPtr DeviceDataPrv; /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; /* Clear the receive counters and pointer */ DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */ DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */ DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */ /* Clear the transmit counters and pointer */ DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */ DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */ DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */ DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ /* Allocate interrupt vectors */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_UART0__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv; /* SIM_SCGC4: UART0=1 */ SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; /* PORTA_PCR1: ISF=0,MUX=2 */ PORTA_PCR1 = (uint32_t)((PORTA_PCR1 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x05) )) | (uint32_t)( PORT_PCR_MUX(0x02) )); /* PORTA_PCR2: ISF=0,MUX=2 */ PORTA_PCR2 = (uint32_t)((PORTA_PCR2 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x05) )) | (uint32_t)( PORT_PCR_MUX(0x02) )); /* NVIC_IPR3: PRI_12=0 */ NVIC_IPR3 &= (uint32_t)~(uint32_t)(NVIC_IP_PRI_12(0xFF)); /* NVIC_ISER: SETENA|=0x1000 */ NVIC_ISER |= NVIC_ISER_SETENA(0x1000); UART0_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */ UART0_PDD_EnableReceiver(UART0_BASE_PTR, PDD_DISABLE); /* Disable receiver. */ DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */ DeviceDataPrv->ErrFlag = 0x00U; /* Reset error flags */ DeviceDataPrv->EnUser = FALSE; /* Disable device */ /* UART0_C1: LOOPS=0,DOZEEN=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */ UART0_C1 = 0x00U; /* Set the C1 register */ /* UART0_C3: R8T9=0,R9T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */ UART0_C3 = 0x00U; /* Set the C3 register */ /* UART0_C4: MAEN1=0,MAEN2=0,M10=0,OSR=0 */ UART0_C4 = UART0_C4_OSR(0x00); /* Set the C4 register */ /* UART0_S2: LBKDIF=0,RXEDGIF=0,MSBF=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */ UART0_S2 = 0x00U; /* Set the S2 register */ SIM_PDD_SetClockSourceUART0(SIM_BASE_PTR, SIM_PDD_UART0_PLL_FLL_CLOCK); UART0_PDD_SetBaudRate(UART0_BASE_PTR, 2U); /* Set the baud rate register. */ UART0_PDD_SetOversamplingRatio(UART0_BASE_PTR, 3U); UART0_PDD_EnableSamplingOnBothEdges(UART0_BASE_PTR, PDD_ENABLE); UART0_PDD_DisableInterrupt(UART0_BASE_PTR, ( UART0_PDD_INTERRUPT_RECEIVER | UART0_PDD_INTERRUPT_TRANSMITTER | UART0_PDD_INTERRUPT_PARITY_ERROR | UART0_PDD_INTERRUPT_FRAMING_ERROR | UART0_PDD_INTERRUPT_NOISE_ERROR | UART0_PDD_INTERRUPT_OVERRUN_ERROR )); /* Disable interrupts */ UART0_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */ UART0_PDD_EnableReceiver(UART0_BASE_PTR, PDD_DISABLE); /* Disable receiver. */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_ASerialLdd1_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); }