PUBLIC_FCT void UART0_Init (T_ULONG bd_value)
{
const T_ULONG cul_mcg_clk_hz = 24000000; //PLL/2 Source Clock for UART
T_ULONG lul_baud_rate = 0; //Variable to store baud rate
T_ULONG lul_br_value = 0; //Variable to store BD dividers
float lf_br_float = 0; //Auxiliary variable to save the result of division
float lf_residue = 0; //Variable to store the minimum residue
T_UBYTE lub_temp = 4; //Auxiliary Variable
T_UWORD luw_osr_value = 4; //Variable to store OSR dividers
register T_UBYTE lub_i = 0; //Auxiliary Variable
PORTA_PCR1 = PORT_PCR_MUX(2); //Enable the UART_TXD function on PTA1
PORTA_PCR2 = PORT_PCR_MUX(2); //Enable the UART_TXD function on PTA2
SIM_SOPT2 |= SIM_SOPT2_UART0SRC(1); //Select the PLLFLLCLK as UART0 clock source
SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; //Enable Clock signal for UART0
UART0_Stop(); //Disable UART0 before changing registers
lul_baud_rate = bd_value; //Store Baud rate desired
/*
* Calculate BR registers depends on Baud Rate = Baud Clock / (BR * (OSR + 1)) according to datasheet
*/
lul_br_value = cul_mcg_clk_hz / (lul_baud_rate * (luw_osr_value + 1));
lf_br_float = (float)cul_mcg_clk_hz / ((float)lul_baud_rate * ((float)luw_osr_value + 1));
lf_residue = lf_br_float - (float)lul_br_value;
/*
* Calculate it for all OSR possible values to find the minimum error
*/
for(lub_i = 5; lub_i <= 32; lub_i++)
{
lul_br_value = cul_mcg_clk_hz / (lul_baud_rate * (lub_i + 1));
lf_br_float = (float)cul_mcg_clk_hz / ((float)lul_baud_rate * ((float)lub_i + 1));
lf_br_float -= (float)lul_br_value;
if(lf_br_float <= lf_residue) //If a new "minimum error" is found
{
lf_residue = lf_br_float; //Store new minimum error
lub_temp = lub_i; //Store OSR value for this minimum error
}
}
luw_osr_value = lub_temp; //Assign the found OSR value to calculate the minimum error
lul_br_value = cul_mcg_clk_hz / (lul_baud_rate * (luw_osr_value + 1)); //Calculate BR value
UART0_BDH |= UART0_BDH_SBR(((lul_br_value & 0x1F00) >> 8)); //Setting BD dividers
UART0_BDL = (T_UBYTE)(lul_br_value & UART0_BDL_SBR_MASK); //Setting BD dividers
UART0_C4 = UART0_C4_OSR(luw_osr_value); //Setting OSR for Sampling Ratio
if(luw_osr_value < 8) //If Sampling Ratio is less than 8
{
UART0_C5|= UART0_C5_BOTHEDGE_MASK; //Enable both edges of baud clock for receiving data
}
else
{
}
UART0_C1 &=~(UART0_C1_M_MASK | UART0_C1_PE_MASK); //8 Bit for data, No parity Selected
UART0_BDH &= ~(UART0_BDH_SBNS_MASK); //Configure One Stop Bit: 0 One stop bit.
UART0_Start(); //Enable receiver and transmitter
}
/**********************************************************************
name :
function :
**********************************************************************/
void UARTClass::end( void )
{
UART0_Stop();
rx_buffer->rx_Head = rx_buffer->rx_Tail;
}
