/* ** This function initializes the UART instance for use. */ static void UARTInitialize(void) { /* Performing a module reset. */ UARTModuleReset(UART_INSTANCE_BASE_ADD); #ifdef UART_ENABLE_FIFO /* Performing FIFO configurations. */ UartFIFOConfigure(); #else /* Enabling DMA Mode 1. */ UARTDMAEnable(UART_INSTANCE_BASE_ADD, UART_DMA_MODE_1_ENABLE); #endif #if (defined UART_ENABLE_FIFO) && (defined DIRECT_TX_DMA_THRESH_MODE) /* Selecting the method of setting the Transmit DMA Threshold value. */ UARTTxDMAThresholdControl(UART_INSTANCE_BASE_ADD, UART_TX_DMA_THRESHOLD_REG); /* Configuring the Transmit DMA Threshold value. */ UARTTxDMAThresholdValConfig(UART_INSTANCE_BASE_ADD, TX_DMA_THRESHOLD); #endif /* Performing Baud Rate settings. */ UartBaudRateSet(); /* Switching to Configuration Mode B. */ UARTRegConfigModeEnable(UART_INSTANCE_BASE_ADD, UART_REG_CONFIG_MODE_B); /* Programming the Line Characteristics. */ UARTLineCharacConfig(UART_INSTANCE_BASE_ADD, (UART_FRAME_WORD_LENGTH_8 | UART_FRAME_NUM_STB_1), UART_PARITY_NONE); /* Disabling write access to Divisor Latches. */ UARTDivisorLatchDisable(UART_INSTANCE_BASE_ADD); /* Disabling Break Control. */ UARTBreakCtl(UART_INSTANCE_BASE_ADD, UART_BREAK_COND_DISABLE); /* Switching to UART16x operating mode. */ UARTOperatingModeSelect(UART_INSTANCE_BASE_ADD, UART16x_OPER_MODE); }
int main(void) { /* Configuring the system clocks for EDMA. */ EDMAModuleClkConfig(); /* Configuring the system clocks for UART0 instance. */ UART0ModuleClkConfig(); /* Performing Pin Multiplexing for UART0 instance. */ UARTPinMuxSetup(0); /* Enabling IRQ in CPSR of ARM processor. */ IntMasterIRQEnable(); /* Initializing the ARM Interrupt Controller. */ IntAINTCInit(); /* Initializing the EDMA. */ EDMA3Initialize(); /* Initializing the UART0 instance for use. */ UARTInitialize(); /* ** Configuring the EDMA. */ /* Request DMA Channel and TCC for UART Transmit*/ EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA, EDMA3_UART_TX_CHA_NUM, EDMA3_UART_TX_CHA_NUM, EVT_QUEUE_NUM); /* Registering Callback Function for TX*/ cb_Fxn[EDMA3_UART_TX_CHA_NUM] = &callback; /* Request DMA Channel and TCC for UART Receive */ EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA, EDMA3_UART_RX_CHA_NUM, EDMA3_UART_RX_CHA_NUM, EVT_QUEUE_NUM); /* Registering Callback Function for RX*/ cb_Fxn[EDMA3_UART_RX_CHA_NUM] = &callback; /******************** Transmission of a string **************************/ /* Configuring EDMA PaRAM sets to transmit 'welcome' message. */ UartEDMATxConfTransfer(EDMA3_UART_TX_CHA_NUM, EDMA3_UART_TX_CHA_NUM, welcome, sizeof(welcome) - 1); /* Wait for return from callback */ while(0 == clBackFlag); clBackFlag = 0; /******************** Transmission of a string **************************/ /* Enabling DMA Mode 1. */ UARTDMAEnable(UART_INSTANCE_BASE_ADD, UART_DMA_MODE_1_ENABLE); /* Configuring EDMA PaRAM sets to transmit 'enter' message. */ UartEDMATxConfTransfer(EDMA3_UART_TX_CHA_NUM, EDMA3_UART_TX_CHA_NUM, enter, sizeof(enter) - 1); /* Wait for return from callback */ while(0 == clBackFlag); clBackFlag = 0; /********************* Receiving Data from User *************************/ /* Enabling DMA Mode 1. */ UARTDMAEnable(UART_INSTANCE_BASE_ADD, UART_DMA_MODE_1_ENABLE); /* Configuring the PaRAM set for reception. */ UartEDMARxConfTransfer(EDMA3_UART_RX_CHA_NUM, EDMA3_UART_RX_CHA_NUM, rxBuffer, sizeof(rxBuffer)); /* Wait for return from callback */ while(0 == clBackFlag); clBackFlag = 0; /******************* Echoing received bytes *****************************/ /* Enabling DMA Mode 1. */ UARTDMAEnable(UART_INSTANCE_BASE_ADD, UART_DMA_MODE_1_ENABLE); /* Configuring the PaRAM set to transmit the bytes that were received. */ UartEDMATxConfTransfer(EDMA3_UART_TX_CHA_NUM, EDMA3_UART_TX_CHA_NUM, rxBuffer, sizeof(rxBuffer)); /* Wait for return from callback */ while(0 == clBackFlag); clBackFlag = 0; /******************* Freeing of allocated channels **********************/ /* Free EDMA3 Channels for TX and RX */ EDMA3FreeChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA, EDMA3_UART_TX_CHA_NUM, EDMA3_TRIG_MODE_EVENT, EDMA3_UART_TX_CHA_NUM, EVT_QUEUE_NUM); EDMA3FreeChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA, EDMA3_UART_RX_CHA_NUM, EDMA3_TRIG_MODE_EVENT, EDMA3_UART_RX_CHA_NUM, EVT_QUEUE_NUM); while(1); }
/* ** Main function. */ int main(void) { unsigned int numByteChunks = 0; unsigned char *pBuffer = NULL; unsigned int remainBytes = 0; /* Configure and enable the MMU. */ MMUConfigAndEnable(); /* Enable all levels of Cache. */ CacheEnable(CACHE_ALL); /* Configuring the system clocks for EDMA. */ EDMAModuleClkConfig(); /* Configuring the system clocks for UART0 instance. */ UART0ModuleClkConfig(); /* Performing Pin Multiplexing for UART0 instance. */ UARTPinMuxSetup(0); /* Enabling IRQ in CPSR of ARM processor. */ IntMasterIRQEnable(); /* Initializing the ARM Interrupt Controller. */ IntAINTCInit(); /* Initializing the EDMA. */ EDMA3Initialize(); /* Initializing the UART0 instance for use. */ UARTInitialize(); /* Select the console type based on compile time check */ ConsoleUtilsSetType(CONSOLE_UART); /* ** Configuring the EDMA. */ /* Request DMA Channel and TCC for UART Transmit*/ EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA, EDMA3_UART_TX_CHA_NUM, EDMA3_UART_TX_CHA_NUM, EVT_QUEUE_NUM); /* Registering Callback Function for TX*/ cb_Fxn[EDMA3_UART_TX_CHA_NUM] = &callback; /* Request DMA Channel and TCC for UART Receive */ EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA, EDMA3_UART_RX_CHA_NUM, EDMA3_UART_RX_CHA_NUM, EVT_QUEUE_NUM); /* Registering Callback Function for RX*/ cb_Fxn[EDMA3_UART_RX_CHA_NUM] = &callback; /******************** Transmission of a string **************************/ numByteChunks = (sizeof(welcome) - 1) / txBytesPerEvent; remainBytes = (sizeof(welcome) - 1) % txBytesPerEvent; /* Configuring EDMA PaRAM sets to transmit data. */ UARTTxEDMAPaRAMSetConfig(welcome, numByteChunks * txBytesPerEvent, EDMA3_UART_TX_CHA_NUM, EDMA3CC_OPT(DUMMY_CH_NUM), EDMA3_UART_TX_CHA_NUM); /* Configuring the PaRAM set for Dummy Transfer. */ TxDummyPaRAMConfEnable(); /* Enable EDMA Transfer */ EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_UART_TX_CHA_NUM, EDMA3_TRIG_MODE_EVENT); /* Wait for return from callback */ while(0 == clBackFlag); clBackFlag = 0; /* Remaining bytes are transferred through polling method. */ if(0 != remainBytes) { pBuffer = welcome + (sizeof(welcome) - 1) - remainBytes; UARTPuts((char*)pBuffer, remainBytes); } /******************** Transmission of a string **************************/ numByteChunks = (sizeof(intent) - 1) / txBytesPerEvent; remainBytes = (sizeof(intent) - 1) % txBytesPerEvent; /* Enabling DMA Mode 1. */ UARTDMAEnable(UART_INSTANCE_BASE_ADD, UART_DMA_MODE_1_ENABLE); /* Configuring EDMA PaRAM sets to transmit data. */ UARTTxEDMAPaRAMSetConfig(intent, numByteChunks * txBytesPerEvent, EDMA3_UART_TX_CHA_NUM, EDMA3CC_OPT(DUMMY_CH_NUM), EDMA3_UART_TX_CHA_NUM); /* Configuring the PaRAM set for Dummy Transfer. */ TxDummyPaRAMConfEnable(); /* Enable EDMA Transfer */ EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_UART_TX_CHA_NUM, EDMA3_TRIG_MODE_EVENT); /* Wait for return from callback */ while(0 == clBackFlag); clBackFlag = 0; /* Remaining bytes are transferred through polling method. */ if(0 != remainBytes) { pBuffer = intent + (sizeof(intent) - 1) - remainBytes; UARTPuts((char*)pBuffer, remainBytes); } /******************** Transmission of a string **************************/ numByteChunks = (sizeof(enter) - 1) / txBytesPerEvent; remainBytes = (sizeof(enter) - 1) % txBytesPerEvent; /* Enabling DMA Mode 1. */ UARTDMAEnable(UART_INSTANCE_BASE_ADD, UART_DMA_MODE_1_ENABLE); /* Configuring EDMA PaRAM sets to transmit data. */ UARTTxEDMAPaRAMSetConfig(enter, numByteChunks * txBytesPerEvent, EDMA3_UART_TX_CHA_NUM, EDMA3CC_OPT(DUMMY_CH_NUM), EDMA3_UART_TX_CHA_NUM); /* Configuring the PaRAM set for Dummy Transfer. */ TxDummyPaRAMConfEnable(); /* Enable EDMA Transfer */ EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_UART_TX_CHA_NUM, EDMA3_TRIG_MODE_EVENT); /* Wait for return from callback */ while(0 == clBackFlag); clBackFlag = 0; /* Remaining bytes are transferred through polling method. */ if(0 != remainBytes) { pBuffer = enter + (sizeof(enter) - 1) - remainBytes; UARTPuts((char*)pBuffer, remainBytes); } /********************* Receiving Data from User *************************/ /* Enabling DMA Mode 1. */ UARTDMAEnable(UART_INSTANCE_BASE_ADD, UART_DMA_MODE_1_ENABLE); /* Configuring the PaRAM set for reception. */ UARTRxEDMAPaRAMSetConfig(rxBuffer, NUM_RX_BYTES, EDMA3_UART_RX_CHA_NUM, 0xFFFF, EDMA3_UART_RX_CHA_NUM); /* Enable EDMA Transfer */ EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_UART_RX_CHA_NUM, EDMA3_TRIG_MODE_EVENT); /* Wait for return from callback */ while(0 == clBackFlag); clBackFlag = 0; /******************* Echoing received bytes *****************************/ numByteChunks = (NUM_RX_BYTES) / txBytesPerEvent; remainBytes = (NUM_RX_BYTES) % txBytesPerEvent; /* Enabling DMA Mode 1. */ UARTDMAEnable(UART_INSTANCE_BASE_ADD, UART_DMA_MODE_1_ENABLE); /* Configuring EDMA PaRAM sets to transmit data. */ UARTTxEDMAPaRAMSetConfig(rxBuffer, numByteChunks * txBytesPerEvent, EDMA3_UART_TX_CHA_NUM, EDMA3CC_OPT(DUMMY_CH_NUM), EDMA3_UART_TX_CHA_NUM); /* Configuring the PaRAM set for Dummy Transfer. */ TxDummyPaRAMConfEnable(); /* Enable EDMA Transfer */ EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_UART_TX_CHA_NUM, EDMA3_TRIG_MODE_EVENT); /* Wait for return from callback */ while(0 == clBackFlag); clBackFlag = 0; /* Remaining bytes are transferred through polling method. */ if(0 != remainBytes) { pBuffer = rxBuffer + NUM_RX_BYTES - remainBytes; UARTPuts((char*)pBuffer, remainBytes); } /******************* Freeing of allocated channels **********************/ /* Free EDMA3 Channels for TX and RX */ EDMA3FreeChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA, EDMA3_UART_TX_CHA_NUM, EDMA3_TRIG_MODE_EVENT, EDMA3_UART_TX_CHA_NUM, EVT_QUEUE_NUM); EDMA3FreeChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA, EDMA3_UART_RX_CHA_NUM, EDMA3_TRIG_MODE_EVENT, EDMA3_UART_RX_CHA_NUM, EVT_QUEUE_NUM); /* Support for Automation Testing. */ PRINT_STATUS(S_PASS); while(1); }
void InitUartInterface(uint32_t sys_clock) { uart_rx_read_index = 0; uart_rx_write_index = 0; const uint32_t dma_rx_primary = UDMA_CHANNEL_UART1RX | UDMA_PRI_SELECT; SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1); SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UART1); //921600 //460800 uint32_t uart_config = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE; UARTConfigSetExpClk(UART1_BASE, sys_clock, 921600, uart_config); GPIOPinConfigure(GPIO_PB0_U1RX); GPIOPinConfigure(GPIO_PB1_U1TX); GPIOPinTypeUART(GPIO_PORTB_BASE, GPIO_PIN_0 | GPIO_PIN_1); UARTFIFOLevelSet(UART1_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8); UARTEnable(UART1_BASE); //UARTDMAEnable(UART1_BASE, UART_DMA_RX | UART_DMA_TX); UARTDMAEnable(UART1_BASE, UART_DMA_RX); // Put the attributes in a known state for the uDMA UART1RX channel. These // should already be disabled by default. uint32_t dma_config = UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK; uDMAChannelAttributeDisable(UDMA_CHANNEL_UART1RX, dma_config); uint32_t dma_control = UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 | UDMA_ARB_4; uDMAChannelControlSet(dma_rx_primary, dma_control); uDMAChannelTransferSet(dma_rx_primary, UDMA_MODE_BASIC, (void *)(UART1_BASE + UART_O_DR), &uart_rx_buf[uart_rx_write_index], UART_RX_BLOCK_SIZE); // Put the attributes in a known state for the uDMA UART1TX channel. These // should already be disabled by default. // uDMAChannelAttributeDisable(UDMA_CHANNEL_UART1TX, // UDMA_ATTR_ALTSELECT | // UDMA_ATTR_HIGH_PRIORITY | // UDMA_ATTR_REQMASK); // Set the USEBURST attribute for the uDMA UART TX channel. This will // force the controller to always use a burst when transferring data from // the TX buffer to the UART. This is somewhat more effecient bus usage // than the default which allows single or burst transfers. //uDMAChannelAttributeEnable(UDMA_CHANNEL_UART1TX, UDMA_ATTR_USEBURST); // Configure the control parameters for the UART TX. The uDMA UART TX // channel is used to transfer a block of data from a buffer to the UART. // The data size is 8 bits. The source address increment is 8-bit bytes // since the data is coming from a buffer. The destination increment is // none since the data is to be written to the UART data register. The // arbitration size is set to 4, which matches the UART TX FIFO trigger // threshold. // uDMAChannelControlSet(UDMA_CHANNEL_UART1TX | UDMA_PRI_SELECT, // UDMA_SIZE_8 | UDMA_SRC_INC_8 | // UDMA_DST_INC_NONE | // UDMA_ARB_4); // Set up the transfer parameters for the uDMA UART TX channel. This will // configure the transfer source and destination and the transfer size. // Basic mode is used because the peripheral is making the uDMA transfer // request. The source is the TX buffer and the destination is the UART // data register. // uDMAChannelTransferSet(UDMA_CHANNEL_UART1TX | UDMA_PRI_SELECT, // UDMA_MODE_BASIC, g_ui8TxBuf, // (void *)(UART1_BASE + UART_O_DR), // sizeof(g_ui8TxBuf)); // Now both the uDMA UART TX and RX channels are primed to start a // transfer. As soon as the channels are enabled, the peripheral will // issue a transfer request and the data transfers will begin. uDMAChannelEnable(UDMA_CHANNEL_UART1RX); //uDMAChannelEnable(UDMA_CHANNEL_UART1TX); // Enable the UART DMA TX/RX interrupts. //UARTIntEnable(UART1_BASE, UART_INT_DMATX | UART_INT_DMATX); UARTIntEnable(UART1_BASE, UART_INT_DMARX); IntEnable(INT_UART1); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0); MAP_TimerConfigure(TIMER0_BASE, TIMER_CFG_PERIODIC); MAP_TimerLoadSet(TIMER0_BASE, TIMER_A, sys_clock / 2000); MAP_IntEnable(INT_TIMER0A); MAP_TimerIntEnable(TIMER0_BASE, TIMER_TIMA_TIMEOUT); MAP_TimerEnable(TIMER0_BASE, TIMER_A); MAP_IntPrioritySet(INT_TIMER0A, 0xC0); }