/* ** A wrapper function performing FIFO configurations. */ static void UartFIFOConfigure(void) { unsigned int fifoConfig = 0; /* ** Transmitter Trigger Level Granularity is 1. ** Receiver Trigger Level Granularity is 1. ** Transmit Trigger Space set using 'txTrigSpace'. ** Receive Trigger level set using 'rxTrigLevel'. ** Clear the Trasnmit FIFO. ** Clear the Receive FIFO. ** DMA Mode enabling shall happen through SCR register. ** DMA Mode 1 is enabled. */ fifoConfig = UART_FIFO_CONFIG(UART_TRIG_LVL_GRANULARITY_1, UART_TRIG_LVL_GRANULARITY_1, txTrigSpace, rxTrigLevel, 1, 1, UART_DMA_EN_PATH_SCR, UART_DMA_MODE_1_ENABLE); /* Configuring the FIFO settings. */ UARTFIFOConfig(UART_INSTANCE_BASE_ADD, fifoConfig); }
static void UartFIFOConfigure(void) { unsigned int fifoConfig = 0; /* ** - Transmit Trigger Level Granularity is 4 ** - Receiver Trigger Level Granularity is 1 ** - Transmit FIFO Space Setting is 56. Hence TX Trigger level ** is 8 (64 - 56). The TX FIFO size is 64 bytes. ** - The Receiver Trigger Level is 1. ** - Clear the Transmit FIFO. ** - Clear the Receiver FIFO. ** - DMA Mode enabling shall happen through SCR register. ** - DMA Mode 0 is enabled. DMA Mode 0 corresponds to No ** DMA Mode. Effectively DMA Mode is disabled. */ fifoConfig = UART_FIFO_CONFIG(UART_TRIG_LVL_GRANULARITY_4, UART_TRIG_LVL_GRANULARITY_1, UART_FCR_TX_TRIG_LVL_56, 1, 1, 1, UART_DMA_EN_PATH_SCR, UART_DMA_MODE_0_ENABLE); /* Configuring the FIFO settings. */ UARTFIFOConfig(SOC_UART_0_REGS, fifoConfig); }
/* ** A wrapper function performing FIFO configurations. */ static void UartFIFOConfigure(void) { unsigned int fifoConfig = 0; /* Setting the TX and RX FIFO Trigger levels as 1. No DMA enabled. */ fifoConfig = UART_FIFO_CONFIG(UART_TRIG_LVL_GRANULARITY_1, UART_TRIG_LVL_GRANULARITY_1, 1, 1, 1, 1, UART_DMA_EN_PATH_SCR, UART_DMA_MODE_0_ENABLE); /* Configuring the FIFO settings. */ UARTFIFOConfig(SOC_UART_0_REGS, fifoConfig); }
/* ** The main function */ int main() { unsigned int divisorValue = 0; /* Configuring the system clocks for UART0 instance. */ UART0ModuleClkConfig(); /* Initializing the ARM Interrupt Controller. */ IntAINTCInit(); /* Performing the Pin Multiplexing for UART0 instance. */ UARTPinMuxSetup(0); /* Performing a module reset. */ UARTModuleReset(UART_INST_BASE); UARTFIFOConfig(UART_INST_BASE, UART_FIFO_CONFIG(UART_TRIG_LVL_GRANULARITY_1, UART_TRIG_LVL_GRANULARITY_1, 1, 1, 1, 1, UART_DMA_EN_PATH_SCR, UART_DMA_MODE_0_ENABLE)); /* Computing the Divisor Value. */ divisorValue = UARTDivisorValCompute(UART_MODULE_INPUT_CLK, BAUD_RATE_115200, UART16x_OPER_MODE, UART_MIR_OVERSAMPLING_RATE_42); /* Programming the Divisor Latches. */ UARTDivisorLatchWrite(UART_INST_BASE, divisorValue); /* Switching to Configuration Mode B. */ UARTRegConfigModeEnable(UART_INST_BASE, UART_REG_CONFIG_MODE_B); /* Programming the Line Characteristics. */ UARTLineCharacConfig(UART_INST_BASE, (UART_FRAME_WORD_LENGTH_8 | UART_FRAME_NUM_STB_1), UART_PARITY_NONE); /* Disabe write access to Divisor Latches. */ UARTDivisorLatchDisable(UART_INST_BASE); /* Disable Break Control. */ UARTBreakCtl(UART_INST_BASE, UART_BREAK_COND_DISABLE); /* Switch to UART16x operating mode. */ UARTOperatingModeSelect(UART_INST_BASE, UART16x_OPER_MODE); UARTIntEnable(UART_INST_BASE, (UART_INT_LINE_STAT | UART_INT_THR | UART_INT_RHR_CTI)); /* Register the Interrupt Service Routines */ IntRegister(RTC_INT_NUM, RTCIsr); IntRegister(UART_INT_NUM, UARTIsr); IntRegister(TIMER_INT_NUM, DMTimerIsr); /* ** Setting the priority for the system interrupt in AINTC. ** Timer interrupt is given highest priority - 1 ** RTC interrupt is given medium priority - 2 ** UART interrupt is given lowest priority - 4 */ IntPrioritySet(TIMER_INT_NUM, IRQ_PRIORITY_TIMER, AINTC_HOSTINT_ROUTE_IRQ); IntPrioritySet(RTC_INT_NUM, IRQ_PRIORITY_RTC, AINTC_HOSTINT_ROUTE_IRQ); IntPrioritySet(UART_INT_NUM, IRQ_PRIORITY_UART, AINTC_HOSTINT_ROUTE_IRQ); /* Enabling the system interrupt in AINTC for UART */ IntSystemEnable(UART_INT_NUM); IntMasterIRQEnable(); while(1); }