/********************************************************************************************************* ** Function name: uart2TranControl ** Descriptions: UARTµÄ´«Êä¿ØÖÆ ** input parameters: ucTxEnable:·¢ËÍʹÄÜ¿ØÖÆ£»ucRxEnable:½ÓÊÕʹÄÜ¿ØÖÆ ** output parameters: none ** Returned value: none ** Created by: ** Created date: **-------------------------------------------------------------------------------------------------------- ** Modified by: ** Modified date: *********************************************************************************************************/ void uart2TranControl (INT8U ucTxEnable, INT8U ucRxEnable) { UART_MemMapPtr uartPtr = UART2_BASE_PTR; #if UART_PARAM_DEBUG UART_CHECK_PARAM(UART_PARAM_LOGIC(ucTxEnable)); UART_CHECK_PARAM(UART_PARAM_LOGIC(ucRxEnable)); #endif UART_C2_REG(uartPtr) &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK); UART_C2_REG(uartPtr) |= (ucTxEnable << UART_C2_TE_SHIFT)| (ucRxEnable << UART_C2_RE_SHIFT); }
void UART_init(void) { // Habilito la llave general de las interrupciones NVICISER0 |= NVIC_ISER_SETENA(1<<31); //Habilito los cuatro modulos de UART SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK; // Habilito el pin PTC1 como salida del canal 0 PORTB_PCR16 = (PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03)); //Tx PORTB_PCR17 = (PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03)); //Rx //Habilito por interrupcion, un bit de stop y baudrate UART_C1_REG(UART0_BASE_PTR) = 0x00; UART_BDH_REG(UART0_BASE_PTR) = /*UART_BDH_RXEDGIE_MASK | */UART_BDH_SBR(BAUDRATEHIGH); UART_BDL_REG(UART0_BASE_PTR) = UART_BDL_SBR(BAUDRATELOW); UART_C2_REG(UART0_BASE_PTR) = UART_C2_TIE_MASK | UART_C2_TE_MASK | UART_C2_RE_MASK | UART_C2_RIE_MASK; UART_C3_REG(UART0_BASE_PTR) = UART_C3_TXDIR_MASK; UART_PFIFO_REG(UART0_BASE_PTR) = UART_PFIFO_TXFE_MASK | UART_PFIFO_TXFIFOSIZE(0x06) | UART_PFIFO_RXFE_MASK | UART_PFIFO_RXFIFOSIZE(0x01); UART_S2_REG(UART0_BASE_PTR) = 0x00; }
bool FEHXBee::Initialize() { if( !_initialized ) { _initialized = true; // Init uart clock for xbee connection SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; // XBEE UART: // Signal JTAG_TDI-XBEE_RX - UART0_RX - PTA1 - Pin 52 // Signal JTAG_TDO-XBEE_TX - UART0_TX - PTA2 - Pin 53 // UART function on Alt2, JTAG on Alt7 PORTA_PCR1 = PORT_PCR_MUX( 0x2 ); PORTA_PCR2 = PORT_PCR_MUX( 0x2 ); // Initialize propeller UART uart_init( UART0_BASE_PTR, CoreClockKHz, 9600 ); // uart_init( UART0_BASE_PTR, CoreClockKHz, 115200 ); // Setup interrupt on UART0 // disable receiver while changing settings UART_C2_REG( UART0_BASE_PTR ) &= ~( UART_C2_TE_MASK | UART_C2_RE_MASK ); // enable interrupt UART_C2_REG( UART0_BASE_PTR ) |= UART_C2_RIE_MASK; // set to interrupt not dma UART_C5_REG( UART0_BASE_PTR ) &= ~( UART_C5_RDMAS_MASK ); // enable interrupt on IRQ = 45 NVICICPR1 |= 1 << ( 13 ); NVICISER1 |= 1 << ( 13 ); // enable receiver UART_C2_REG( UART0_BASE_PTR ) |= ( UART_C2_TE_MASK | UART_C2_RE_MASK ); // wait for UART to init Sleep( 100 ); _initialized = true; return true; } return false; }
/********************************************************************************************************* ** Function name: uart2Init ** Descriptions: UART2µÄ³õʼ»¯ ** input parameters: ucBaudRate:²¨ÌØÂÊ£»ucParityEnable:УÑéλѡÔñ£» ** ucParityType:УÑéÀàÐÍ£»ucDataLength:Êý¾Ý³¤¶È£»ucStopBit:ֹͣλ£» ** output parameters: none ** Returned value: none ** Created by: ** Created date: **-------------------------------------------------------------------------------------------------------- ** Modified by: ** Modified date: *********************************************************************************************************/ void uart2Init (INT32U ulBaudRate, INT8U ucParityEnable, INT8U ucParityType, INT8U ucDataLength, INT8U ucStopBit) { UART_MemMapPtr uartPtr = UART2_BASE_PTR; register INT16U usBaudRate = 0; #if UART_PARAM_DEBUG UART_CHECK_PARAM(UART_PARAM_LENGTH(ucDataLength)); UART_CHECK_PARAM(UART_PARAM_STOP(ucStopBit)); UART_CHECK_PARAM(UART_PARAM_LOGIC(ucParityEnable)); UART_CHECK_PARAM(UART_PARAM_PARITY(ucParityType)); #endif SIM_SCGC4 |= SIM_SCGC4_UART2_MASK; /* ÔÊÐíÍâÉèʱÖÓ */ uart2TranControl(UART_TX_DISABLE, UART_RX_DISABLE); /* Ê×ÏȽûֹͨÐÅ */ #if 0 PORTD_PCR3 = PORT_PCR_MUX(0x3); /* UART2_TXD */ PORTD_PCR2 = PORT_PCR_MUX(0x3); /* UART2_RXD */ #endif #if 0 PORTD_PCR5 = PORT_PCR_MUX(0x3); /* UART2_TXD */ PORTD_PCR4 = PORT_PCR_MUX(0x3); /* UART2_RXD */ #endif #if 0 PORTE_PCR22 = PORT_PCR_MUX(0x4); /* UART2_TXD */ PORTE_PCR23 = PORT_PCR_MUX(0x4); /* UART2_RXD */ #endif UART_C1_REG(uartPtr) &= ~(UART_C1_M_MASK | /* Êý¾Ý³¤¶È */ UART_C1_PT_MASK | /* УÑéλÀàÐÍ */ UART_C1_PE_MASK); /* УÑéλ */ UART_C1_REG(uartPtr) |= ((ucDataLength - 8UL) << UART_C1_M_SHIFT)| (ucParityEnable << UART_C1_PE_SHIFT)| (ucParityType << UART_C1_PT_SHIFT); usBaudRate = SystemBusClock/(ulBaudRate * 16); UART_BDH_REG(uartPtr) = (usBaudRate & 0x1F00) >> 8; /* ²¨ÌØÂÊ */ UART_BDL_REG(uartPtr) = (INT8U)(usBaudRate & UART_BDL_SBR_MASK); UART_BDH_REG(uartPtr) &= ~UART_BDH_SBNS_MASK; /* ֹͣλ */ UART_BDH_REG(uartPtr) |= (ucStopBit - 1) << UART_BDH_SBNS_SHIFT; UART_C2_REG(uartPtr) &= ~(UART_C2_TIE_MASK | UART_C2_TCIE_MASK| /* Çå³ýÖжÏÉèÖà */ UART_C2_RIE_MASK | UART_C2_ILIE_MASK); while ((UART_S1_REG(uartPtr) & UART_S1_RDRF_MASK) && (UART_D_REG(uartPtr))); /* Çå½ÓÊÕ»º³åÇø */ #if UART2_IRQ_ENABLE #if UART2_SEND_IRQ UART_C2_REG(uartPtr) |= UART_C2_TCIE_MASK; #endif #if UART2_RECEIVE_IRQ UART_C2_REG(uartPtr) |= UART_C2_RIE_MASK; #endif NVIC_EnableIRQ(UART2_IRQn); NVIC_SetPriority(UART2_IRQn,3); /* Óû§×Ô¼º¶¨Òå */ #endif }
void UART_TransferComplete() { UART_C2_REG(UART0_BASE_PTR) &= ~UART_C2_TIE_MASK; }
void UART_writeByte(uint8_t data) { UART_D_REG(UART0_BASE_PTR) = data; UART_C2_REG(UART0_BASE_PTR) |= UART_C2_TIE_MASK; }