BOOL UART_Init(const uint32_t baudRate, const uint32_t moduleClk)
{
uint16union_t SBR; /*!<UART baud rate*/
register uint16_t brfa; /*!<baud rate fine adjust*/
SIM_SCGC5 = 1<<13; /*!Enable PORTE clock gate control.UART2:13*/
PORTE_PCR16 = 3<<8; /*!Set MUX(bit 10 to 8) to 3(011) in PORTE16 to choose ALT3 to choose UART2_TX.*/
PORTE_PCR17 = 3<<8; /*!Set MUX(bit 10 to 8) to (011)3 in PORTE17 to choose ALT3 to choose UART2_RX.*/
SIM_SCGC4 = 1<<12; /*! Enable UART2 clock gate control. UART2:12.*/
UART2_C1 = 0x00; /*!8 bits data, Parity function disabled. PE*/
UART2_MODEM = 0x00;
SBR.l = (moduleClk/baudRate)/16; /*!Baud Rate Generation.*/
brfa = (((moduleClk<<5)/(baudRate<<4))-(SBR.l<<5));
UART2_C4 = (UART2_C4 &~(UART_C4_BRFA(0x1F)))|UART_C4_BRFA(brfa);
SBR.l &=(~BIT15TO13); /*!make bit 15 to 13 equal to 0. 0xXXXX & ~0xe000(0x1fff)it should be 000xxxxxxxxxxxxx*/
UART2_BDH = SBR.s.Hi; /*!type.h BDH is the first part of uint16union_t SBR*/
UART2_BDL = SBR.s.Lo; /*!type.h BDL is the second part of uint16union_t SBR*/
UART2_C2 = UART_C2_RE_MASK | UART_C2_TE_MASK; /*!Transmitter Enable, no interrupt.TE RE:00001100*/
UART2_C2 |= UART_C2_RIE_MASK; /*!enable receiver full interrupt*/
UART2_C2 &= ~UART_C2_TIE_MASK; /*!disable transmitter interrupt*/
NVICICPR1 = (1<<17); /*! clear any pending interrupts on uart2: by using table 3-5 the UART status source IRQ is 49 NCIC number is 1, using function 49 mode 32*/
NVICISER1 = (1<<17); /*!enable interrupts from UART module*/
return bTRUE;
}
// =============================================================================
// 功能: 设置串口串口的波特率，FreescaleKxx的UART0和UART1时钟源为CORE，其他的时钟源
// 为BUS时钟
// 参数: Reg,被操作的寄存器组指针
// baud,波特率
// 返回: 无
// =============================================================================
static void __UART_BaudSet(tagUartReg volatile *Reg,u32 baud)
{
u32 UartClk;
u16 Sbr,Brfa;
u8 temp;
if(Reg == NULL) return;
if(((u32)Reg == CN_UART0_BASE) || ((u32)Reg == CN_UART1_BASE))
UartClk = CN_CFG_MCLK;
else
UartClk = CN_CFG_MCLK/2;
Sbr = (u16)(UartClk/(baud * 16));
Brfa = (((UartClk*32)/(baud * 16)) - (Sbr * 32));
//配置波特率
temp = Reg->BDH & ~(UART_BDH_SBR(0x1F));
Reg->BDH = temp | UART_BDH_SBR(((Sbr & 0x1F00) >> 8));
Reg->BDL = (u8)(Sbr & UART_BDL_SBR_MASK);
//用于校正
temp = Reg->C4 & ~(UART_C4_BRFA(0x1F));
Reg->C4 = temp | UART_C4_BRFA(Brfa);
if(tg_UART_Reg[TxDirectPort] == Reg)
{
TxByteTime = 11000000/baud; //1个字节传输时间，按10bit，+10%计算
}
}
static void hw_uart_init(void)
{
register uint16_t sbr, brfa;
uint8_t temp;
/* Enable UART core clock */
SIM->SCGC1 |= SIM_SCGC1_UART5_MASK;
/* Configure UART TX pin */
UART_TX_PORT->PCR[UART_TX_PIN] = PORT_PCR_MUX(UART_TX_MUX);
/* Disable transmitter and receiver while we change settings. */
UART_PORT->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK );
/* Configure the UART for 8-bit mode, no parity */
UART_PORT->C1 = 0;
/* Calculate baud settings */
sbr = (uint16_t)((BUS_CLK_KHZ * 1000)/(UART_BAUD * 16));
temp = UART_PORT->BDH & ~(UART_BDH_SBR(0x1F));
UART_PORT->BDH = temp | UART_BDH_SBR(((sbr & 0x1F00) >> 8));
UART_PORT->BDL = (uint8_t)(sbr & UART_BDL_SBR_MASK);
/* Determine if a fractional divider is needed to get closer to the baud rate */
brfa = (((BUS_CLK_KHZ * 32000)/(UART_BAUD * 16)) - (sbr * 32));
temp = UART_PORT->C4 & ~(UART_C4_BRFA(0x1F));
UART_PORT->C4 = temp | UART_C4_BRFA(brfa);
/* Enable receiver and transmitter */
UART_PORT->C2 |= (UART_C2_TE_MASK | UART_C2_RE_MASK);
}
/* ===================================================================*/
LDD_TDeviceData* ASerialLdd2_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate device structure */
ASerialLdd2_TDeviceDataPtr DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
/* Clear the receive counters and pointer */
DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */
/* Clear the transmit counters and pointer */
DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
/* SIM_SCGC4: UART0=1 */
SIM_SCGC4 |= SIM_SCGC4_UART0_MASK;
/* PORTB_PCR16: ISF=0,MUX=3 */
PORTB_PCR16 = (uint32_t)((PORTB_PCR16 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x04)
)) | (uint32_t)(
PORT_PCR_MUX(0x03)
));
/* PORTB_PCR17: ISF=0,MUX=3 */
PORTB_PCR17 = (uint32_t)((PORTB_PCR17 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x04)
)) | (uint32_t)(
PORT_PCR_MUX(0x03)
));
UART_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */
UART_PDD_EnableReceiver(UART0_BASE_PTR, PDD_DISABLE); /* Disable receiver. */
DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */
DeviceDataPrv->ErrFlag = 0x00U; /* Reset error flags */
/* UART0_C1: LOOPS=0,UARTSWAI=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */
UART0_C1 = 0x00U; /* Set the C1 register */
/* UART0_C3: R8=0,T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */
UART0_C3 = 0x00U; /* Set the C3 register */
/* UART0_C4: MAEN1=0,MAEN2=0,M10=0,BRFA=0 */
UART0_C4 = UART_C4_BRFA(0x00); /* Set the C4 register */
/* UART0_S2: LBKDIF=0,RXEDGIF=0,MSBF=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */
UART0_S2 = 0x00U; /* Set the S2 register */
/* UART0_MODEM: ??=0,??=0,??=0,??=0,RXRTSE=0,TXRTSPOL=0,TXRTSE=0,TXCTSE=0 */
UART0_MODEM = 0x00U; /* Set the MODEM register */
UART_PDD_SetBaudRateFineAdjust(UART0_BASE_PTR, 18u); /* Set baud rate fine adjust */
UART_PDD_SetBaudRate(UART0_BASE_PTR, 13U); /* Set the baud rate register. */
UART_PDD_EnableFifo(UART0_BASE_PTR, (UART_PDD_TX_FIFO_ENABLE | UART_PDD_RX_FIFO_ENABLE)); /* Enable RX and TX FIFO */
UART_PDD_FlushFifo(UART0_BASE_PTR, (UART_PDD_TX_FIFO_FLUSH | UART_PDD_RX_FIFO_FLUSH)); /* Flush RX and TX FIFO */
UART_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_ENABLE); /* Enable transmitter */
UART_PDD_EnableReceiver(UART0_BASE_PTR, PDD_ENABLE); /* Enable receiver */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_ASerialLdd2_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv);
}
static void hw_uart_init(void)
{
register uint16_t sbr, brfa;
uint8_t temp;
#ifdef FREESCALE_KSDK_BM
PORT_SetPinMux(UART_TX_PORT, UART_TX_PIN, UART_TX_MUX);
CLOCK_SetLpuartClock(1); /* MCGPLLCLK */
DbgConsole_Init((uint32_t)UART_PORT, UART_BAUD, DEBUG_CONSOLE_DEVICE_TYPE_LPUART, SYS_CLK_HZ);
#else
/* Enable UART core clock */
/* Note: Remember to update me if UART_PORT changes */
SIM->SCGC1 |= SIM_SCGC1_UART4_MASK;
/* Configure UART TX pin */
UART_TX_PORT->PCR[UART_TX_PIN] = PORT_PCR_MUX(UART_TX_MUX);
/* Disable transmitter and receiver while we change settings. */
UART_PORT->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK );
/* Configure the UART for 8-bit mode, no parity */
UART_PORT->C1 = 0;
/* Calculate baud settings */
sbr = (uint16_t)((BUS_CLK_KHZ * 1000)/(UART_BAUD * 16));
temp = UART_PORT->BDH & ~(UART_BDH_SBR(0x1F));
UART_PORT->BDH = temp | UART_BDH_SBR(((sbr & 0x1F00) >> 8));
UART_PORT->BDL = (uint8_t)(sbr & UART_BDL_SBR_MASK);
/* Determine if a fractional divider is needed to get closer to the baud rate */
brfa = (((BUS_CLK_KHZ * 32000)/(UART_BAUD * 16)) - (sbr * 32));
temp = UART_PORT->C4 & ~(UART_C4_BRFA(0x1F));
UART_PORT->C4 = temp | UART_C4_BRFA(brfa);
/* Enable receiver and transmitter */
UART_PORT->C2 |= (UART_C2_TE_MASK | UART_C2_RE_MASK);
#endif
}
void init_uart0 (void)
{
uint16_t ubd, bfra;
uint8_t temp;
//Settings pins
SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;
PORTE->PCR [RX] |= PORT_PCR_MUX(3);
PORTE->PCR [TX] |= PORT_PCR_MUX(3);
PTE->PDDR |= 1 << TX;
//Settings uart
SIM->SCGC4 |= SIM_SCGC4_UART1_MASK;
UART1->C2 &= ~(UART_C2_TE_MASK|UART_C2_RE_MASK);
UART1->C1 = 0;
ubd = (uint16_t) ((F_CPU*1000)/(BAUD*16));
temp = UART1->BDH & ~(UART_BDH_SBR(0x1F));
UART1->BDH = temp | UART_BDH_SBR(((ubd & 0x1F00) >> 8));
UART1->BDL = (uint8_t) (ubd & UART_BDL_SBR_MASK);
bfra = (((F_CPU*32000)/(BAUD*16)) - (ubd*32));
temp = UART1->C4 & ~(UART_C4_BRFA(0x1F));
UART1->C4 = temp | UART_C4_BRFA(bfra);
UART1->C2 |= UART_C2_RE_MASK|UART_C2_TE_MASK;
}
BOOL UART_SetBaud ( UART_Type *UARTx, INT32U baud )
{
BOOL ret = TRUE;
INT16U sbr,tmp,brfa;
sbr = (INT32U)((UART_PCLK) / (baud * 16));
tmp = UARTx->BDH & ~UART_BDH_SBR_MASK;
UARTx->BDH = tmp | UART_BDH_SBR(((sbr & 0x1F00) >> 8));
UARTx->BDL = (INT8U)(sbr & UART_BDL_SBR_MASK);
brfa = (((UART_PCLK * 32)/(baud * 16)) - (sbr * 32));
tmp = UARTx->C4 & ~UART_C4_BRFA_MASK;
UARTx->C4 = tmp | UART_C4_BRFA(brfa);
return (ret);
}
void debugInit(uint32_t baudrate)
{
uint32_t div;
uint32_t busClockFreq;
//Clock 2 output divider value
div = (SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT;
//Bus clock frequency
busClockFreq = SystemCoreClock / (div + 1);
//Compute the UART baudrate prescaler
div = ((2 * busClockFreq) + (baudrate / 2)) / baudrate;
//Enable PORTC peripheral clock
SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
//Enable UART3 peripheral clock
SIM->SCGC4 |= SIM_SCGC4_UART3_MASK;
//Configure PTC16 (UART3_RX) and PTC17 (UART3_TX)
PORTC->PCR[16] = PORT_PCR_MUX(3);
PORTC->PCR[17] = PORT_PCR_MUX(3);
//LSB is transmitted first
UART3->S2 = 0;
//8-bit mode, no parity
UART3->C1 = 0;
//Transmit data is not inverted
UART3->C3 = 0;
//Baud rate fine ajust
UART3->C4 = UART_C4_BRFA(div & 0x1F);
//Select baudrate
UART3->BDH = UART_BDH_SBR((div >> 13) & 0x1F);
UART3->BDL = UART_BDL_SBR((div >> 5) & 0xFF);
//Transmit FIFO watermark
UART3->TWFIFO = UART_TWFIFO_TXWATER(0);
//Receive FIFO watermark
UART3->RWFIFO = UART_RWFIFO_RXWATER(1);
//Enable transmitter and receiver
UART3->C2 = UART_C2_TE_MASK | UART_C2_RE_MASK;
}
/*
* LPLD_UART_Init
* 初始化UART通道、波特率、发送接收引脚
*
* 参数:
* uart_init_structure--UART初始化结构体，
* 具体定义见UART_InitTypeDef
*
* 输出:
* 无
*
*/
void LPLD_UART_Init(UART_InitTypeDef uart_init_structure)
{
register uint16 sbr, brfa;
uint32 sysclk;
uint8 temp, x;
UART_Type *uartx = uart_init_structure.UART_Uartx;
uint32 baud = uart_init_structure.UART_BaudRate;
PortPinsEnum_Type tx_pin = uart_init_structure.UART_TxPin;
PortPinsEnum_Type rx_pin = uart_init_structure.UART_RxPin;
UART_ISR_CALLBACK rx_isr = uart_init_structure.UART_RxIsr;
UART_ISR_CALLBACK tx_isr = uart_init_structure.UART_TxIsr;
if(baud == NULL)
{
baud = 9600;
}
//使能选中的UART串口通道时钟，相应GPIO的UART复用功能
if(uartx == UART0)
{
x = 0;
sysclk = g_core_clock;
SIM->SCGC4 |= SIM_SCGC4_UART0_MASK;
if(tx_pin == PTA2)
PORTA->PCR[2] = PORT_PCR_MUX(2);
else if(tx_pin == PTA14)
PORTA->PCR[14] = PORT_PCR_MUX(3);
else
PORTB->PCR[17] = PORT_PCR_MUX(3);
if(rx_pin == PTA1)
PORTA->PCR[1] = PORT_PCR_MUX(2);
else if(rx_pin == PTA15)
PORTA->PCR[15] = PORT_PCR_MUX(3);
else
PORTB->PCR[16] = PORT_PCR_MUX(3);
}
else
{
if (uartx == UART1)
{
x = 1;
sysclk = g_core_clock;
SIM->SCGC4 |= SIM_SCGC4_UART1_MASK;
if(tx_pin == PTE0)
PORTE->PCR[0] = PORT_PCR_MUX(3);
else
PORTC->PCR[4] = PORT_PCR_MUX(3);
if(rx_pin == PTE1)
PORTE->PCR[1] = PORT_PCR_MUX(3);
else
PORTC->PCR[3] = PORT_PCR_MUX(3);
}
else
{
sysclk = g_bus_clock;
if (uartx == UART2)
{
x = 2;
SIM->SCGC4 |= SIM_SCGC4_UART2_MASK;
PORTD->PCR[3] = PORT_PCR_MUX(3);
PORTD->PCR[2] = PORT_PCR_MUX(3);
}
else
{
if(uartx == UART3)
{
x = 3;
SIM->SCGC4 |= SIM_SCGC4_UART3_MASK;
if(tx_pin == PTE4)
PORTE->PCR[4] = PORT_PCR_MUX(3);
else if(tx_pin == PTB11)
PORTB->PCR[11] = PORT_PCR_MUX(3);
else
PORTC->PCR[17] = PORT_PCR_MUX(3);
if(rx_pin == PTE5)
PORTE->PCR[5] = PORT_PCR_MUX(3);
else if(rx_pin == PTB10)
PORTB->PCR[10] = PORT_PCR_MUX(3);
else
PORTC->PCR[16] = PORT_PCR_MUX(3);
}
else
{
if(uartx == UART4)
{
x = 4;
SIM->SCGC1 |= SIM_SCGC1_UART4_MASK;
if(tx_pin == PTE24)
PORTE->PCR[24] = PORT_PCR_MUX(3);
else
PORTC->PCR[15] = PORT_PCR_MUX(3);
if(rx_pin == PTE25)
PORTE->PCR[25] = PORT_PCR_MUX(3);
else
PORTC->PCR[14] = PORT_PCR_MUX(3);
}
else
{
x = 5;
uartx = UART5;
SIM->SCGC1 |= SIM_SCGC1_UART5_MASK;
if(tx_pin == PTD9)
PORTD->PCR[9] = PORT_PCR_MUX(3);
else
PORTE->PCR[8] = PORT_PCR_MUX(3);
if(rx_pin == PTD8)
PORTD->PCR[8] = PORT_PCR_MUX(3);
else
PORTE->PCR[9] = PORT_PCR_MUX(3);
}
}
}
}
}
//在配置好其他寄存器前，先关闭发送器和接收器
uartx->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK );
//配置UART为 8位, 无奇偶校验 */
uartx->C1 = 0;
//计算波特率
sbr = (uint16)((sysclk)/(baud * 16));
//保存UARTx_BDH寄存器中除了SBR的值
temp = uartx->BDH & ~(UART_BDH_SBR(0x1F));
uartx->BDH = temp | UART_BDH_SBR(((sbr & 0x1F00) >> 8));
uartx->BDL = (uint8)(sbr & UART_BDL_SBR_MASK);
//配置波特率的微调分数
brfa = (((sysclk*32)/(baud * 16)) - (sbr * 32));
//保存UARTx_C4寄存器中除了BRFA的值
temp = uartx->C4 & ~(UART_C4_BRFA(0x1F));
uartx->C4 = temp | UART_C4_BRFA(brfa);
//配置发送接收中断
if(uart_init_structure.UART_RxIntEnable == TRUE && rx_isr != NULL)
{
uartx->C2 |= UART_C2_RIE_MASK;
UART_R_ISR[x] = rx_isr;
}
else
{
uartx->C2 &= ~(UART_C2_RIE_MASK);
}
if(uart_init_structure.UART_TxIntEnable == TRUE && tx_isr != NULL)
{
uartx->C2 |= UART_C2_TIE_MASK;
UART_T_ISR[x] = tx_isr;
}
else
{
uartx->C2 &= ~(UART_C2_TIE_MASK);
}
//使能发送器和接收器
uartx->C2 |= (UART_C2_TE_MASK | UART_C2_RE_MASK );
}
/* ===================================================================*/
LDD_TDeviceData* UART_A_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate device structure */
UART_A_TDeviceDataPtr DeviceDataPrv;
/* {MQXLite RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
/* Clear the receive counters and pointer */
DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */
/* Clear the transmit counters and pointer */
DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
/* Allocate interrupt vectors */
/* {MQXLite RTOS Adapter} Save old and set new interrupt vector (function handler and ISR parameter) */
/* Note: Exception handler for interrupt is not saved, because it is not modified */
DeviceDataPrv->SavedISRSettings.isrData = _int_get_isr_data(LDD_ivIndex_INT_UART3_RX_TX);
DeviceDataPrv->SavedISRSettings.isrFunction = _int_install_isr(LDD_ivIndex_INT_UART3_RX_TX, UART_A_Interrupt, DeviceDataPrv);
/* {MQXLite RTOS Adapter} Save old and set new interrupt vector (function handler and ISR parameter) */
/* Note: Exception handler for interrupt is not saved, because it is not modified */
DeviceDataPrv->SavedISRSettings.isrData = _int_get_isr_data(LDD_ivIndex_INT_UART3_ERR);
DeviceDataPrv->SavedISRSettings.isrFunction = _int_install_isr(LDD_ivIndex_INT_UART3_ERR, UART_A_Interrupt, DeviceDataPrv);
/* SIM_SCGC4: UART3=1 */
SIM_SCGC4 |= SIM_SCGC4_UART3_MASK;
/* SIM_SCGC5: PORTC=1 */
SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK;
/* PORTC_PCR16: ISF=0,MUX=3 */
PORTC_PCR16 = (uint32_t)((PORTC_PCR16 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x04)
)) | (uint32_t)(
PORT_PCR_MUX(0x03)
));
/* PORTC_PCR17: ISF=0,MUX=3 */
PORTC_PCR17 = (uint32_t)((PORTC_PCR17 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x04)
)) | (uint32_t)(
PORT_PCR_MUX(0x03)
));
/* NVICIP37: PRI37=0x70 */
NVICIP37 = NVIC_IP_PRI37(0x70);
/* NVICISER1: SETENA|=0x20 */
NVICISER1 |= NVIC_ISER_SETENA(0x20);
/* NVICIP38: PRI38=0x70 */
NVICIP38 = NVIC_IP_PRI38(0x70);
/* NVICISER1: SETENA|=0x40 */
NVICISER1 |= NVIC_ISER_SETENA(0x40);
UART_PDD_EnableTransmitter(UART3_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */
UART_PDD_EnableReceiver(UART3_BASE_PTR, PDD_DISABLE); /* Disable receiver. */
DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */
/* UART3_C1: LOOPS=0,UARTSWAI=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */
UART3_C1 = 0x00U; /* Set the C1 register */
/* UART3_C3: R8=0,T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */
UART3_C3 = 0x00U; /* Set the C3 register */
/* UART3_C4: MAEN1=0,MAEN2=0,M10=0,BRFA=0 */
UART3_C4 = UART_C4_BRFA(0x00); /* Set the C4 register */
/* UART3_S2: LBKDIF=0,RXEDGIF=0,MSBF=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */
UART3_S2 = 0x00U; /* Set the S2 register */
/* UART3_MODEM: ??=0,??=0,??=0,??=0,RXRTSE=0,TXRTSPOL=0,TXRTSE=0,TXCTSE=0 */
UART3_MODEM = 0x00U; /* Set the MODEM register */
UART_PDD_SetBaudRateFineAdjust(UART3_BASE_PTR, 18u); /* Set baud rate fine adjust */
UART_PDD_SetBaudRate(UART3_BASE_PTR, 32U); /* Set the baud rate register. */
UART_PDD_EnableFifo(UART3_BASE_PTR, (UART_PDD_TX_FIFO_ENABLE | UART_PDD_RX_FIFO_ENABLE)); /* Enable RX and TX FIFO */
UART_PDD_FlushFifo(UART3_BASE_PTR, (UART_PDD_TX_FIFO_FLUSH | UART_PDD_RX_FIFO_FLUSH)); /* Flush RX and TX FIFO */
UART_PDD_EnableTransmitter(UART3_BASE_PTR, PDD_ENABLE); /* Enable transmitter */
UART_PDD_EnableReceiver(UART3_BASE_PTR, PDD_ENABLE); /* Enable receiver */
UART_PDD_EnableInterrupt(UART3_BASE_PTR, ( UART_PDD_INTERRUPT_RECEIVER )); /* Enable interrupts */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_UART_A_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv);
}
uint_8 SCI_Init (
PSERIAL_INIT pSerialInit, /* [IN] Serial Class Initialization
Structure */
SCI_CALLBACK pfnSciCallback /* [IN] Serial Class Callback function */
)
{
/* Enable SCI, transmit and receive interrupts */
PSCI_REG pSciReg;
uint_32 baud_divisor;
uint_32 fractional_fine_adjust;
/* Enable clock source for UART0 module */
SIM_SCGC1 |= SIM_SCGC1_UART0_MASK;
/* Enable Port Muxing of Uart0 */
MXC_PTAPF1 &= ~MXC_PTAPF1_A7(0xF);
MXC_PTAPF1 |= MXC_PTAPF1_A7(0x2);
MXC_PTDPF1 &=~ MXC_PTDPF1_D6(0xF);
MXC_PTDPF1 |= MXC_PTDPF1_D6(0x2);
/* Register Application Callback */
g_serial_struct[pSerialInit->ControllerId].app_callback = pfnSciCallback;
pSciReg = g_sci_reg[pSerialInit->ControllerId];
/* Calculate baudrate divisor and fractional fine adjust values */
fractional_fine_adjust = (uint_32)(SYSTEM_CLOCK/(CONSOLE_BAUD_RATE/2));
baud_divisor = (uint_32)(fractional_fine_adjust >>5);
fractional_fine_adjust -= (baud_divisor <<5);
/* Set baudrate */
pSciReg->UART_BDH |= ((baud_divisor>>8) & UART_BDH_SBR_MASK);
pSciReg->UART_BDL = ((uint_8)(baud_divisor & 0xFF));
pSciReg->UART_C4 |= UART_C4_BRFA(fractional_fine_adjust);
/* 8 bits data, no parity */
pSciReg->UART_C1 = 0;
/* Configure Mode */
/* Default Mode is 8 bit mode */
pSciReg->UART_C1 |= ((pSerialInit->Mode == 9) ? UART_C1_M_MASK : 0) ;
if (pSerialInit->ParityEnable == TRUE)
{
pSciReg->UART_C1 |= UART_C1_PE_MASK;
if(pSerialInit->Parity == 1)
{
pSciReg->UART_C1 |= UART_C1_PT_MASK;
}
}
/* Enable Address Mark Wake Up */
pSciReg->UART_C1 |= UART_C1_WAKE_MASK;
/* Clear Status2 Register Write 1 to clear */
pSciReg->UART_S2 = UART_S2_LBKDIF_MASK | UART_S2_RXEDGIF_MASK;
pSciReg->UART_C2 = (UART_C2_TE_MASK | UART_C2_RIE_MASK | UART_C2_RE_MASK | UART_C2_TCIE_MASK |UART_C2_RWU_MASK);
pSciReg->UART_C3 = (UART_C3_PEIE_MASK | UART_C3_FEIE_MASK | UART_C3_NEIE_MASK |UART_C3_ORIE_MASK);
/* Inform the upper layer */
if(pfnSciCallback)
{
pfnSciCallback(pSerialInit->ControllerId, SCI_CONNECT, NULL);
}
return SERIAL_OK;
}
/* ===================================================================*/
LDD_TDeviceData* UART_SDA_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate device structure */
UART_SDA_TDeviceDataPtr DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
/* Clear the receive counters and pointer */
DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */
/* Clear the transmit counters and pointer */
DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
/* Allocate interrupt vectors */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_UART0_RX_TX__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_UART0_ERR__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
/* SIM_SCGC4: UART0=1 */
SIM_SCGC4 |= SIM_SCGC4_UART0_MASK;
/* SIM_SCGC5: PORTB=1 */
SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
/* PORTB_PCR16: ISF=0,MUX=3 */
PORTB_PCR16 = (uint32_t)((PORTB_PCR16 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x04)
)) | (uint32_t)(
PORT_PCR_MUX(0x03)
));
/* PORTB_PCR17: ISF=0,MUX=3 */
PORTB_PCR17 = (uint32_t)((PORTB_PCR17 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x04)
)) | (uint32_t)(
PORT_PCR_MUX(0x03)
));
/* NVICIP31: PRI31=0x70 */
NVICIP31 = NVIC_IP_PRI31(0x70);
/* NVICISER0: SETENA|=0x80000000 */
NVICISER0 |= NVIC_ISER_SETENA(0x80000000);
/* NVICIP32: PRI32=0x70 */
NVICIP32 = NVIC_IP_PRI32(0x70);
/* NVICISER1: SETENA|=1 */
NVICISER1 |= NVIC_ISER_SETENA(0x01);
UART_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */
UART_PDD_EnableReceiver(UART0_BASE_PTR, PDD_DISABLE); /* Disable receiver. */
DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */
/* UART0_C1: LOOPS=0,UARTSWAI=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */
UART0_C1 = 0x00U; /* Set the C1 register */
/* UART0_C3: R8=0,T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */
UART0_C3 = 0x00U; /* Set the C3 register */
/* UART0_C4: MAEN1=0,MAEN2=0,M10=0,BRFA=0 */
UART0_C4 = UART_C4_BRFA(0x00); /* Set the C4 register */
/* UART0_S2: LBKDIF=0,RXEDGIF=0,MSBF=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */
UART0_S2 = 0x00U; /* Set the S2 register */
/* UART0_MODEM: ??=0,??=0,??=0,??=0,RXRTSE=0,TXRTSPOL=0,TXRTSE=0,TXCTSE=0 */
UART0_MODEM = 0x00U; /* Set the MODEM register */
UART_SDA_SetClockConfiguration(DeviceDataPrv, Cpu_GetClockConfiguration()); /* Initial speed CPU mode is high */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_UART_SDA_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv);
}
