/***************************************************************************//**
* @brief
* Init USART/UART for normal asynchronous mode.
*
* @details
* This function will configure basic settings in order to operate in normal
* asynchronous mode.
*
* Special control setup not covered by this function must be done after
* using this function by direct modification of the CTRL register.
*
* Notice that pins used by the USART/UART module must be properly configured
* by the user explicitly, in order for the USART/UART to work as intended.
* (When configuring pins, one should remember to consider the sequence of
* configuration, in order to avoid unintended pulses/glitches on output
* pins.)
*
* @param[in] usart
* Pointer to USART/UART peripheral register block.
*
* @param[in] init
* Pointer to initialization structure used to configure basic async setup.
******************************************************************************/
void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init)
{
/* Make sure the module exists on the selected chip */
EFM_ASSERT(USART_REF_VALID(usart) || UART_REF_VALID(usart));
/* Init USART registers to HW reset state. */
USART_Reset(usart);
#if defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
/* Disable majority vote if specified. */
if (init->mvdis)
{
usart->CTRL |= USART_CTRL_MVDIS;
}
/* Configure PRS input mode. */
if (init->prsRxEnable)
{
usart->INPUT = (uint32_t) init->prsRxCh | USART_INPUT_RXPRS;
}
#endif
/* Configure databits, stopbits and parity */
usart->FRAME = (uint32_t) (init->databits) |
(uint32_t) (init->stopbits) |
(uint32_t) (init->parity);
/* Configure baudrate */
USART_BaudrateAsyncSet(usart, init->refFreq, init->baudrate, init->oversampling);
/* Finally enable (as specified) */
usart->CMD = (uint32_t) (init->enable);
}
/***************************************************************************//**
* @brief
* Init USART/UART for normal asynchronous mode.
*
* @details
* This function will configure basic settings in order to operate in normal
* asynchronous mode. Consider using USART_Reset() prior to this function if
* state of configuration is not known, since only configuration settings
* specified by @p init are set.
*
* Special control setup not covered by this function may be done either
* before or after using this function (but normally before enabling)
* by direct modification of the CTRL register.
*
* Notice that pins used by the USART/UART module must be properly configured
* by the user explicitly, in order for the USART/UART to work as intended.
* (When configuring pins, one should remember to consider the sequence of
* configuration, in order to avoid unintended pulses/glitches on output
* pins.)
*
* @param[in] usart
* Pointer to USART/UART peripheral register block.
*
* @param[in] init
* Pointer to initialization structure used to configure basic async setup.
******************************************************************************/
void USART_InitAsync(USART_TypeDef *usart, USART_InitAsync_TypeDef *init)
{
/* Make sure the module exists on the selected chip */
EFM_ASSERT(USART_REF_VALID(usart));
/* Ensure disabled while doing config */
/* (Mastermode disabled just in case, master mode not used for async op.) */
usart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS | USART_CMD_MASTERDIS;
/* Make sure IrDA is disabled */
usart->IRCTRL &= ~USART_IRCTRL_IREN;
/* Reset bits that should be reset for normal UART mode or reconfigured */
usart->CTRL &= ~(_USART_CTRL_SYNC_MASK |
_USART_CTRL_CLKPOL_MASK |
_USART_CTRL_CLKPHA_MASK |
_USART_CTRL_CSMA_MASK |
_USART_CTRL_SCMODE_MASK |
_USART_CTRL_SCRETRANS_MASK);
/* Configure databits, stopbits and parity */
usart->FRAME = (uint32_t)(init->databits) |
(uint32_t)(init->stopbits) |
(uint32_t)(init->parity);
/* Configure baudrate */
USART_BaudrateAsyncSet(usart, init->refFreq, init->baudrate, init->oversampling);
/* Finally enable (as specified) */
usart->CMD = (uint32_t)(init->enable);
}
static
int
usart_configure_as_uart (sBSPACMperiphUARTstate * usp,
const sBSPACMperiphUARTconfiguration * cfgp)
{
USART_TypeDef * usart;
const sBSPACMdeviceEFM32periphUARTdevcfg * devcfgp;
if (! (usp && usp->uart)) {
return -1;
}
usart = (USART_TypeDef *)usp->uart;
/* For a USART the devcfgp object is actual a
* sBSPACMdeviceEFM32periphUSARTdevcfg, but that structure simply
* extends the UART part of the configuration. */
devcfgp = (const sBSPACMdeviceEFM32periphUARTdevcfg *)usp->devcfg.ptr;
/* If enabling configuration, enable the high-frequency peripheral
* clock and the clock for the uart itself.
*
* If disabling configuration, disable the interrupts. */
if (cfgp) {
CMU_ClockEnable(cmuClock_HFPER, true);
CMU_ClockEnable(devcfgp->common.clock, true);
} else {
NVIC_DisableIRQ(devcfgp->rx_irqn);
NVIC_DisableIRQ(devcfgp->tx_irqn);
NVIC_ClearPendingIRQ(devcfgp->rx_irqn);
NVIC_ClearPendingIRQ(devcfgp->tx_irqn);
}
USART_Reset(usart);
if (usp->rx_fifo_ni_) {
fifo_reset(usp->rx_fifo_ni_);
}
if (usp->tx_fifo_ni_) {
fifo_reset(usp->tx_fifo_ni_);
}
usp->tx_state_ = 0;
if (cfgp) {
unsigned int baud_rate = cfgp->speed_baud;
if (0 == baud_rate) {
baud_rate = 115200;
}
/* Configure the USART for 8N1. Set TXBL at half-full. */
usart->FRAME = USART_FRAME_DATABITS_EIGHT | USART_FRAME_PARITY_NONE | USART_FRAME_STOPBITS_ONE;
usart->CTRL |= USART_CTRL_TXBIL_HALFFULL;
USART_BaudrateAsyncSet(usart, 0, baud_rate, usartOVS16);
CMU_ClockEnable(cmuClock_GPIO, true);
} else {
/* Done with device; turn it off */
CMU_ClockEnable(devcfgp->common.clock, false);
}
/* Enable or disable UART pins. To avoid false start, when enabling
* configure TX as high. This relies on a comment in the EMLIB code
* that manipulating registers of disabled modules has no effect
* (unlike TM4C where it causes a HardFault). We'll see. */
vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->common.rx_pinmux, !!cfgp, 1);
vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->common.tx_pinmux, !!cfgp, 0);
if (cfgp) {
usart->ROUTE = USART_ROUTE_RXPEN | USART_ROUTE_TXPEN | devcfgp->common.location;
/* Clear and enable RX interrupts. TX interrupts are enabled at the
* peripheral when there's something to transmit. TX and RX are
* enabled at the NVIC now. */
usart->IFC = _USART_IF_MASK;
usart->IEN = USART_IF_RXDATAV;
NVIC_ClearPendingIRQ(devcfgp->rx_irqn);
NVIC_ClearPendingIRQ(devcfgp->tx_irqn);
NVIC_EnableIRQ(devcfgp->rx_irqn);
NVIC_EnableIRQ(devcfgp->tx_irqn);
/* Configuration complete; enable the USART */
usart->CMD = USART_CMD_RXEN | USART_CMD_TXEN;
}
return 0;
}