/* "power up" COM by switching back to DMA interrupts */
void COM_InternalPowerUp()
{
#ifdef COM_USART0_ENABLE
USART_IntClear(USART0, USART_IF_RXDATAV);
USART_IntDisable(USART0, USART_IF_RXDATAV);
NVIC_ClearPendingIRQ( USART0_RX_IRQn );
NVIC_DisableIRQ( USART0_RX_IRQn );
#endif
#ifdef COM_USART1_ENABLE
USART_IntClear(USART1, USART_IF_RXDATAV);
USART_IntDisable(USART1, USART_IF_RXDATAV);
NVIC_ClearPendingIRQ( USART1_RX_IRQn );
NVIC_DisableIRQ( USART1_RX_IRQn );
#endif
#ifdef COM_USART2_ENABLE
USART_IntClear(USART2, USART_IF_RXDATAV);
USART_IntDisable(USART2, USART_IF_RXDATAV);
NVIC_ClearPendingIRQ( USART2_RX_IRQn );
NVIC_DisableIRQ( USART2_RX_IRQn );
#endif
if (dma_IEN!=0)
{
DMA_REG->IEN = dma_IEN;
}
}
/****************************************************************************
* void spi_enable_interrupt(spi_t *obj, uint32_t handler, uint8_t enable)
*
* This will enable the interrupt in NVIC for the associated USART RX channel
*
* * obj: pointer to spi object
* * handler: pointer to interrupt handler for this channel
* * enable: Whether to enable (true) or disable (false) the interrupt
*
****************************************************************************/
void spi_enable_interrupt(spi_t *obj, uint32_t handler, uint8_t enable)
{
IRQn_Type IRQvector;
switch ((uint32_t)obj->spi.spi) {
#ifdef USART0
case USART_0:
IRQvector = USART0_RX_IRQn;
break;
#endif
#ifdef USART1
case USART_1:
IRQvector = USART1_RX_IRQn;
break;
#endif
#ifdef USART2
case USART_2:
IRQvector = USART2_RX_IRQn;
break;
#endif
default:
error("Undefined SPI peripheral");
return;
}
if (enable == true) {
vIRQ_SetVector(IRQvector, handler);
USART_IntEnable(obj->spi.spi, USART_IEN_RXDATAV);
vIRQ_EnableIRQ(IRQvector);
} else {
vIRQ_SetVector(IRQvector, handler);
USART_IntDisable(obj->spi.spi, USART_IEN_RXDATAV);
vIRQ_DisableIRQ(IRQvector);
}
}
static void uart_gecko_irq_rx_disable(struct device *dev)
{
const struct uart_gecko_config *config = dev->config->config_info;
u32_t mask = USART_IEN_RXDATAV;
USART_IntDisable(config->base, mask);
}
static void uart_gecko_irq_err_disable(struct device *dev)
{
const struct uart_gecko_config *config = dev->config->config_info;
USART_IntDisable(config->base, USART_IF_RXOF |
USART_IF_PERR |
USART_IF_FERR);
}
void UART_1_TX_ISR(void)
{
/* Check TX buffer level status */
if(UART_1_DEV->STATUS & UART_STATUS_TXBL) {
int data = ringbuffer_get_one(&rb_uart1);
if(-1 != data) {
/* Write data to buffer */
UART_1_DEV->TXDATA = (uint32_t)data;
} else {
USART_IntDisable(UART_1_DEV, USART_IF_TXBL);
}
}
if(sched_context_switch_request) {
thread_yield();
}
}
/**************************************************************************//**
* @brief USART1 TX IRQ Handler
*
* Set up the interrupt prior to use
*
*****************************************************************************/
void USART1_TX_IRQHandler(void)
{
/* Check TX buffer level status */
if (uart->STATUS & USART_STATUS_TXBL)
{
if (txBuf.pendingBytes > 0)
{
/* Transmit pending character */
USART_Tx(uart, txBuf.data[txBuf.rdI]);
txBuf.rdI = (txBuf.rdI + 1) % BUFFERSIZE;
txBuf.pendingBytes--;
}
/* Disable Tx interrupt if no more bytes in queue */
if (txBuf.pendingBytes == 0)
{
USART_IntDisable(uart, USART_IF_TXBL);
}
}
}