//! (HCS12) Writes one byte to the BDM address space
//!
//! @param address 16-bit memory address
//! @param data 8-bit data value
//!
//! @return 0 => Success,\n !=0 => Fail
//!
//! @note Access to Control register addres is mapped to USBDM_WriteControlReg()
//!
TBDML_API unsigned char _tbdml_write_bd(unsigned int address, unsigned char data) {
if (address == HC12_BDMSTS)
return USBDM_WriteControlReg(data);
else
return USBDM_WriteDReg(address, data);
}
//! 2.2.6.1 Write Value to Register
//!
//! @param dnRegNumber
//! @param drvValue
//!
USBDM_GDI_API
DiReturnT DiRegisterWrite ( DiUInt32T dnRegNumber,
DiRegisterValueT drvValue ) {
LOGGING;
U32c value(drvValue);
USBDM_ErrorCode rc = BDM_RC_OK;
// Logging::print("DiRegisterWrite(0x%X(%d) <= 0x%08X)\n", dnRegNumber, dnRegNumber, (uint32_t)value);
CHECK_ERROR_STATE();
if (dnRegNumber>cfv234regID_FIRST_DEBUG_REG) {
dnRegNumber -= cfv234regID_FIRST_DEBUG_REG;
Logging::print("DiRegisterWriteD(0x%X(%s) <= 0x%08X)\n", dnRegNumber, getCFVxDebugRegName(dnRegNumber), (uint32_t)value);
rc = USBDM_WriteDReg(dnRegNumber,value);
}
else if (dnRegNumber > cfv234regID_FIRST_CONTROL_REG) {
dnRegNumber -= cfv234regID_FIRST_CONTROL_REG;
Logging::print("DiRegisterWriteC(0x%X(%s) <= 0x%08X)\n", dnRegNumber, getCFVxControlRegName(dnRegNumber), (uint32_t)value);
rc = USBDM_WriteCReg(dnRegNumber,value);
}
else {
switch (dnRegNumber) {
case cfv234regID_pc :
Logging::print("DiRegisterWrite(0x%X(%s) <= 0x%08X)\n", CFVx_CRegPC, getCFVxControlRegName(CFVx_CRegPC), (uint32_t)value);
rc = USBDM_WriteCReg(CFVx_CRegPC,value);
break;
case cfv234regID_sr :
Logging::print("DiRegisterWrite(0x%X(%s) <= 0x%08X)\n", CFVx_CRegSR, getCFVxControlRegName(CFVx_CRegSR), (uint32_t)value);
rc = USBDM_WriteCReg(CFVx_CRegSR,value);
break;
default : // D0-7, A0-7
if (dnRegNumber<=cfv234regID_a7) {
Logging::print("DiRegisterWrite(0x%X(%s) <= 0x%08X)\n", dnRegNumber, getCFVxRegName(dnRegNumber), (uint32_t)value);
rc = USBDM_WriteReg(dnRegNumber,value);
}
else {
Logging::print("DiRegisterWrite(illegal reg# = 0x%X (%d)\n", dnRegNumber, dnRegNumber);
rc = BDM_RC_ILLEGAL_PARAMS;
}
break;
}
}
if (rc != BDM_RC_OK) {
// Logging::error("DiRegisterWrite(0x%X,%s) Failed, reason= %s\n",
// dnRegNumber, DSC_GetRegisterName(regNum), USBDM_GetErrorString(rc));
return setErrorState(DI_ERR_NONFATAL, rc);
}
return setErrorState(DI_OK);
}
//! De-activate breakpoints. \n
//! This may involve changing target code for RAM breakpoints or
//! modifying target breakpoint hardware.
//!
void deactivateBreakpoints(void) {
print("deactivateBreakpoints()\n");
memoryBreakInfo *bpPtr;
if (!breakpointsActive)
return;
for (bpPtr = memoryBreakpoints;
bpPtr < memoryBreakpoints+MAX_MEMORY_BREAKPOINTS;
bpPtr++) {
if (bpPtr->inUse) {
print("deactivateBreakpoints(MEM@%08X)\n", bpPtr->address);
USBDM_WriteMemory(2,2,bpPtr->address,bpPtr->opcode);
}
}
USBDM_WriteDReg(CFV1_DRegTDR, TDR_DISABLE);
breakpointsActive = false;
}
//! (CFv1) Write Debug register
//!
//! @param regNo Register #
//! @param value 32-bit value
//!
OSBDM_API void _opensourcebdm_write_dreg(unsigned char regNo, unsigned int value) {
#ifdef MC51AC_HACK
if ((targetType == T_CFV1) && (regNo == CFV1_DRegCSR)) {
// MCF51AC Hack
print("_opensourcebdm_write_dreg() - hacking CSR value\n", value);
value |= CFV1_CSR_VBD;
}
#endif
if (regNo>31) {// debugger tries to write to illegal registers !
print("_opensourcebdm_write_dreg(%d,%X) - illegal register\r\n", regNo, value);
return;
}
USBDM_WriteDReg(regNo, value);
}
//! (HCS12 & HCS08) Writes CCR
//!
//! @param value 8-bit value
//!
TBDML_API void _tbdml_write_reg_ccr(unsigned int value) {
USBDM_WriteDReg(0xFF06,value);
}
//! 2.2.6.1 Write Value to Register
//!
//! @param dnRegNumber
//! @param drvValue
//!
USBDM_GDI_DECLSPEC
DiReturnT DiRegisterWrite ( DiUInt32T dnRegNumber,
DiRegisterValueT drvValue ) {
LOGGING;
U32c value(drvValue);
USBDM_ErrorCode rc = BDM_RC_OK;
log.print("(0x%X(%d) <= 0x%08X)\n", dnRegNumber, dnRegNumber, (uint32_t)value);
CHECK_ERROR_STATE();
if (dnRegNumber>cfv1regID_FIRST_DEBUG_regID_BYTE) {
switch (dnRegNumber) {
case cfv1regID_xcsr_byte :
rc = USBDM_WriteControlReg(value);
if (rc != BDM_RC_OK) {
log.print("DiRegisterWrite(%s(0x%X)) Failed, reason= %s\n",
"XCSR.byte", dnRegNumber, USBDM_GetErrorString(rc));
return setErrorState(DI_ERR_NONFATAL, rc);
}
break;
case cfv1regID_csr2_byte :
rc = USBDM_WriteDReg(CFV1_DRegCSR2byte,value);
if (rc != BDM_RC_OK) {
log.print("DiRegisterWrite(%s(0x%X)) Failed, reason= %s\n",
"CSR2.byte", dnRegNumber, USBDM_GetErrorString(rc));
return setErrorState(DI_ERR_NONFATAL, rc);
}
break;
case cfv1regID_csr3_byte :
rc = USBDM_WriteDReg(CFV1_DRegCSR3byte,value);
if (rc != BDM_RC_OK) {
log.print("DiRegisterWrite(%s(0x%X)) Failed, reason= %s\n",
"CSR3.byte", dnRegNumber, USBDM_GetErrorString(rc));
return setErrorState(DI_ERR_NONFATAL, rc);
}
break;
default :
log.print("DiRegisterWrite(Illegal Reg# 0x%X(%d)\n", dnRegNumber, dnRegNumber);
rc = BDM_RC_ILLEGAL_PARAMS;
break;
}
}
else if (dnRegNumber>cfv1regID_FIRST_DEBUG_REG) {
int regNum = dnRegNumber-cfv1regID_FIRST_DEBUG_REG;
rc = USBDM_WriteDReg(regNum,value);
if (rc != BDM_RC_OK) {
log.print("DiRegisterWrite(%s(0x%X)) Failed, reason= %s\n",
getCFV1DebugRegName(regNum), dnRegNumber, USBDM_GetErrorString(rc));
return setErrorState(DI_ERR_NONFATAL, rc);
}
}
else if (dnRegNumber > cfv1regID_FIRST_CONTROL_REG) {
int regNum = dnRegNumber-cfv1regID_FIRST_CONTROL_REG;
rc = USBDM_WriteCReg(regNum,value);
if (rc != BDM_RC_OK) {
log.print("DiRegisterWrite(%s(0x%X)) Failed, reason= %s\n",
getCFV1ControlRegName(regNum), dnRegNumber, USBDM_GetErrorString(rc));
return setErrorState(DI_ERR_NONFATAL, rc);
}
}
else {
switch (dnRegNumber) {
case cfv1regID_pc : /* PC */
if (!pcWritten) {
log.print("Saving initial PC write = 0x%08X)\n", (uint32_t)value);
pcWritten = true;
pcResetValue = value;
}
rc = USBDM_WriteCReg(CFV1_CRegPC,value);
if (rc != BDM_RC_OK) {
log.print("DiRegisterWrite(%s(0x%X)) Failed, reason= %s\n",
"PC", dnRegNumber, USBDM_GetErrorString(rc));
return setErrorState(DI_ERR_NONFATAL, rc);
}
break;
case cfv1regID_sr :
rc = USBDM_WriteCReg(CFV1_CRegSR,value);
if (rc != BDM_RC_OK) {
log.print("DiRegisterWrite(%s(0x%X)) Failed, reason= %s\n",
"SR", dnRegNumber, USBDM_GetErrorString(rc));
return setErrorState(DI_ERR_NONFATAL, rc);
}
break;
default : // D0-7, A0-7
if (dnRegNumber>15) {
log.print("DiRegisterWrite(Illegal Reg# 0x%X(%d)\n", dnRegNumber, dnRegNumber);
rc = BDM_RC_ILLEGAL_PARAMS;
}
else {
rc = USBDM_WriteReg(dnRegNumber,value);
if (rc != BDM_RC_OK) {
log.print("DiRegisterWrite(%s(0x%X)) Failed, reason= %s\n",
getCFV1RegName(dnRegNumber), dnRegNumber, USBDM_GetErrorString(rc));
return setErrorState(DI_ERR_NONFATAL, rc);
}
}
break;
}
}
if (rc != BDM_RC_OK) {
log.error("0x%X Failed, reason= %s\n",
dnRegNumber, USBDM_GetErrorString(rc));
return setErrorState(DI_ERR_NONFATAL, rc);
}
return setErrorState(DI_OK);
}
//! Activate breakpoints. \n
//! This may involve changing target code for RAM breakpoints or
//! modifying target breakpoint hardware
//!
void activateBreakpoints(void) {
print("activateBreakpoints()\n");
static const uint8_t haltOpcode[] = {0x4a, 0xc8};
memoryBreakInfo *bpPtr;
if (breakpointsActive)
return;
for (bpPtr = memoryBreakpoints;
bpPtr < memoryBreakpoints+MAX_MEMORY_BREAKPOINTS;
bpPtr++) {
if (bpPtr->inUse) {
print("activateBreakpoints(%s@%08X)\n", getBreakpointName(memoryBreak), bpPtr->address);
USBDM_ReadMemory(2,2,bpPtr->address,bpPtr->opcode);
USBDM_WriteMemory(2,2,bpPtr->address,haltOpcode);
breakpointsActive = true;
}
}
uint32_t tdrValue = TDR_DISABLE;
if (hardwareBreakpoints[0].inUse) {
tdrValue |= TDR_TRC_HALT|TDR_L1T|TDR_L1EBL|TDR_L1EPC;
USBDM_WriteDReg(CFVx_DRegPBR0, hardwareBreakpoints[0].address&~0x1);
USBDM_WriteDReg(CFVx_DRegPBMR, 0x00000000);
breakpointsActive = true;
print("activateBreakpoints(%s@%08X)\n", getBreakpointName(hardBreak),
hardwareBreakpoints[0].address&~0x1);
}
if (hardwareBreakpoints[1].inUse) {
tdrValue |= TDR_TRC_HALT|TDR_L1T|TDR_L1EBL|TDR_L1EPC;
USBDM_WriteDReg(CFVx_DRegPBR1, hardwareBreakpoints[1].address|0x1);
breakpointsActive = true;
print("activateBreakpoints(%s@%08X)\n", getBreakpointName(hardBreak),
hardwareBreakpoints[1].address&~0x1);
}
else {
USBDM_WriteDReg(CFVx_DRegPBR1,0);
}
if (hardwareBreakpoints[2].inUse) {
tdrValue |= TDR_TRC_HALT|TDR_L1T|TDR_L1EBL|TDR_L1EPC;
USBDM_WriteDReg(CFVx_DRegPBR2, hardwareBreakpoints[2].address|0x1);
breakpointsActive = true;
print("activateBreakpoints(%s@%08X)\n", getBreakpointName(hardBreak),
hardwareBreakpoints[2].address&~0x1);
}
else {
USBDM_WriteDReg(CFVx_DRegPBR2,0);
}
if (hardwareBreakpoints[3].inUse) {
tdrValue |= TDR_TRC_HALT|TDR_L1T|TDR_L1EBL|TDR_L1EPC;
USBDM_WriteDReg(CFVx_DRegPBR3, hardwareBreakpoints[3].address|0x1);
breakpointsActive = true;
print("activateBreakpoints(%s@%08X)\n", getBreakpointName(hardBreak),
hardwareBreakpoints[3].address&~0x1);
}
else {
USBDM_WriteDReg(CFV1_DRegPBR3,0);
}
if (dataWatchPoints[0].inUse) {
tdrValue |= TDR_TRC_HALT|TDR_L1T|TDR_L1EBL|TDR_L1EA_INC;
USBDM_WriteDReg(CFVx_DRegABLR, dataWatchPoints[0].address);
USBDM_WriteDReg(CFVx_DRegABHR, dataWatchPoints[0].address+dataWatchPoints[0].size-1);
breakpointsActive = true;
}
USBDM_WriteDReg(CFVx_DRegTDR, tdrValue);
}
//! (CFv1) Write CSR3.msb
//!
//! @param value 8-bit number
//!
OSBDM_API void _opensourcebdm_write_csr3_byte(unsigned char value) {
USBDM_WriteDReg(CFV1_DRegCSR3byte,value);
return;
}
//! (HCS08 & RS08) Write to Breakpoint Register
//!
//! @param value 16-bit value
//!
OSBDM_API void _opensourcebdm_write_bkpt(unsigned int value){
USBDM_WriteDReg(0, value);
}
