/** * @brief USB_OTG_USBH_handle_rx_qlvl_ISR * Handles the Rx Status Queue Level Interrupt * @param pdev: Selected device * @retval status */ #if defined ( __ICCARM__ ) /*!< IAR Compiler */ #pragma optimize = none #endif /* __CC_ARM */ static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR (USB_OTG_CORE_HANDLE *pdev) { USB_OTG_GRXFSTS_TypeDef grxsts; USB_OTG_GINTMSK_TypeDef intmsk; USB_OTG_HCTSIZn_TypeDef hctsiz; USB_OTG_HCCHAR_TypeDef hcchar; __IO uint8_t channelnum =0; uint32_t count; /* Disable the Rx Status Queue Level interrupt */ intmsk.d32 = 0; intmsk.b.rxstsqlvl = 1; USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0); grxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRXSTSP); channelnum = grxsts.b.chnum; hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[channelnum]->HCCHAR); switch (grxsts.b.pktsts) { case GRXSTS_PKTSTS_IN: /* Read the data into the host buffer. */ #ifdef USE_HOST_MODE if ((grxsts.b.bcnt > 0) && (pdev->host.hc[channelnum].xfer_buff != (void *)0)) { USB_OTG_ReadPacket(pdev, pdev->host.hc[channelnum].xfer_buff, grxsts.b.bcnt); /*manage multiple Xfer */ pdev->host.hc[grxsts.b.chnum].xfer_buff += grxsts.b.bcnt; pdev->host.hc[grxsts.b.chnum].xfer_count += grxsts.b.bcnt; count = pdev->host.hc[channelnum].xfer_count; pdev->host.XferCnt[channelnum] = count; hctsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[channelnum]->HCTSIZ); if(hctsiz.b.pktcnt > 0) { /* re-activate the channel when more packets are expected */ hcchar.b.chen = 1; hcchar.b.chdis = 0; USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[channelnum]->HCCHAR, hcchar.d32); } } #endif break; case GRXSTS_PKTSTS_IN_XFER_COMP: case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: case GRXSTS_PKTSTS_CH_HALTED: default: break; } /* Enable the Rx Status Queue Level interrupt */ intmsk.b.rxstsqlvl = 1; USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); return 1; }
/** * @brief DCD_HandleRxStatusQueueLevel_ISR * Handles the Rx Status Queue Level Interrupt * @param pdev: device instance * @retval status */ static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev) { USB_OTG_GINTMSK_TypeDef int_mask; USB_OTG_DRXSTS_TypeDef status; USB_OTG_EP *ep; /* Disable the Rx Status Queue Level interrupt */ int_mask.d32 = 0; int_mask.b.rxstsqlvl = 1; USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32, 0); /* Get the Status from the top of the FIFO */ status.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRXSTSP ); ep = &pdev->dev.out_ep[status.b.epnum]; switch (status.b.pktsts) { case STS_GOUT_NAK: break; case STS_DATA_UPDT: if (status.b.bcnt) { USB_OTG_ReadPacket(pdev,ep->xfer_buff, status.b.bcnt); ep->xfer_buff += status.b.bcnt; ep->xfer_count += status.b.bcnt; } break; case STS_XFER_COMP: break; case STS_SETUP_COMP: break; case STS_SETUP_UPDT: /* Copy the setup packet received in FIFO into the setup buffer in RAM */ USB_OTG_ReadPacket(pdev , pdev->dev.setup_packet, 8); ep->xfer_count += status.b.bcnt; break; default: break; } /* Enable the Rx Status Queue Level interrupt */ USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, int_mask.d32); return 1; }