Std_ReturnType Stmo_SetPosDegree(Stmo_IdType Id,Stmo_DegreeType Degree)
{
Std_ReturnType ercd = E_NOT_OK;
VALIDATE_ID(Id,Stmo_SetPosDegree);
if(Degree <= STMO_MAX_DEGREE)
{
StmoCtrl[Id].Command = Degree+GET_STMO_SOFTWARE_ZERO(Id);
ercd = E_OK;
}
cleanup:
return ercd;
}
/* Thresholds for scaling are specified in % of fifo freeness.
* If threshold_low is specified as 20%, it means when the fifo free
* between 0 to 20%, use la as programmed_la.
* If threshold_mid is specified as 50%, it means when the fifo free
* between 20 to 50%, use la as programmed_la/2 .
* If threshold_high is specified as 80%, it means when the fifo free
* between 50 to 80%, use la as programmed_la/4.
* When the fifo is free between 80 to 100%, use la as 0(highest priority).
*/
int t3_enable_la_scaling(enum tegra_la_id id,
unsigned int threshold_low,
unsigned int threshold_mid,
unsigned int threshold_high)
{
unsigned long reg;
void __iomem *scaling_enable_reg =
(void __iomem *)(T3_MC_RA(ARB_OVERRIDE));
int idx = cs->id_to_index[id];
VALIDATE_ID(id, cs);
VALIDATE_THRESHOLDS(threshold_low, threshold_mid, threshold_high);
if (cs->la_info_array[idx].scaling_supported == false)
goto exit;
spin_lock(&cs->lock);
la_debug("\n%s: id=%d, tl=%d, tm=%d, th=%d", __func__,
id, threshold_low, threshold_mid, threshold_high);
cs->scaling_info[idx].threshold_low = threshold_low;
cs->scaling_info[idx].threshold_mid = threshold_mid;
cs->scaling_info[idx].threshold_high = threshold_high;
cs->scaling_info[idx].scaling_ref_count++;
if (id >= ID(DISPLAY_0A) && id <= ID(DISPLAY_1BB))
set_disp_latency_thresholds(id);
else if (id >= ID(VI_WSB) && id <= ID(VI_WY))
set_vi_latency_thresholds(id);
if (!cs->la_scaling_enable_count++) {
reg = readl(scaling_enable_reg);
reg |= (1 << GLOBAL_LATENCY_SCALING_ENABLE_BIT);
writel(reg, scaling_enable_reg);
la_debug("enabled scaling.");
}
spin_unlock(&cs->lock);
exit:
return 0;
}
