static struct pipe_sampler_view *etna_pipe_create_sampler_view(struct pipe_context *pipe,
struct pipe_resource *texture,
const struct pipe_sampler_view *templat)
{
struct etna_pipe_context *priv = etna_pipe_context(pipe);
struct etna_sampler_view *sv = CALLOC_STRUCT(etna_sampler_view);
sv->base = *templat;
sv->base.context = pipe;
sv->base.texture = 0;
pipe_resource_reference(&sv->base.texture, texture);
sv->base.texture = texture;
assert(sv->base.texture);
struct compiled_sampler_view *cs = CALLOC_STRUCT(compiled_sampler_view);
struct etna_resource *res = etna_resource(sv->base.texture);
assert(res != NULL);
cs->TE_SAMPLER_CONFIG0 =
VIVS_TE_SAMPLER_CONFIG0_TYPE(translate_texture_target(res->base.target, false)) |
VIVS_TE_SAMPLER_CONFIG0_FORMAT(translate_texture_format(sv->base.format, false));
/* merged with sampler state */
cs->TE_SAMPLER_CONFIG0_MASK = 0xffffffff;
cs->TE_SAMPLER_CONFIG1 =
VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R(templat->swizzle_r) |
VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G(templat->swizzle_g) |
VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B(templat->swizzle_b) |
VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A(templat->swizzle_a) |
VIVS_TE_SAMPLER_CONFIG1_HALIGN(res->halign);
cs->TE_SAMPLER_SIZE =
VIVS_TE_SAMPLER_SIZE_WIDTH(res->base.width0)|
VIVS_TE_SAMPLER_SIZE_HEIGHT(res->base.height0);
cs->TE_SAMPLER_LOG_SIZE =
VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(etna_log2_fixp55(res->base.width0)) |
VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(etna_log2_fixp55(res->base.height0));
/* Set up levels-of-detail */
for(int lod=0; lod<=res->base.last_level; ++lod)
{
cs->TE_SAMPLER_LOD_ADDR[lod] = etna_bo_gpu_address(res->bo) + res->levels[lod].offset;
}
cs->min_lod = sv->base.u.tex.first_level << 5;
cs->max_lod = MIN2(sv->base.u.tex.last_level, res->base.last_level) << 5;
/* Workaround for npot textures -- it appears that only CLAMP_TO_EDGE is supported when the
* appropriate capability is not set. */
if(!priv->specs.npot_tex_any_wrap &&
(!util_is_power_of_two(res->base.width0) || !util_is_power_of_two(res->base.height0)))
{
cs->TE_SAMPLER_CONFIG0_MASK = ~(VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK |
VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK);
cs->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_UWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE) |
VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE);
}
sv->internal = cs;
pipe_reference_init(&sv->base.reference, 1);
return &sv->base;
}
static struct pipe_sampler_view *etna_pipe_create_sampler_view(struct pipe_context *pipe,
struct pipe_resource *texture,
const struct pipe_sampler_view *templat)
{
//struct etna_pipe_context *priv = etna_pipe_context(pipe);
struct etna_sampler_view *sv = CALLOC_STRUCT(etna_sampler_view);
sv->base = *templat;
sv->base.context = pipe;
sv->base.texture = 0;
pipe_resource_reference(&sv->base.texture, texture);
sv->base.texture = texture;
assert(sv->base.texture);
struct compiled_sampler_view *cs = CALLOC_STRUCT(compiled_sampler_view);
struct etna_resource *res = etna_resource(sv->base.texture);
assert(res != NULL);
cs->TE_SAMPLER_CONFIG0 =
VIVS_TE_SAMPLER_CONFIG0_TYPE(translate_texture_target(res->base.target, false)) |
VIVS_TE_SAMPLER_CONFIG0_FORMAT(translate_texture_format(sv->base.format, false));
/* merged with sampler state */
cs->TE_SAMPLER_CONFIG1 =
VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R(templat->swizzle_r) |
VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G(templat->swizzle_g) |
VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B(templat->swizzle_b) |
VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A(templat->swizzle_a) |
VIVS_TE_SAMPLER_CONFIG1_HALIGN(res->halign);
cs->TE_SAMPLER_SIZE =
VIVS_TE_SAMPLER_SIZE_WIDTH(res->base.width0)|
VIVS_TE_SAMPLER_SIZE_HEIGHT(res->base.height0);
cs->TE_SAMPLER_LOG_SIZE =
VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(log2_fixp55(res->base.width0)) |
VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(log2_fixp55(res->base.height0));
/* XXX in principle we only have to define lods sv->first_level .. sv->last_level */
for(int lod=0; lod<=res->base.last_level; ++lod)
{
cs->TE_SAMPLER_LOD_ADDR[lod] = res->levels[lod].address;
}
cs->min_lod = sv->base.u.tex.first_level << 5;
cs->max_lod = MIN2(sv->base.u.tex.last_level, res->base.last_level) << 5;
sv->internal = cs;
pipe_reference_init(&sv->base.reference, 1);
return &sv->base;
}
static struct pipe_sampler_view *
etna_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc,
const struct pipe_sampler_view *so)
{
struct etna_sampler_view *sv = CALLOC_STRUCT(etna_sampler_view);
struct etna_resource *res = etna_resource(prsc);
struct etna_context *ctx = etna_context(pctx);
const uint32_t format = translate_texture_format(so->format);
const bool ext = !!(format & EXT_FORMAT);
const uint32_t swiz = get_texture_swiz(so->format, so->swizzle_r,
so->swizzle_g, so->swizzle_b,
so->swizzle_a);
if (!sv)
return NULL;
if (!etna_resource_sampler_compatible(res)) {
/* The original resource is not compatible with the sampler.
* Allocate an appropriately tiled texture. */
if (!res->texture) {
struct pipe_resource templat = *prsc;
templat.bind &= ~(PIPE_BIND_DEPTH_STENCIL | PIPE_BIND_RENDER_TARGET |
PIPE_BIND_BLENDABLE);
res->texture =
etna_resource_alloc(pctx->screen, ETNA_LAYOUT_TILED,
DRM_FORMAT_MOD_LINEAR, &templat);
}
if (!res->texture) {
free(sv);
return NULL;
}
res = etna_resource(res->texture);
}
sv->base = *so;
pipe_reference_init(&sv->base.reference, 1);
sv->base.texture = NULL;
pipe_resource_reference(&sv->base.texture, prsc);
sv->base.context = pctx;
/* merged with sampler state */
sv->TE_SAMPLER_CONFIG0 = COND(!ext, VIVS_TE_SAMPLER_CONFIG0_FORMAT(format));
sv->TE_SAMPLER_CONFIG0_MASK = 0xffffffff;
switch (sv->base.target) {
case PIPE_TEXTURE_1D:
/* For 1D textures, we will have a height of 1, so we can use 2D
* but set T wrap to repeat */
sv->TE_SAMPLER_CONFIG0_MASK = ~VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK;
sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_REPEAT);
/* fallthrough */
case PIPE_TEXTURE_2D:
case PIPE_TEXTURE_RECT:
sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_2D);
break;
case PIPE_TEXTURE_CUBE:
sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_CUBE_MAP);
break;
default:
BUG("Unhandled texture target");
free(sv);
return NULL;
}
sv->TE_SAMPLER_CONFIG1 = COND(ext, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(format)) |
VIVS_TE_SAMPLER_CONFIG1_HALIGN(res->halign) | swiz;
sv->TE_SAMPLER_SIZE = VIVS_TE_SAMPLER_SIZE_WIDTH(res->base.width0) |
VIVS_TE_SAMPLER_SIZE_HEIGHT(res->base.height0);
sv->TE_SAMPLER_LOG_SIZE =
VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(etna_log2_fixp55(res->base.width0)) |
VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(etna_log2_fixp55(res->base.height0));
/* Set up levels-of-detail */
for (int lod = 0; lod <= res->base.last_level; ++lod) {
sv->TE_SAMPLER_LOD_ADDR[lod].bo = res->bo;
sv->TE_SAMPLER_LOD_ADDR[lod].offset = res->levels[lod].offset;
sv->TE_SAMPLER_LOD_ADDR[lod].flags = ETNA_RELOC_READ;
}
sv->min_lod = sv->base.u.tex.first_level << 5;
sv->max_lod = MIN2(sv->base.u.tex.last_level, res->base.last_level) << 5;
/* Workaround for npot textures -- it appears that only CLAMP_TO_EDGE is
* supported when the appropriate capability is not set. */
if (!ctx->specs.npot_tex_any_wrap &&
(!util_is_power_of_two(res->base.width0) || !util_is_power_of_two(res->base.height0))) {
sv->TE_SAMPLER_CONFIG0_MASK = ~(VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK |
VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK);
sv->TE_SAMPLER_CONFIG0 |=
VIVS_TE_SAMPLER_CONFIG0_UWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE) |
VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE);
}
return &sv->base;
}
