static const VMStateDescription vmstate_ISAIPMIBTDevice = { .name = TYPE_IPMI_INTERFACE, .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_BOOL(bt.obf_irq_set, ISAIPMIBTDevice), VMSTATE_BOOL(bt.atn_irq_set, ISAIPMIBTDevice), VMSTATE_BOOL(bt.use_irq, ISAIPMIBTDevice), VMSTATE_BOOL(bt.irqs_enabled, ISAIPMIBTDevice), VMSTATE_UINT32(bt.outpos, ISAIPMIBTDevice), VMSTATE_VBUFFER_UINT32(bt.outmsg, ISAIPMIBTDevice, 1, NULL, 0, bt.outlen), VMSTATE_VBUFFER_UINT32(bt.inmsg, ISAIPMIBTDevice, 1, NULL, 0, bt.inlen), VMSTATE_UINT8(bt.control_reg, ISAIPMIBTDevice), VMSTATE_UINT8(bt.mask_reg, ISAIPMIBTDevice), VMSTATE_UINT8(bt.waiting_rsp, ISAIPMIBTDevice), VMSTATE_UINT8(bt.waiting_seq, ISAIPMIBTDevice), VMSTATE_END_OF_LIST() } }; static void isa_ipmi_bt_init(Object *obj) { ISAIPMIBTDevice *iib = ISA_IPMI_BT(obj); ipmi_bmc_find_and_link(obj, (Object **) &iib->bt.bmc); vmstate_register(NULL, 0, &vmstate_ISAIPMIBTDevice, iib); }
rtc_coalesced_timer_update(s); } } #endif return 0; } static const VMStateDescription vmstate_rtc = { .name = "mc146818rtc", .version_id = 3, .minimum_version_id = 1, .minimum_version_id_old = 1, .post_load = rtc_post_load, .fields = (VMStateField []) { VMSTATE_BUFFER(cmos_data, RTCState), VMSTATE_UINT8(cmos_index, RTCState), VMSTATE_UNUSED(7*4), VMSTATE_TIMER(periodic_timer, RTCState), VMSTATE_INT64(next_periodic_time, RTCState), VMSTATE_UNUSED(3*8), VMSTATE_UINT32_V(irq_coalesced, RTCState, 2), VMSTATE_UINT32_V(period, RTCState, 2), VMSTATE_UINT64_V(base_rtc, RTCState, 3), VMSTATE_UINT64_V(last_update, RTCState, 3), VMSTATE_INT64_V(offset, RTCState, 3), VMSTATE_TIMER_V(update_timer, RTCState, 3), VMSTATE_UINT64_V(next_alarm_time, RTCState, 3), VMSTATE_END_OF_LIST() } };
PCIVPBState *s = opaque; pci_vpb_update_all_windows(s); return 0; } static const VMStateDescription pci_vpb_vmstate = { .name = "versatile-pci", .version_id = 1, .minimum_version_id = 1, .post_load = pci_vpb_post_load, .fields = (VMStateField[]) { VMSTATE_UINT32_ARRAY(imap, PCIVPBState, 3), VMSTATE_UINT32_ARRAY(smap, PCIVPBState, 3), VMSTATE_UINT32(selfid, PCIVPBState), VMSTATE_UINT32(flags, PCIVPBState), VMSTATE_UINT8(irq_mapping, PCIVPBState), VMSTATE_END_OF_LIST() } }; #define TYPE_VERSATILE_PCI "versatile_pci" #define PCI_VPB(obj) \ OBJECT_CHECK(PCIVPBState, (obj), TYPE_VERSATILE_PCI) #define TYPE_VERSATILE_PCI_HOST "versatile_pci_host" #define PCI_VPB_HOST(obj) \ OBJECT_CHECK(PCIDevice, (obj), TYPE_VERSATILE_PCIHOST) typedef enum { PCI_IMAP0 = 0x0, PCI_IMAP1 = 0x4,
static void kbd_reset(void *opaque) { KBDState *s = opaque; s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT; s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED; } static const VMStateDescription vmstate_kbd = { .name = "pckbd", .version_id = 3, .minimum_version_id = 3, .minimum_version_id_old = 3, .fields = (VMStateField []) { VMSTATE_UINT8(write_cmd, KBDState), VMSTATE_UINT8(status, KBDState), VMSTATE_UINT8(mode, KBDState), VMSTATE_UINT8(pending, KBDState), VMSTATE_END_OF_LIST() } }; /* Memory mapped interface */ static uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr) { KBDState *s = opaque; if (addr & s->mask) return kbd_read_status(s, 0) & 0xff; else
} static const VMStateDescription vmstate_tcx = { .name ="tcx", .version_id = 4, .minimum_version_id = 4, .minimum_version_id_old = 4, .post_load = vmstate_tcx_post_load, .fields = (VMStateField []) { VMSTATE_UINT16(height, TCXState), VMSTATE_UINT16(width, TCXState), VMSTATE_UINT16(depth, TCXState), VMSTATE_BUFFER(r, TCXState), VMSTATE_BUFFER(g, TCXState), VMSTATE_BUFFER(b, TCXState), VMSTATE_UINT8(dac_index, TCXState), VMSTATE_UINT8(dac_state, TCXState), VMSTATE_END_OF_LIST() } }; static void tcx_reset(DeviceState *d) { TCXState *s = container_of(d, TCXState, busdev.qdev); /* Initialize palette */ memset(s->r, 0, 256); memset(s->g, 0, 256); memset(s->b, 0, 256); s->r[255] = s->g[255] = s->b[255] = 255; update_palette_entries(s, 0, 256);
qdev_prop_set_uint32(dev, "elcr_addr", master ? 0x4d0 : 0x4d1); qdev_prop_set_uint8(dev, "elcr_mask", master ? 0xf8 : 0xde); qdev_prop_set_bit(dev, "master", master); qdev_init_nofail(dev); return isadev; } static const VMStateDescription vmstate_pic_common = { .name = "i8259", .version_id = 1, .minimum_version_id = 1, .pre_save = pic_dispatch_pre_save, .post_load = pic_dispatch_post_load, .fields = (VMStateField[]) { VMSTATE_UINT8(last_irr, PICCommonState), VMSTATE_UINT8(irr, PICCommonState), VMSTATE_UINT8(imr, PICCommonState), VMSTATE_UINT8(isr, PICCommonState), VMSTATE_UINT8(priority_add, PICCommonState), VMSTATE_UINT8(irq_base, PICCommonState), VMSTATE_UINT8(read_reg_select, PICCommonState), VMSTATE_UINT8(poll, PICCommonState), VMSTATE_UINT8(special_mask, PICCommonState), VMSTATE_UINT8(init_state, PICCommonState), VMSTATE_UINT8(auto_eoi, PICCommonState), VMSTATE_UINT8(rotate_on_auto_eoi, PICCommonState), VMSTATE_UINT8(special_fully_nested_mode, PICCommonState), VMSTATE_UINT8(init4, PICCommonState), VMSTATE_UINT8(single_mode, PICCommonState), VMSTATE_UINT8(elcr, PICCommonState),
PCIXenPlatformState *s = opaque; platform_fixed_ioport_writeb(s, 0, s->flags); return 0; } static const VMStateDescription vmstate_xen_platform = { .name = "platform", .version_id = 4, .minimum_version_id = 4, .minimum_version_id_old = 4, .post_load = xen_platform_post_load, .fields = (VMStateField []) { VMSTATE_PCI_DEVICE(pci_dev, PCIXenPlatformState), VMSTATE_UINT8(flags, PCIXenPlatformState), VMSTATE_END_OF_LIST() } }; static int xen_platform_initfn(PCIDevice *dev) { PCIXenPlatformState *d = DO_UPCAST(PCIXenPlatformState, pci_dev, dev); uint8_t *pci_conf; pci_conf = d->pci_dev.config; pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY); pci_config_set_prog_interface(pci_conf, 0);
VMSTATE_UINT16(ctr, smc91c111_state), VMSTATE_UINT16(gpr, smc91c111_state), VMSTATE_UINT16(ptr, smc91c111_state), VMSTATE_UINT16(ercv, smc91c111_state), VMSTATE_INT32(bank, smc91c111_state), VMSTATE_INT32(packet_num, smc91c111_state), VMSTATE_INT32(tx_alloc, smc91c111_state), VMSTATE_INT32(allocated, smc91c111_state), VMSTATE_INT32(tx_fifo_len, smc91c111_state), VMSTATE_INT32_ARRAY(tx_fifo, smc91c111_state, NUM_PACKETS), VMSTATE_INT32(rx_fifo_len, smc91c111_state), VMSTATE_INT32_ARRAY(rx_fifo, smc91c111_state, NUM_PACKETS), VMSTATE_INT32(tx_fifo_done_len, smc91c111_state), VMSTATE_INT32_ARRAY(tx_fifo_done, smc91c111_state, NUM_PACKETS), VMSTATE_BUFFER_UNSAFE(data, smc91c111_state, 0, NUM_PACKETS * 2048), VMSTATE_UINT8(int_level, smc91c111_state), VMSTATE_UINT8(int_mask, smc91c111_state), VMSTATE_END_OF_LIST() } }; #define RCR_SOFT_RST 0x8000 #define RCR_STRIP_CRC 0x0200 #define RCR_RXEN 0x0100 #define TCR_EPH_LOOP 0x2000 #define TCR_NOCRC 0x0100 #define TCR_PAD_EN 0x0080 #define TCR_FORCOL 0x0004 #define TCR_LOOP 0x0002 #define TCR_TXEN 0x0001
&& s->buttons[i].pressed != down) { s->buttons[i].pressed = down; qemu_set_irq(s->buttons[i].irq, down); } } s->extension = 0; } static const VMStateDescription vmstate_stellaris_button = { .name = "stellaris_button", .version_id = 0, .minimum_version_id = 0, .minimum_version_id_old = 0, .fields = (VMStateField[]) { VMSTATE_UINT8(pressed, gamepad_button), VMSTATE_END_OF_LIST() } }; static const VMStateDescription vmstate_stellaris_gamepad = { .name = "stellaris_gamepad", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField[]) { VMSTATE_INT32(extension, gamepad_state), VMSTATE_STRUCT_VARRAY_INT32(buttons, gamepad_state, num_buttons, 0, vmstate_stellaris_button, gamepad_button), VMSTATE_END_OF_LIST() }
vmmouse_update_handler(s, s->absolute); return 0; } static const VMStateDescription vmstate_vmmouse = { .name = "vmmouse", .version_id = 0, .minimum_version_id = 0, .minimum_version_id_old = 0, .post_load = vmmouse_post_load, .fields = (VMStateField []) { VMSTATE_INT32_EQUAL(queue_size, VMMouseState), VMSTATE_UINT32_ARRAY(queue, VMMouseState, VMMOUSE_QUEUE_SIZE), VMSTATE_UINT16(nb_queue, VMMouseState), VMSTATE_UINT16(status, VMMouseState), VMSTATE_UINT8(absolute, VMMouseState), VMSTATE_END_OF_LIST() } }; static void vmmouse_reset(void *opaque) { VMMouseState *s = opaque; s->status = 0xffff; s->queue_size = VMMOUSE_QUEUE_SIZE; vmmouse_disable(s); } void *vmmouse_init(void *m)
{ GICState *s = (GICState *)opaque; ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s); if (c->post_load) { c->post_load(s); } return 0; } static const VMStateDescription vmstate_gic_irq_state = { .name = "arm_gic_irq_state", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_UINT8(enabled, gic_irq_state), VMSTATE_UINT8(pending, gic_irq_state), VMSTATE_UINT8(active, gic_irq_state), VMSTATE_UINT8(level, gic_irq_state), VMSTATE_BOOL(model, gic_irq_state), VMSTATE_BOOL(edge_trigger, gic_irq_state), VMSTATE_UINT8(group, gic_irq_state), VMSTATE_END_OF_LIST() } }; static const VMStateDescription vmstate_gic = { .name = "arm_gic", .version_id = 12, .minimum_version_id = 12, .pre_save = gic_pre_save,
const VMStateDescription vmstate_IPMIBT = { .name = TYPE_IPMI_INTERFACE_PREFIX "bt", .version_id = 1, .minimum_version_id = 1, .post_load = ipmi_bt_vmstate_post_load, .fields = (VMStateField[]) { VMSTATE_BOOL(obf_irq_set, IPMIBT), VMSTATE_BOOL(atn_irq_set, IPMIBT), VMSTATE_BOOL(irqs_enabled, IPMIBT), VMSTATE_UINT32(outpos, IPMIBT), VMSTATE_UINT32(outlen, IPMIBT), VMSTATE_UINT8_ARRAY(outmsg, IPMIBT, MAX_IPMI_MSG_SIZE), VMSTATE_UINT32(inlen, IPMIBT), VMSTATE_UINT8_ARRAY(inmsg, IPMIBT, MAX_IPMI_MSG_SIZE), VMSTATE_UINT8(control_reg, IPMIBT), VMSTATE_UINT8(mask_reg, IPMIBT), VMSTATE_UINT8(waiting_rsp, IPMIBT), VMSTATE_UINT8(waiting_seq, IPMIBT), VMSTATE_END_OF_LIST() } }; static const VMStateDescription vmstate_ISAIPMIBTDevice = { .name = TYPE_IPMI_INTERFACE_PREFIX "isa-bt", .version_id = 2, .minimum_version_id = 2, /* * Version 1 had messed up the array transfer, it's not even usable * because it used VMSTATE_VBUFFER_UINT32, but it did not transfer * the buffer length, so random things would happen.
if (addr == 0) { val = apm->apmc; } else { val = apm->apms; } APM_DPRINTF("apm_ioport_readb addr=0x%x val=0x%02x\n", addr, val); return val; } const VMStateDescription vmstate_apm = { .name = "APM State", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField[]) { VMSTATE_UINT8(apmc, APMState), VMSTATE_UINT8(apms, APMState), VMSTATE_END_OF_LIST() } }; void apm_init(APMState *apm, apm_ctrl_changed_t callback, void *arg) { apm->callback = callback; apm->arg = arg; /* ioport 0xb2, 0xb3 */ register_ioport_write(APM_CNT_IOPORT, 2, 1, apm_ioport_writeb, apm); register_ioport_read(APM_CNT_IOPORT, 2, 1, apm_ioport_readb, apm); }
.fields = (VMStateField[]) { VMSTATE_UINT64_ARRAY(env.regs, S390CPU, 16), VMSTATE_UINT64(env.psw.mask, S390CPU), VMSTATE_UINT64(env.psw.addr, S390CPU), VMSTATE_UINT64(env.psa, S390CPU), VMSTATE_UINT32(env.todpr, S390CPU), VMSTATE_UINT64(env.pfault_token, S390CPU), VMSTATE_UINT64(env.pfault_compare, S390CPU), VMSTATE_UINT64(env.pfault_select, S390CPU), VMSTATE_UINT64(env.cputm, S390CPU), VMSTATE_UINT64(env.ckc, S390CPU), VMSTATE_UINT64(env.gbea, S390CPU), VMSTATE_UINT64(env.pp, S390CPU), VMSTATE_UINT32_ARRAY(env.aregs, S390CPU, 16), VMSTATE_UINT64_ARRAY(env.cregs, S390CPU, 16), VMSTATE_UINT8(env.cpu_state, S390CPU), VMSTATE_UINT8(env.sigp_order, S390CPU), VMSTATE_UINT32_V(irqstate_saved_size, S390CPU, 4), VMSTATE_VBUFFER_UINT32(irqstate, S390CPU, 4, NULL, irqstate_saved_size), VMSTATE_END_OF_LIST() }, .subsections = (const VMStateDescription*[]) { &vmstate_fpu, &vmstate_vregs, &vmstate_riccb, &vmstate_exval, &vmstate_gscb, NULL }, };
DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF), DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0), DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8), DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2), DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10), DEFINE_PROP_DRIVE("drive", Flash, blk), DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_m25p80 = { .name = "m25p80", .version_id = 0, .minimum_version_id = 0, .pre_save = m25p80_pre_save, .fields = (VMStateField[]) { VMSTATE_UINT8(state, Flash), VMSTATE_UINT8_ARRAY(data, Flash, 16), VMSTATE_UINT32(len, Flash), VMSTATE_UINT32(pos, Flash), VMSTATE_UINT8(needed_bytes, Flash), VMSTATE_UINT8(cmd_in_progress, Flash), VMSTATE_UINT32(cur_addr, Flash), VMSTATE_BOOL(write_enable, Flash), VMSTATE_BOOL(reset_enable, Flash), VMSTATE_UINT8(ear, Flash), VMSTATE_BOOL(four_bytes_address_mode, Flash), VMSTATE_UINT32(nonvolatile_cfg, Flash), VMSTATE_UINT32(volatile_cfg, Flash), VMSTATE_UINT32(enh_volatile_cfg, Flash), VMSTATE_BOOL(quad_enable, Flash), VMSTATE_UINT8(spansion_cr1nv, Flash),
}; static const MemoryRegionPortio isa_parallel_portio_sw_list[] = { { 0, 8, 1, .read = parallel_ioport_read_sw, .write = parallel_ioport_write_sw }, PORTIO_END_OF_LIST(), }; static const VMStateDescription vmstate_parallel_isa = { .name = "parallel_isa", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_UINT8(state.dataw, ISAParallelState), VMSTATE_UINT8(state.datar, ISAParallelState), VMSTATE_UINT8(state.status, ISAParallelState), VMSTATE_UINT8(state.control, ISAParallelState), VMSTATE_INT32(state.irq_pending, ISAParallelState), VMSTATE_INT32(state.epp_timeout, ISAParallelState), VMSTATE_END_OF_LIST() } }; static void parallel_isa_realizefn(DeviceState *dev, Error **errp) { static int index; ISADevice *isadev = ISA_DEVICE(dev); ISAParallelState *isa = ISA_PARALLEL(dev);
memory_region_set_address(&s->simm[socket], start_address); start_address += memory_region_size(&s->simm[socket]); } } } isa_register_portio_list(ISA_DEVICE(dev), &s->portio, 0x0, rs6000mc_port_list, s, "rs6000mc"); } static const VMStateDescription vmstate_rs6000mc = { .name = "rs6000-mc", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_UINT8(port0820_index, RS6000MCState), VMSTATE_END_OF_LIST() }, }; static Property rs6000mc_properties[] = { DEFINE_PROP_UINT32("ram-size", RS6000MCState, ram_size, 0), DEFINE_PROP_BOOL("auto-configure", RS6000MCState, autoconfigure, true), DEFINE_PROP_END_OF_LIST() }; static void rs6000mc_class_initfn(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = rs6000mc_realize;
return -EINVAL; } s->ioaddr = s->io + s->ioaddr_vmstate; return 0; } static const VMStateDescription vmstate_nand = { .name = "nand", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .pre_save = nand_pre_save, .post_load = nand_post_load, .fields = (VMStateField[]) { VMSTATE_UINT8(cle, NANDFlashState), VMSTATE_UINT8(ale, NANDFlashState), VMSTATE_UINT8(ce, NANDFlashState), VMSTATE_UINT8(wp, NANDFlashState), VMSTATE_UINT8(gnd, NANDFlashState), VMSTATE_BUFFER(io, NANDFlashState), VMSTATE_UINT32(ioaddr_vmstate, NANDFlashState), VMSTATE_INT32(iolen, NANDFlashState), VMSTATE_UINT32(cmd, NANDFlashState), VMSTATE_UINT64(addr, NANDFlashState), VMSTATE_INT32(addrlen, NANDFlashState), VMSTATE_INT32(status, NANDFlashState), VMSTATE_INT32(offset, NANDFlashState), /* XXX: do we want to save s->storage too? */ VMSTATE_END_OF_LIST() }
.subsections = (const VMStateDescription*[]) { &vmstate_iplb_extended, NULL } }; static const VMStateDescription vmstate_ipl = { .name = "ipl", .version_id = 0, .minimum_version_id = 0, .fields = (VMStateField[]) { VMSTATE_UINT64(compat_start_addr, S390IPLState), VMSTATE_UINT64(compat_bios_start_addr, S390IPLState), VMSTATE_STRUCT(iplb, S390IPLState, 0, vmstate_iplb, IplParameterBlock), VMSTATE_BOOL(iplb_valid, S390IPLState), VMSTATE_UINT8(cssid, S390IPLState), VMSTATE_UINT8(ssid, S390IPLState), VMSTATE_UINT16(devno, S390IPLState), VMSTATE_END_OF_LIST() } }; static S390IPLState *get_ipl_device(void) { return S390_IPL(object_resolve_path_type("", TYPE_S390_IPL, NULL)); } static uint64_t bios_translate_addr(void *opaque, uint64_t srcaddr) { uint64_t dstaddr = *(uint64_t *) opaque; /*
return 0; } static const VMStateDescription vmstate_ide_pc98 = { .name = "pc98-ide", .version_id = 1, .minimum_version_id = 0, .minimum_version_id_old = 0, .pre_save = pc98_ide_pre_save, .post_load = pc98_ide_post_load, .fields = (VMStateField []) { VMSTATE_IDE_BUS(bus[0], PC98IDEState), VMSTATE_IDE_DRIVES(bus[0].ifs, PC98IDEState), VMSTATE_IDE_BUS(bus[1], PC98IDEState), VMSTATE_IDE_DRIVES(bus[1].ifs, PC98IDEState), VMSTATE_UINT8(bus1_selected_vmstate, PC98IDEState), VMSTATE_END_OF_LIST() } }; static int pc98_ide_initfn(ISADevice *dev) { PC98IDEState *s = DO_UPCAST(PC98IDEState, dev, dev); int i; ide_bus_new(&s->bus[0], &s->dev.qdev, 0); ide_bus_new(&s->bus[1], &s->dev.qdev, 1); isa_init_irq(dev, &s->irq, s->isairq); ide_init2(&s->bus[0], s->irq); ide_init2(&s->bus[1], s->irq);
} static int pc98_kbd_pre_load(void *opaque) { pc98_kbd_reset(opaque); return 0; } static const VMStateDescription vmstate_kbd = { .name = "pc98-kbd", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .pre_load = pc98_kbd_pre_load, .fields = (VMStateField []) { VMSTATE_UINT8(lock, KeyBoardState), VMSTATE_UINT8(mode, KeyBoardState), VMSTATE_UINT8(status, KeyBoardState), VMSTATE_UINT8(rts, KeyBoardState), VMSTATE_UINT8(sbrk, KeyBoardState), VMSTATE_UINT8(rxen, KeyBoardState), VMSTATE_UINT8(txen, KeyBoardState), VMSTATE_UINT8(recv_data, KeyBoardState), VMSTATE_END_OF_LIST() } }; static int pc98_kbd_initfn(ISADevice *dev) { KeyBoardState *s = DO_UPCAST(KeyBoardState, dev, dev);
} static void *acpi_add_rom_blob(AcpiBuildState *build_state, GArray *blob, const char *name) { return rom_add_blob(name, blob->data, acpi_data_len(blob), -1, name, acpi_build_update, build_state); } static const VMStateDescription vmstate_acpi_build = { .name = "acpi_build", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField[]) { VMSTATE_UINT8(patched, AcpiBuildState), VMSTATE_END_OF_LIST() }, }; void acpi_setup(PcGuestInfo *guest_info) { AcpiBuildTables tables; AcpiBuildState *build_state; if (!guest_info->fw_cfg) { ACPI_BUILD_DPRINTF(3, "No fw cfg. Bailing out.\n"); return; } if (!guest_info->has_acpi_build) {
return info->post_load(ss, version_id); } return 0; } static const VMStateDescription vmstate_icp_server = { .name = "icp/server", .version_id = 1, .minimum_version_id = 1, .pre_save = icp_dispatch_pre_save, .post_load = icp_dispatch_post_load, .fields = (VMStateField[]) { /* Sanity check */ VMSTATE_UINT32(xirr, ICPState), VMSTATE_UINT8(pending_priority, ICPState), VMSTATE_UINT8(mfrr, ICPState), VMSTATE_END_OF_LIST() }, }; static void icp_reset(DeviceState *dev) { ICPState *icp = ICP(dev); icp->xirr = 0; icp->pending_priority = 0xff; icp->mfrr = 0xff; /* Make all outputs are deasserted */ qemu_set_irq(icp->output, 0);
VMSTATE_END_OF_LIST() } }; static const VMStateDescription vmstate_apic_common = { .name = "apic", .version_id = 3, .minimum_version_id = 3, .minimum_version_id_old = 1, .load_state_old = apic_load_old, .pre_load = apic_pre_load, .pre_save = apic_dispatch_pre_save, .post_load = apic_dispatch_post_load, .fields = (VMStateField[]) { VMSTATE_UINT32(apicbase, APICCommonState), VMSTATE_UINT8(id, APICCommonState), VMSTATE_UINT8(arb_id, APICCommonState), VMSTATE_UINT8(tpr, APICCommonState), VMSTATE_UINT32(spurious_vec, APICCommonState), VMSTATE_UINT8(log_dest, APICCommonState), VMSTATE_UINT8(dest_mode, APICCommonState), VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8), VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8), VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8), VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB), VMSTATE_UINT32(esr, APICCommonState), VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2), VMSTATE_UINT32(divide_conf, APICCommonState), VMSTATE_INT32(count_shift, APICCommonState), VMSTATE_UINT32(initial_count, APICCommonState), VMSTATE_INT64(initial_count_load_time, APICCommonState),
static int mch_post_load(void *opaque, int version_id) { MCHPCIState *mch = opaque; mch_update(mch); return 0; } static const VMStateDescription vmstate_mch = { .name = "mch", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .post_load = mch_post_load, .fields = (VMStateField []) { VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), VMSTATE_UINT8(smm_enabled, MCHPCIState), VMSTATE_END_OF_LIST() } }; static void mch_reset(DeviceState *qdev) { PCIDevice *d = PCI_DEVICE(qdev); MCHPCIState *mch = MCH_PCI_DEVICE(d); pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; mch_update(mch);
.write = slavio_led_mem_writew, .endianness = DEVICE_NATIVE_ENDIAN, .valid = { .min_access_size = 2, .max_access_size = 2, }, }; static const VMStateDescription vmstate_misc = { .name ="slavio_misc", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField []) { VMSTATE_UINT32(dummy, MiscState), VMSTATE_UINT8(config, MiscState), VMSTATE_UINT8(aux1, MiscState), VMSTATE_UINT8(aux2, MiscState), VMSTATE_UINT8(diag, MiscState), VMSTATE_UINT8(mctrl, MiscState), VMSTATE_UINT8(sysctrl, MiscState), VMSTATE_END_OF_LIST() } }; static int apc_init1(SysBusDevice *dev) { APCState *s = FROM_SYSBUS(APCState, dev); sysbus_init_irq(dev, &s->cpu_halt);
return 0; } static const VMStateDescription vmstate_cg3 = { .name = "cg3", .version_id = 1, .minimum_version_id = 1, .post_load = vmstate_cg3_post_load, .fields = (VMStateField[]) { VMSTATE_UINT16(height, CG3State), VMSTATE_UINT16(width, CG3State), VMSTATE_UINT16(depth, CG3State), VMSTATE_BUFFER(r, CG3State), VMSTATE_BUFFER(g, CG3State), VMSTATE_BUFFER(b, CG3State), VMSTATE_UINT8(dac_index, CG3State), VMSTATE_UINT8(dac_state, CG3State), VMSTATE_END_OF_LIST() } }; static void cg3_reset(DeviceState *d) { CG3State *s = CG3(d); /* Initialize palette */ memset(s->r, 0, 256); memset(s->g, 0, 256); memset(s->b, 0, 256); s->dac_state = 0;
#endif s->pending |= mask; } else { s->pending &= ~mask; } sun4c_check_interrupts(s); } } static const VMStateDescription vmstate_sun4c_intctl = { .name ="sun4c_intctl", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField []) { VMSTATE_UINT8(reg, Sun4c_INTCTLState), VMSTATE_UINT8(pending, Sun4c_INTCTLState), VMSTATE_END_OF_LIST() } }; static void sun4c_intctl_reset(DeviceState *d) { Sun4c_INTCTLState *s = container_of(d, Sun4c_INTCTLState, busdev.qdev); s->reg = 1; s->pending = 0; } static int sun4c_intctl_init1(SysBusDevice *dev) {
}; #define VMSTATE_UINT16_HACK_TEST(_f, _s, _t) \ VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint16_from_uint8, uint16_t) static bool is_old_eeprom_version(void *opaque, int version_id) { return version_id == OLD_EEPROM_VERSION; } static const VMStateDescription vmstate_eeprom = { .name = "eeprom", .version_id = EEPROM_VERSION, .minimum_version_id = OLD_EEPROM_VERSION, .fields = (VMStateField[]) { VMSTATE_UINT8(tick, eeprom_t), VMSTATE_UINT8(address, eeprom_t), VMSTATE_UINT8(command, eeprom_t), VMSTATE_UINT8(writable, eeprom_t), VMSTATE_UINT8(eecs, eeprom_t), VMSTATE_UINT8(eesk, eeprom_t), VMSTATE_UINT8(eedo, eeprom_t), VMSTATE_UINT8(addrbits, eeprom_t), VMSTATE_UINT16_HACK_TEST(size, eeprom_t, is_old_eeprom_version), VMSTATE_UNUSED_TEST(is_old_eeprom_version, 1), VMSTATE_UINT16_EQUAL_V(size, eeprom_t, EEPROM_VERSION), VMSTATE_UINT16(data, eeprom_t), VMSTATE_VARRAY_UINT16_UNSAFE(contents, eeprom_t, size, 0, vmstate_info_uint16, uint16_t),
typedef struct { SysBusDevice busdev; uint8_t buttonState; qemu_irq gpio_out; CharDriverState* chr; /* Char device */ } stm32_button_state; static const VMStateDescription vmstate_stm32_button = { .name = "stm32_button", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_UINT8(buttonState, stm32_button_state), VMSTATE_END_OF_LIST() } }; static void stm32_button_reset(stm32_button_state *s) { s->buttonState = 0; } //--------------------------------------------------- //CHARDEV //--------------------------------------------------- static int stm32_can_receive(void *opaque) {return 1;} static void stm32_receive(void *opaque, const uint8_t* buf, int size) { stm32_button_state *s = (stm32_button_state *) opaque;