}
static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id)
{
ARMCPU *cpu = opaque;
return cpu->env.cp15.c6_rgnr < cpu->pmsav7_dregion;
}
static const VMStateDescription vmstate_pmsav7 = {
.name = "cpu/pmsav7",
.version_id = 1,
.minimum_version_id = 1,
.needed = pmsav7_needed,
.fields = (VMStateField[]) {
VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0,
vmstate_info_uint32, uint32_t),
VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0,
vmstate_info_uint32, uint32_t),
VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0,
vmstate_info_uint32, uint32_t),
VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate),
VMSTATE_END_OF_LIST()
}
};
static int get_cpsr(QEMUFile *f, void *opaque, size_t size)
{
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
uint32_t val = qemu_get_be32(f);
printf("nvram_post_load: short write\n");
}
fflush(s->file);
}
return 0;
}
static const VMStateDescription vmstate_nvram = {
.name = "nvram",
.version_id = 0,
.minimum_version_id = 0,
.minimum_version_id_old = 0,
.post_load = nvram_post_load,
.fields = (VMStateField[]) {
VMSTATE_VARRAY_UINT32(contents, NvRamState, chip_size, 0,
vmstate_info_uint8, uint8_t),
VMSTATE_END_OF_LIST()
}
};
typedef struct {
SysBusDevice busdev;
NvRamState nvram;
} SysBusNvRamState;
static int nvram_sysbus_initfn(SysBusDevice *dev)
{
NvRamState *s = &FROM_SYSBUS(SysBusNvRamState, dev)->nvram;
FILE *file;
s->contents = g_malloc0(s->chip_size);
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(leds, arm_sysctl_state),
VMSTATE_UINT16(lockval, arm_sysctl_state),
VMSTATE_UINT32(cfgdata1, arm_sysctl_state),
VMSTATE_UINT32(cfgdata2, arm_sysctl_state),
VMSTATE_UINT32(flags, arm_sysctl_state),
VMSTATE_UINT32(nvflags, arm_sysctl_state),
VMSTATE_UINT32(resetlevel, arm_sysctl_state),
VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2),
VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2),
VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
VMSTATE_UINT32_ARRAY_V(mb_clock, arm_sysctl_state, 6, 4),
VMSTATE_VARRAY_UINT32(db_clock, arm_sysctl_state, db_num_clocks,
4, vmstate_info_uint32, uint32_t),
VMSTATE_END_OF_LIST()
}
};
/* The PB926 actually uses a different format for
* its SYS_ID register. Fortunately the bits which are
* board type on later boards are distinct.
*/
#define BOARD_ID_PB926 0x100
#define BOARD_ID_EB 0x140
#define BOARD_ID_PBA8 0x178
#define BOARD_ID_PBX 0x182
#define BOARD_ID_VEXPRESS 0x190
static int board_id(arm_sysctl_state *s)
}
syborg_keyboard_update(s);
}
static const VMStateDescription vmstate_syborg_keyboard = {
.name = "syborg_keyboard",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32_EQUAL(fifo_size, SyborgKeyboardState),
VMSTATE_UINT32(int_enabled, SyborgKeyboardState),
VMSTATE_UINT32(read_pos, SyborgKeyboardState),
VMSTATE_UINT32(read_count, SyborgKeyboardState),
VMSTATE_VARRAY_UINT32(key_fifo, SyborgKeyboardState, fifo_size, 1,
vmstate_info_uint32, uint32),
VMSTATE_END_OF_LIST()
}
};
static int syborg_keyboard_init(SysBusDevice *dev)
{
SyborgKeyboardState *s = FROM_SYSBUS(SyborgKeyboardState, dev);
int iomemtype;
sysbus_init_irq(dev, &s->irq);
iomemtype = cpu_register_io_memory(syborg_keyboard_readfn,
syborg_keyboard_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
if (s->fifo_size <= 0) {
