/**
* @brief 初始化VREF 模块
* @param[in] VREF_InitStruct 指向VREF初始化结构体的指针
* @retval None
*/
void VREF_Init(VREF_InitTypeDef *VREF_InitStruct)
{
/* open clock gate */
SIM->SCGC4 |= SIM_SCGC4_VREF_MASK;
/* enable moudle */
#ifdef VREF_SC_ICOMPEN_MASK
VREF->SC = VREF_SC_VREFEN_MASK | VREF_SC_REGEN_MASK | VREF_SC_ICOMPEN_MASK | VREF_SC_MODE_LV(VREF_InitStruct->bufferMode);
VREF->TRM |= VREF_TRM_CHOPEN_MASK;
#else
VREF->SC = VREF_SC_VREFEN_MASK | VREF_SC_REGEN_MASK | VREF_SC_MODE_LV(VREF_InitStruct->bufferMode);
#endif
}
/* Initialize stuff:
* - Start Vref module
* - Clear all fail flags
* - Internal reference (default: external vcc)
* - Mux between a and b channels (b channels)
* - Calibrate with 32 averages and low speed
* - When first calibration is done it sets:
* - Resolution (default: 10 bits)
* - Conversion speed and sampling time (both set to medium speed)
* - Averaging (set to 4)
*/
void ADC_Module::analog_init() {
// default settings:
/*
- 10 bits resolution
- 4 averages
- vcc reference
- no interrupts
- pga gain=1
- conversion speed = medium
- sampling speed = medium
initiate to 0 (or 1) so the corresponding functions change it to the correct value
*/
analog_res_bits = 0;
analog_max_val = 0;
analog_num_average = 0;
analog_reference_internal = 1;
var_enableInterrupts = 0;
pga_value = 1;
conversion_speed = 0;
sampling_speed = 0;
// the first calibration will use 32 averages and lowest speed,
// when this calibration is over the averages and speed will be set to default by wait_for_cal and init_calib will be cleared.
init_calib = 1;
fail_flag = ADC_ERROR_CLEAR; // clear all errors
// Internal reference initialization
VREF_TRM = VREF_TRM_CHOPEN | 0x20; // enable module and set the trimmer to medium (max=0x3F=63)
VREF_SC = VREF_SC_VREFEN | VREF_SC_REGEN | VREF_SC_ICOMPEN | VREF_SC_MODE_LV(1); // (=0xE1) enable 1.2 volt ref with all compensations
// select b channels
*ADC_CFG2_muxsel = 1;
// set reference to vcc/external
setReference(ADC_REF_EXTERNAL);
// set resolution to 10
setResolution(10);
// calibrate at low speed and max repetitions
setAveraging(32);
setConversionSpeed(ADC_LOW_SPEED);
setSamplingSpeed(ADC_LOW_SPEED);
// begin init calibration
calibrate();
}
void VREF_Init(VREF_Type *base, const vref_config_t *config)
{
assert(config != NULL);
uint8_t reg = 0U;
/* Ungate clock for VREF */
CLOCK_EnableClock(s_vrefClocks[VREF_GetInstance(base)]);
/* Configure VREF to a known state */
#if defined(FSL_FEATURE_VREF_HAS_CHOP_OSC) && FSL_FEATURE_VREF_HAS_CHOP_OSC
/* Set chop oscillator bit */
base->TRM |= VREF_TRM_CHOPEN_MASK;
#endif /* FSL_FEATURE_VREF_HAS_CHOP_OSC */
reg = base->SC;
/* Set buffer Mode selection and Regulator enable bit */
reg |= VREF_SC_MODE_LV(config->bufferMode) | VREF_SC_REGEN(1U);
#if defined(FSL_FEATURE_VREF_HAS_COMPENSATION) && FSL_FEATURE_VREF_HAS_COMPENSATION
/* Set second order curvature compensation enable bit */
reg |= VREF_SC_ICOMPEN(1U);
#endif /* FSL_FEATURE_VREF_HAS_COMPENSATION */
/* Enable VREF module */
reg |= VREF_SC_VREFEN(1U);
/* Update bit-field from value to Status and Control register */
base->SC = reg;
#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
reg = base->VREFL_TRM;
/* Clear old select external voltage reference and VREFL (0.4 V) reference buffer enable bits*/
reg &= ~(VREF_VREFL_TRM_VREFL_EN_MASK | VREF_VREFL_TRM_VREFL_SEL_MASK);
/* Select external voltage reference and set VREFL (0.4 V) reference buffer enable */
reg |= VREF_VREFL_TRM_VREFL_SEL(config->enableExternalVoltRef) | VREF_VREFL_TRM_VREFL_EN(config->enableLowRef);
base->VREFL_TRM = reg;
#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
/* Wait until internal voltage stable */
while ((base->SC & VREF_SC_VREFST_MASK) == 0)
{
}
}
//! Start the 1.2V internal reference (if present)
void ADC_Module::startInternalReference() {
#if defined(ADC_TEENSY_3_1) || defined(ADC_TEENSY_3_0)
VREF_TRM = VREF_TRM_CHOPEN | 0x20; // enable module and set the trimmer to medium (max=0x3F=63)
VREF_SC = VREF_SC_VREFEN | VREF_SC_REGEN | VREF_SC_ICOMPEN | VREF_SC_MODE_LV(1); // (=0xE1) enable 1.2 volt ref with all compensations
#endif
}
