/* * If credit checking is enabled for this window, poll for the return * of window credits (i.e for NX engines to process any outstanding CRBs). * Since NX-842 waits for the CRBs to be processed before closing the * window, we should not have to wait for too long. * * TODO: We retry in 10ms intervals now. We could/should probably peek at * the VAS_LRFIFO_PUSH_OFFSET register to get an estimate of pending * CRBs on the FIFO and compute the delay dynamically on each retry. * But that is not really needed until we support NX-GZIP access from * user space. (NX-842 driver waits for CSB and Fast thread-wakeup * doesn't use credit checking). */ static void poll_window_credits(struct vas_window *window) { u64 val; int creds, mode; val = read_hvwc_reg(window, VREG(WINCTL)); if (window->tx_win) mode = GET_FIELD(VAS_WINCTL_TX_WCRED_MODE, val); else mode = GET_FIELD(VAS_WINCTL_RX_WCRED_MODE, val); if (!mode) return; retry: if (window->tx_win) { val = read_hvwc_reg(window, VREG(TX_WCRED)); creds = GET_FIELD(VAS_TX_WCRED, val); } else { val = read_hvwc_reg(window, VREG(LRX_WCRED)); creds = GET_FIELD(VAS_LRX_WCRED, val); } if (creds < window->wcreds_max) { val = 0; set_current_state(TASK_UNINTERRUPTIBLE); schedule_timeout(msecs_to_jiffies(10)); goto retry; } }
/* * Unpin and close a window so no new requests are accepted and the * hardware can evict this window from cache if necessary. */ static void unpin_close_window(struct vas_window *window) { u64 val; val = read_hvwc_reg(window, VREG(WINCTL)); val = SET_FIELD(VAS_WINCTL_PIN, val, 0); val = SET_FIELD(VAS_WINCTL_OPEN, val, 0); write_hvwc_reg(window, VREG(WINCTL), val); }
/* * Initialize window context registers related to Address Translation. * These registers are common to send/receive windows although they * differ for user/kernel windows. As we resolve the TODOs we may * want to add fields to vas_winctx and move the initialization to * init_vas_winctx_regs(). */ static void init_xlate_regs(struct vas_window *window, bool user_win) { u64 lpcr, val; /* * MSR_TA, MSR_US are false for both kernel and user. * MSR_DR and MSR_PR are false for kernel. */ val = 0ULL; val = SET_FIELD(VAS_XLATE_MSR_HV, val, 1); val = SET_FIELD(VAS_XLATE_MSR_SF, val, 1); if (user_win) { val = SET_FIELD(VAS_XLATE_MSR_DR, val, 1); val = SET_FIELD(VAS_XLATE_MSR_PR, val, 1); } write_hvwc_reg(window, VREG(XLATE_MSR), val); lpcr = mfspr(SPRN_LPCR); val = 0ULL; /* * NOTE: From Section 5.7.8.1 Segment Lookaside Buffer of the * Power ISA, v3.0B, Page size encoding is 0 = 4KB, 5 = 64KB. * * NOTE: From Section 1.3.1, Address Translation Context of the * Nest MMU Workbook, LPCR_SC should be 0 for Power9. */ val = SET_FIELD(VAS_XLATE_LPCR_PAGE_SIZE, val, 5); val = SET_FIELD(VAS_XLATE_LPCR_ISL, val, lpcr & LPCR_ISL); val = SET_FIELD(VAS_XLATE_LPCR_TC, val, lpcr & LPCR_TC); val = SET_FIELD(VAS_XLATE_LPCR_SC, val, 0); write_hvwc_reg(window, VREG(XLATE_LPCR), val); /* * Section 1.3.1 (Address translation Context) of NMMU workbook. * 0b00 Hashed Page Table mode * 0b01 Reserved * 0b10 Radix on HPT * 0b11 Radix on Radix */ val = 0ULL; val = SET_FIELD(VAS_XLATE_MODE, val, radix_enabled() ? 3 : 2); write_hvwc_reg(window, VREG(XLATE_CTL), val); /* * TODO: Can we mfspr(AMR) even for user windows? */ val = 0ULL; val = SET_FIELD(VAS_AMR, val, mfspr(SPRN_AMR)); write_hvwc_reg(window, VREG(AMR), val); val = 0ULL; val = SET_FIELD(VAS_SEIDR, val, 0); write_hvwc_reg(window, VREG(SEIDR), val); }
void DSP::voice_2(voice_t &v) { //read sample pointer (ignored if not needed) uint16 addr = state.t_dir_addr; if(!v.kon_delay) addr += 2; uint8 lo = smp.apuram[(uint16)(addr + 0)]; uint8 hi = smp.apuram[(uint16)(addr + 1)]; state.t_brr_next_addr = ((hi << 8) + lo); state.t_adsr0 = VREG(adsr0); //read pitch, spread over two clocks state.t_pitch = VREG(pitchl); }
inline void DSP::voice_output(voice_t &v, bool channel) { //apply left/right volume int amp = (state.t_output * (int8)VREG(voll + channel)) >> 7; //add to output total state.t_main_out[channel] += amp; state.t_main_out[channel] = sclamp<16>(state.t_main_out[channel]); //optionally add to echo total if(state.t_eon & v.vbit) { state.t_echo_out[channel] += amp; state.t_echo_out[channel] = sclamp<16>(state.t_echo_out[channel]); } }
/* * Wait for the window to go to "not-busy" state. It should only take a * short time to queue a CRB, so window should not be busy for too long. * Trying 5ms intervals. */ static void poll_window_busy_state(struct vas_window *window) { int busy; u64 val; retry: val = read_hvwc_reg(window, VREG(WIN_STATUS)); busy = GET_FIELD(VAS_WIN_BUSY, val); if (busy) { val = 0; set_current_state(TASK_UNINTERRUPTIBLE); schedule_timeout(msecs_to_jiffies(5)); goto retry; } }
void sDSP::envelope_run(voice_t &v) { int env = v.env; if(v.env_mode == env_release) { //60% env -= 0x8; if(env < 0) env = 0; v.env = env; return; } int rate; int env_data = VREG(adsr1); if(state.t_adsr0 & 0x80) { //99% ADSR if(v.env_mode >= env_decay) { //99% env--; env -= env >> 8; rate = env_data & 0x1f; if(v.env_mode == env_decay) { //1% rate = ((state.t_adsr0 >> 3) & 0x0e) + 0x10; } } else { //env_attack
int vas_paste_crb(struct vas_window *txwin, int offset, bool re) { int rc; void *addr; uint64_t val; trace_vas_paste_crb(current, txwin); /* * Only NX windows are supported for now and hardware assumes * report-enable flag is set for NX windows. Ensure software * complies too. */ WARN_ON_ONCE(txwin->nx_win && !re); addr = txwin->paste_kaddr; if (re) { /* * Set the REPORT_ENABLE bit (equivalent to writing * to 1K offset of the paste address) */ val = SET_FIELD(RMA_LSMP_REPORT_ENABLE, 0ULL, 1); addr += val; } /* * Map the raw CR value from vas_paste() to an error code (there * is just pass or fail for now though). */ rc = vas_paste(addr, offset); if (rc == 2) rc = 0; else rc = -EINVAL; pr_debug("Txwin #%d: Msg count %llu\n", txwin->winid, read_hvwc_reg(txwin, VREG(LRFIFO_PUSH))); return rc; }
void DSP::voice_3a(voice_t &v) { state.t_pitch += (VREG(pitchh) & 0x3f) << 8; }
void DSP::voice_1(voice_t &v) { state.t_dir_addr = (state.t_dir << 8) + (state.t_srcn << 2); state.t_srcn = VREG(srcn); }
#define VREG_SWITCH_ENABLE 1 #define VREG_SWITCH_DISABLE 0 #endif struct vreg { const char *name; unsigned id; int status; unsigned refcnt; }; #define VREG(_name, _id, _status, _refcnt) \ { .name = _name, .id = _id, .status = _status, .refcnt = _refcnt } static struct vreg vregs[] = { VREG("msma", 0, 0, 0), VREG("msmp", 1, 0, 0), VREG("msme1", 2, 0, 0), VREG("msmc1", 3, 0, 0), VREG("msmc2", 4, 0, 0), VREG("gp3", 5, 0, 0), VREG("msme2", 6, 0, 0), VREG("gp4", 7, 0, 0), VREG("gp1", 8, 0, 0), VREG("tcxo", 9, 0, 0), VREG("pa", 10, 0, 0), VREG("rftx", 11, 0, 0), VREG("rfrx1", 12, 0, 0), VREG("rfrx2", 13, 0, 0), VREG("synt", 14, 0, 0), VREG("wlan", 15, 0, 0),
/* * init_winctx_regs() * Initialize window context registers for a receive window. * Except for caching control and marking window open, the registers * are initialized in the order listed in Section 3.1.4 (Window Context * Cache Register Details) of the VAS workbook although they don't need * to be. * * Design note: For NX receive windows, NX allocates the FIFO buffer in OPAL * (so that it can get a large contiguous area) and passes that buffer * to kernel via device tree. We now write that buffer address to the * FIFO BAR. Would it make sense to do this all in OPAL? i.e have OPAL * write the per-chip RX FIFO addresses to the windows during boot-up * as a one-time task? That could work for NX but what about other * receivers? Let the receivers tell us the rx-fifo buffers for now. */ int init_winctx_regs(struct vas_window *window, struct vas_winctx *winctx) { u64 val; int fifo_size; reset_window_regs(window); val = 0ULL; val = SET_FIELD(VAS_LPID, val, winctx->lpid); write_hvwc_reg(window, VREG(LPID), val); val = 0ULL; val = SET_FIELD(VAS_PID_ID, val, winctx->pidr); write_hvwc_reg(window, VREG(PID), val); init_xlate_regs(window, winctx->user_win); val = 0ULL; val = SET_FIELD(VAS_FAULT_TX_WIN, val, 0); write_hvwc_reg(window, VREG(FAULT_TX_WIN), val); /* In PowerNV, interrupts go to HV. */ write_hvwc_reg(window, VREG(OSU_INTR_SRC_RA), 0ULL); val = 0ULL; val = SET_FIELD(VAS_HV_INTR_SRC_RA, val, winctx->irq_port); write_hvwc_reg(window, VREG(HV_INTR_SRC_RA), val); val = 0ULL; val = SET_FIELD(VAS_PSWID_EA_HANDLE, val, winctx->pswid); write_hvwc_reg(window, VREG(PSWID), val); write_hvwc_reg(window, VREG(SPARE1), 0ULL); write_hvwc_reg(window, VREG(SPARE2), 0ULL); write_hvwc_reg(window, VREG(SPARE3), 0ULL); /* * NOTE: VAS expects the FIFO address to be copied into the LFIFO_BAR * register as is - do NOT shift the address into VAS_LFIFO_BAR * bit fields! Ok to set the page migration select fields - * VAS ignores the lower 10+ bits in the address anyway, because * the minimum FIFO size is 1K? * * See also: Design note in function header. */ val = __pa(winctx->rx_fifo); val = SET_FIELD(VAS_PAGE_MIGRATION_SELECT, val, 0); write_hvwc_reg(window, VREG(LFIFO_BAR), val); val = 0ULL; val = SET_FIELD(VAS_LDATA_STAMP, val, winctx->data_stamp); write_hvwc_reg(window, VREG(LDATA_STAMP_CTL), val); val = 0ULL; val = SET_FIELD(VAS_LDMA_TYPE, val, winctx->dma_type); val = SET_FIELD(VAS_LDMA_FIFO_DISABLE, val, winctx->fifo_disable); write_hvwc_reg(window, VREG(LDMA_CACHE_CTL), val); write_hvwc_reg(window, VREG(LRFIFO_PUSH), 0ULL); write_hvwc_reg(window, VREG(CURR_MSG_COUNT), 0ULL); write_hvwc_reg(window, VREG(LNOTIFY_AFTER_COUNT), 0ULL); val = 0ULL; val = SET_FIELD(VAS_LRX_WCRED, val, winctx->wcreds_max); write_hvwc_reg(window, VREG(LRX_WCRED), val); val = 0ULL; val = SET_FIELD(VAS_TX_WCRED, val, winctx->wcreds_max); write_hvwc_reg(window, VREG(TX_WCRED), val); write_hvwc_reg(window, VREG(LRX_WCRED_ADDER), 0ULL); write_hvwc_reg(window, VREG(TX_WCRED_ADDER), 0ULL); fifo_size = winctx->rx_fifo_size / 1024; val = 0ULL; val = SET_FIELD(VAS_LFIFO_SIZE, val, ilog2(fifo_size)); write_hvwc_reg(window, VREG(LFIFO_SIZE), val); /* Update window control and caching control registers last so * we mark the window open only after fully initializing it and * pushing context to cache. */ write_hvwc_reg(window, VREG(WIN_STATUS), 0ULL); init_rsvd_tx_buf_count(window, winctx); /* for a send window, point to the matching receive window */ val = 0ULL; val = SET_FIELD(VAS_LRX_WIN_ID, val, winctx->rx_win_id); write_hvwc_reg(window, VREG(LRFIFO_WIN_PTR), val); write_hvwc_reg(window, VREG(SPARE4), 0ULL); val = 0ULL; val = SET_FIELD(VAS_NOTIFY_DISABLE, val, winctx->notify_disable); val = SET_FIELD(VAS_INTR_DISABLE, val, winctx->intr_disable); val = SET_FIELD(VAS_NOTIFY_EARLY, val, winctx->notify_early); val = SET_FIELD(VAS_NOTIFY_OSU_INTR, val, winctx->notify_os_intr_reg); write_hvwc_reg(window, VREG(LNOTIFY_CTL), val); val = 0ULL; val = SET_FIELD(VAS_LNOTIFY_PID, val, winctx->lnotify_pid); write_hvwc_reg(window, VREG(LNOTIFY_PID), val); val = 0ULL; val = SET_FIELD(VAS_LNOTIFY_LPID, val, winctx->lnotify_lpid); write_hvwc_reg(window, VREG(LNOTIFY_LPID), val); val = 0ULL; val = SET_FIELD(VAS_LNOTIFY_TID, val, winctx->lnotify_tid); write_hvwc_reg(window, VREG(LNOTIFY_TID), val); val = 0ULL; val = SET_FIELD(VAS_LNOTIFY_MIN_SCOPE, val, winctx->min_scope); val = SET_FIELD(VAS_LNOTIFY_MAX_SCOPE, val, winctx->max_scope); write_hvwc_reg(window, VREG(LNOTIFY_SCOPE), val); /* Skip read-only registers NX_UTIL and NX_UTIL_SE */ write_hvwc_reg(window, VREG(SPARE5), 0ULL); write_hvwc_reg(window, VREG(NX_UTIL_ADDER), 0ULL); write_hvwc_reg(window, VREG(SPARE6), 0ULL); /* Finally, push window context to memory and... */ val = 0ULL; val = SET_FIELD(VAS_PUSH_TO_MEM, val, 1); write_hvwc_reg(window, VREG(WIN_CTX_CACHING_CTL), val); /* ... mark the window open for business */ val = 0ULL; val = SET_FIELD(VAS_WINCTL_REJ_NO_CREDIT, val, winctx->rej_no_credit); val = SET_FIELD(VAS_WINCTL_PIN, val, winctx->pin_win); val = SET_FIELD(VAS_WINCTL_TX_WCRED_MODE, val, winctx->tx_wcred_mode); val = SET_FIELD(VAS_WINCTL_RX_WCRED_MODE, val, winctx->rx_wcred_mode); val = SET_FIELD(VAS_WINCTL_TX_WORD_MODE, val, winctx->tx_word_mode); val = SET_FIELD(VAS_WINCTL_RX_WORD_MODE, val, winctx->rx_word_mode); val = SET_FIELD(VAS_WINCTL_FAULT_WIN, val, winctx->fault_win); val = SET_FIELD(VAS_WINCTL_NX_WIN, val, winctx->nx_win); val = SET_FIELD(VAS_WINCTL_OPEN, val, 1); write_hvwc_reg(window, VREG(WINCTL), val); return 0; }
0x825B, /* R0 -- Mode word 0 */ 0xC474, /* R1 -- Mode word 1 */ 0x0006, /* R2 -- Register window base, Control flags */ 0x0100, /* R3 -- Data window base, X limit (0x200000) */ 0x0000, /* R4 -- Data length mask (128K) */ 0x0000, /* R5 -- Data segment base (0x000000) */ 0x0001, /* R6 -- Priority access count (1) */ 0x0040, /* R7 -- Object Descriptor Table base (0x200080) */ 0x0080, /* R8 -- Access Table base (0x200100) */ 0x0010, /* R9 -- Color Lookup Table base (0x200020) */ 0x00FF, /* R10 -- Character Generator bases (0x21E000) */ 0x0000, /* R11 -- Access Table address counter */ #if FASTCHIP VREG (3, 8), /* R12 -- HC0 (HSYNC width) VC0 (VSYNC width) */ VREG (5, 10), /* R13 -- HC1 (AHZ start) VC1 (AVZ start) */ VREG (37, 360), /* R14 -- HC2 (AHZ stop) VC2 (AVZ stop) */ VREG (40, 362) /* R15 -- HC3 (HOR sweep) VC3 (VRT sweep) */ #else VREG (3, 8), /* R12 -- HC0 (HSYNC width) VC0 (VSYNC width) */ VREG (6, 10), /* R13 -- HC1 (AHZ start) VC1 (AVZ start) */ VREG (38, 360), /* R14 -- HC2 (AHZ stop) VC2 (AVZ stop) */ VREG (43, 361) /* R15 -- HC3 (HOR sweep) VC3 (VRT sweep) */ #endif }; /* */ /* =============================================================================
/* * Reset all valid registers in the HV and OS/User Window Contexts for * the window identified by @window. * * NOTE: We cannot really use a for loop to reset window context. Not all * offsets in a window context are valid registers and the valid * registers are not sequential. And, we can only write to offsets * with valid registers. */ void reset_window_regs(struct vas_window *window) { write_hvwc_reg(window, VREG(LPID), 0ULL); write_hvwc_reg(window, VREG(PID), 0ULL); write_hvwc_reg(window, VREG(XLATE_MSR), 0ULL); write_hvwc_reg(window, VREG(XLATE_LPCR), 0ULL); write_hvwc_reg(window, VREG(XLATE_CTL), 0ULL); write_hvwc_reg(window, VREG(AMR), 0ULL); write_hvwc_reg(window, VREG(SEIDR), 0ULL); write_hvwc_reg(window, VREG(FAULT_TX_WIN), 0ULL); write_hvwc_reg(window, VREG(OSU_INTR_SRC_RA), 0ULL); write_hvwc_reg(window, VREG(HV_INTR_SRC_RA), 0ULL); write_hvwc_reg(window, VREG(PSWID), 0ULL); write_hvwc_reg(window, VREG(LFIFO_BAR), 0ULL); write_hvwc_reg(window, VREG(LDATA_STAMP_CTL), 0ULL); write_hvwc_reg(window, VREG(LDMA_CACHE_CTL), 0ULL); write_hvwc_reg(window, VREG(LRFIFO_PUSH), 0ULL); write_hvwc_reg(window, VREG(CURR_MSG_COUNT), 0ULL); write_hvwc_reg(window, VREG(LNOTIFY_AFTER_COUNT), 0ULL); write_hvwc_reg(window, VREG(LRX_WCRED), 0ULL); write_hvwc_reg(window, VREG(LRX_WCRED_ADDER), 0ULL); write_hvwc_reg(window, VREG(TX_WCRED), 0ULL); write_hvwc_reg(window, VREG(TX_WCRED_ADDER), 0ULL); write_hvwc_reg(window, VREG(LFIFO_SIZE), 0ULL); write_hvwc_reg(window, VREG(WINCTL), 0ULL); write_hvwc_reg(window, VREG(WIN_STATUS), 0ULL); write_hvwc_reg(window, VREG(WIN_CTX_CACHING_CTL), 0ULL); write_hvwc_reg(window, VREG(TX_RSVD_BUF_COUNT), 0ULL); write_hvwc_reg(window, VREG(LRFIFO_WIN_PTR), 0ULL); write_hvwc_reg(window, VREG(LNOTIFY_CTL), 0ULL); write_hvwc_reg(window, VREG(LNOTIFY_PID), 0ULL); write_hvwc_reg(window, VREG(LNOTIFY_LPID), 0ULL); write_hvwc_reg(window, VREG(LNOTIFY_TID), 0ULL); write_hvwc_reg(window, VREG(LNOTIFY_SCOPE), 0ULL); write_hvwc_reg(window, VREG(NX_UTIL_ADDER), 0ULL); /* Skip read-only registers: NX_UTIL and NX_UTIL_SE */ /* * The send and receive window credit adder registers are also * accessible from HVWC and have been initialized above. We don't * need to initialize from the OS/User Window Context, so skip * following calls: * * write_uwc_reg(window, VREG(TX_WCRED_ADDER), 0ULL); * write_uwc_reg(window, VREG(LRX_WCRED_ADDER), 0ULL); */ }
/* * Initialize Reserved Send Buffer Count for the send window. It involves * writing to the register, reading it back to confirm that the hardware * has enough buffers to reserve. See section 1.3.1.2.1 of VAS workbook. * * Since we can only make a best-effort attempt to fulfill the request, * we don't return any errors if we cannot. * * TODO: Reserved (aka dedicated) send buffers are not supported yet. */ static void init_rsvd_tx_buf_count(struct vas_window *txwin, struct vas_winctx *winctx) { write_hvwc_reg(txwin, VREG(TX_RSVD_BUF_COUNT), 0ULL); }
static int debug_mask = 0b111; module_param_named(debug_mask, debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP); struct vreg { const char *name; unsigned id; int status; unsigned refcnt; }; #define VREG(_name, _id, _status, _refcnt) \ { .name = _name, .id = _id, .status = _status, .refcnt = _refcnt } static struct vreg vregs[] = { VREG("msma", 0, 0, 0), VREG("msmp", 1, 0, 0), VREG("msme1", 2, 0, 0), VREG("msmc1", 3, 0, 0), VREG("msmc2", 4, 0, 0), VREG("gp3", 5, 0, 0), VREG("msme2", 6, 0, 0), VREG("gp4", 7, 0, 0), VREG("gp1", 8, 0, 0), VREG("tcxo", 9, 0, 0), VREG("pa", 10, 0, 0), VREG("rftx", 11, 0, 0), VREG("rfrx1", 12, 0, 0), VREG("rfrx2", 13, 0, 0), VREG("synt", 14, 0, 0), VREG("wlan", 15, 0, 0),
#include <linux/device.h> #include <linux/init.h> #include <linux/debugfs.h> #include <mach/vreg.h> #include <mach/proc_comm.h> struct vreg { const char *name; unsigned id; }; #define VREG(_name, _id) { .name = _name, .id = _id, } static struct vreg vregs[] = { VREG("msma", 0), VREG("msmp", 1), VREG("msme1", 2), VREG("msmc1", 3), VREG("msmc2", 4), VREG("gp3", 5), VREG("msme2", 6), VREG("gp4", 7), VREG("gp1", 8), VREG("tcxo", 9), VREG("pa", 10), VREG("rftx", 11), VREG("rfrx1", 12), VREG("rfrx2", 13), VREG("synt", 14), VREG("wlan", 15),