void uart_init(void)
{
*pUART0_GCTL = 1;
*pUART0_LCR |= DLAB;
*pUART0_DLL = UART0_DIVISOR & 0xFF;
*pUART0_DLH = UART0_DIVISOR >> 8;
*pUART0_LCR &= ~DLAB;
*pUART0_LCR = WLS(8);
*pUART0_IER = 0;
*pPORTF_MUX &= ~(PF11 | PF12);
*pPORTF_FER |= (PF11 | PF12);
}
void init_uart1(int baudrate)
{
int uart_divider;
uart_divider = (((MASTER_CLOCK * VCO_MULTIPLIER) / SCLK_DIVIDER) / 16) / baudrate;
*pPORTF_FER |= 0x000C; // enable UART1 pins
*pUART1_GCTL = UCEN;
*pUART1_LCR = DLAB;
*pUART1_DLL = uart_divider;
*pUART1_DLH = uart_divider >> 8;
*pUART1_LCR = WLS(8); // 8 bit, no parity, one stop bit
char dummy = *pUART1_RBR;
dummy = *pUART1_LSR;
dummy = *pUART1_IIR;
SSYNC;
}
void init_uart0(int baudrate)
{
int uart_divider;
uart_divider = (((MASTER_CLOCK * VCO_MULTIPLIER) / SCLK_DIVIDER) / 16) / baudrate;
*pPORTF_FER |= 0x0003; // enable UART0 pins
*pUART0_GCTL = UCEN;
*pUART0_LCR = DLAB;
*pUART0_DLL = uart_divider;
*pUART0_DLH = uart_divider >> 8;
*pUART0_LCR = WLS(8); // 8 bit, no parity, one stop bit
// dummy reads to clear possible pending errors / irqs
char dummy = *pUART0_RBR;
dummy = *pUART0_LSR;
dummy = *pUART0_IIR;
SSYNC;
}
void init_uart (void)
{
unsigned char temp;
/* Configure port H for flow control CTS */
*pPORTHIO_DIR |= CTS_MASK;
/* Configure port H for flow control RTS */
*pPORTHIO_INEN |= RTS_MASK;
*pPORTHIO_POLAR |= RTS_MASK;
/* Raise CTS to block input */
*pPORTHIO_SET = CTS_MASK;
/* Enable UART pins on port F */
*pPORTF_FER |= 0x000f;
/* Enable UART0 clocks */
*pUART0_GCTL = UCEN;
/* Switch on divisor programming */
*pUART0_LCR = DLAB;
/* Program divisor */
*pUART0_DLL = UART0_DIVIDER;
*pUART0_DLH = UART0_DIVIDER >> 8;
/* Set operational mode (disables divisor programming) */
*pUART0_LCR = WLS(8); /* 8 bit, no parity, one stop bit */
/* Reads to clear possible pending errors / irqs */
temp = *pUART0_RBR;
temp = *pUART0_LSR;
temp = *pUART0_IIR;
SSYNC;
/* Enable receive interrupts on IVG 10 */
*pSIC_IAR1 = (*pSIC_IAR1 & ~(0xf << 0xc)) | P11_IVG(10);
*pSIC_IMASK |= IRQ_DMA8;
*pUART0_IER |= ERBFI;
SSYNC;
/* Setup RTS interrupts on IVG 14, but don't enable */
*pSIC_IAR2 = (*pSIC_IAR2 & ~(0xf << 0x4)) | P17_IVG(14);
*pSIC_IMASK |= IRQ_PFA_PORTH;
SSYNC;
}
static int bfin_sir_set_speed(struct bfin_sir_port *port, int speed)
{
int ret = -EINVAL;
unsigned int quot;
unsigned short val, lsr, lcr;
static int utime;
int count = 10;
lcr = WLS(8);
switch (speed) {
case 9600:
case 19200:
case 38400:
case 57600:
case 115200:
quot = (port->clk + (8 * speed)) / (16 * speed)\
- ANOMALY_05000230;
do {
udelay(utime);
lsr = SIR_UART_GET_LSR(port);
} while (!(lsr & TEMT) && count--);
/* The useconds for 1 bits to transmit */
utime = 1000000 / speed + 1;
/* Clear UCEN bit to reset the UART state machine
* and control registers
*/
val = SIR_UART_GET_GCTL(port);
val &= ~UCEN;
SIR_UART_PUT_GCTL(port, val);
/* Set DLAB in LCR to Access THR RBR IER */
SIR_UART_SET_DLAB(port);
SSYNC();
SIR_UART_PUT_DLL(port, quot & 0xFF);
SIR_UART_PUT_DLH(port, (quot >> 8) & 0xFF);
SSYNC();
/* Clear DLAB in LCR */
SIR_UART_CLEAR_DLAB(port);
SSYNC();
SIR_UART_PUT_LCR(port, lcr);
val = SIR_UART_GET_GCTL(port);
val |= UCEN;
SIR_UART_PUT_GCTL(port, val);
ret = 0;
break;
default:
printk(KERN_WARNING "bfin_sir: Invalid speed %d\n", speed);
break;
}
val = SIR_UART_GET_GCTL(port);
/* If not add the 'RPOLC', we can't catch the receive interrupt.
* It's related with the HW layout and the IR transiver.
*/
val |= IREN | RPOLC;
SIR_UART_PUT_GCTL(port, val);
return ret;
}
static void
bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
struct ktermios *old)
{
struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
unsigned long flags;
unsigned int baud, quot;
unsigned short val, ier, lcr = 0;
switch (termios->c_cflag & CSIZE) {
case CS8:
lcr = WLS(8);
break;
case CS7:
lcr = WLS(7);
break;
case CS6:
lcr = WLS(6);
break;
case CS5:
lcr = WLS(5);
break;
default:
printk(KERN_ERR "%s: word lengh not supported\n",
__func__);
}
if (termios->c_cflag & CSTOPB)
lcr |= STB;
if (termios->c_cflag & PARENB)
lcr |= PEN;
if (!(termios->c_cflag & PARODD))
lcr |= EPS;
if (termios->c_cflag & CMSPAR)
lcr |= STP;
port->read_status_mask = OE;
if (termios->c_iflag & INPCK)
port->read_status_mask |= (FE | PE);
if (termios->c_iflag & (BRKINT | PARMRK))
port->read_status_mask |= BI;
/*
* Characters to ignore
*/
port->ignore_status_mask = 0;
if (termios->c_iflag & IGNPAR)
port->ignore_status_mask |= FE | PE;
if (termios->c_iflag & IGNBRK) {
port->ignore_status_mask |= BI;
/*
* If we're ignoring parity and break indicators,
* ignore overruns too (for real raw support).
*/
if (termios->c_iflag & IGNPAR)
port->ignore_status_mask |= OE;
}
baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
quot = uart_get_divisor(port, baud);
spin_lock_irqsave(&uart->port.lock, flags);
UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
/* Disable UART */
ier = UART_GET_IER(uart);
UART_DISABLE_INTS(uart);
/* Set DLAB in LCR to Access DLL and DLH */
UART_SET_DLAB(uart);
UART_PUT_DLL(uart, quot & 0xFF);
UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
SSYNC();
/* Clear DLAB in LCR to Access THR RBR IER */
UART_CLEAR_DLAB(uart);
UART_PUT_LCR(uart, lcr);
/* Enable UART */
UART_ENABLE_INTS(uart, ier);
val = UART_GET_GCTL(uart);
val |= UCEN;
UART_PUT_GCTL(uart, val);
/* Port speed changed, update the per-port timeout. */
uart_update_timeout(port, termios->c_cflag, baud);
spin_unlock_irqrestore(&uart->port.lock, flags);
}
static int bfin_sir_set_speed(struct bfin_sir_port *port, int speed)
{
int ret = -EINVAL;
unsigned int quot;
unsigned short val, lsr, lcr;
static int utime;
int count = 10;
lcr = WLS(8);
switch (speed) {
case 9600:
case 19200:
case 38400:
case 57600:
case 115200:
/*
* IRDA is not affected by anomaly 05000230, so there is no
* need to tweak the divisor like he UART driver (which will
* slightly speed up the baud rate on us).
*/
quot = (port->clk + (8 * speed)) / (16 * speed);
do {
udelay(utime);
lsr = UART_GET_LSR(port);
} while (!(lsr & TEMT) && count--);
/* The useconds for 1 bits to transmit */
utime = 1000000 / speed + 1;
/* Clear UCEN bit to reset the UART state machine
* and control registers
*/
val = UART_GET_GCTL(port);
val &= ~UCEN;
UART_PUT_GCTL(port, val);
/* Set DLAB in LCR to Access THR RBR IER */
UART_SET_DLAB(port);
SSYNC();
UART_PUT_DLL(port, quot & 0xFF);
UART_PUT_DLH(port, (quot >> 8) & 0xFF);
SSYNC();
/* Clear DLAB in LCR */
UART_CLEAR_DLAB(port);
SSYNC();
UART_PUT_LCR(port, lcr);
val = UART_GET_GCTL(port);
val |= UCEN;
UART_PUT_GCTL(port, val);
ret = 0;
break;
default:
printk(KERN_WARNING "bfin_sir: Invalid speed %d\n", speed);
break;
}
val = UART_GET_GCTL(port);
/* If not add the 'RPOLC', we can't catch the receive interrupt.
* It's related with the HW layout and the IR transiver.
*/
val |= UMOD_IRDA | RPOLC;
UART_PUT_GCTL(port, val);
return ret;
}
