static void
imx_watchdog(void *arg, u_int cmd, int *error)
{
struct imx_wdog_softc *sc;
uint16_t reg;
u_int timeout;
sc = arg;
mtx_lock(&sc->sc_mtx);
if (cmd == 0) {
if (bootverbose)
device_printf(sc->sc_dev, "Can not be disabled.\n");
*error = EOPNOTSUPP;
} else {
timeout = (u_int)((1ULL << (cmd & WD_INTERVAL)) / 1000000000U);
if (timeout > 1 && timeout < 128) {
if (timeout != sc->sc_timeout) {
sc->sc_timeout = timeout;
reg = RD2(sc, WDOG_CR_REG);
reg &= ~WDOG_CR_WT_MASK;
reg |= (timeout << (WDOG_CR_WT_SHIFT + 1)) &
WDOG_CR_WT_MASK;
WR2(sc, WDOG_CR_REG, reg | WDOG_CR_WDE);
}
/* Refresh counter */
WR2(sc, WDOG_SR_REG, WDOG_SR_STEP1);
WR2(sc, WDOG_SR_REG, WDOG_SR_STEP2);
*error = 0;
}
}
mtx_unlock(&sc->sc_mtx);
}
static void
sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
{
uint32_t clk_base;
uint32_t clk_sel;
uint32_t res;
uint16_t clk;
uint16_t div;
int timeout;
if (clock == slot->clock)
return;
slot->clock = clock;
/* Turn off the clock. */
clk = RD2(slot, SDHCI_CLOCK_CONTROL);
WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
/* If no clock requested - left it so. */
if (clock == 0)
return;
/* Determine the clock base frequency */
clk_base = slot->max_clk;
if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) {
clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & BCM577XX_CTRL_CLKSEL_MASK;
/* Select clock source appropriate for the requested frequency. */
if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) {
clk_base = BCM577XX_ALT_CLOCK_BASE;
clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << BCM577XX_CTRL_CLKSEL_SHIFT);
} else {
clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << BCM577XX_CTRL_CLKSEL_SHIFT);
}
WR2(slot, BCM577XX_HOST_CONTROL, clk_sel);
}
/* Recalculate timeout clock frequency based on the new sd clock. */
if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
slot->timeout_clk = slot->clock / 1000;
if (slot->version < SDHCI_SPEC_300) {
/* Looking for highest freq <= clock. */
res = clk_base;
for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
if (res <= clock)
break;
res >>= 1;
}
/* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
div >>= 1;
}
static void
sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
{
uint32_t res;
uint16_t clk;
uint16_t div;
int timeout;
if (clock == slot->clock)
return;
slot->clock = clock;
/* Turn off the clock. */
WR2(slot, SDHCI_CLOCK_CONTROL, 0);
/* If no clock requested - left it so. */
if (clock == 0)
return;
if (slot->version < SDHCI_SPEC_300) {
/* Looking for highest freq <= clock. */
res = slot->max_clk;
for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
if (res <= clock)
break;
res >>= 1;
}
/* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
div >>= 1;
}
static void
sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
{
uint32_t res;
uint16_t clk;
uint16_t div;
int timeout;
if (clock == slot->clock)
return;
slot->clock = clock;
/* Turn off the clock. */
clk = RD2(slot, SDHCI_CLOCK_CONTROL);
WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
/* If no clock requested - left it so. */
if (clock == 0)
return;
/* Recalculate timeout clock frequency based on the new sd clock. */
if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
slot->timeout_clk = slot->clock / 1000;
if (slot->version < SDHCI_SPEC_300) {
/* Looking for highest freq <= clock. */
res = slot->max_clk;
for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
if (res <= clock)
break;
res >>= 1;
}
/* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
div >>= 1;
}
static void
ffec_miigasket_setup(struct ffec_softc *sc)
{
uint32_t ifmode;
/*
* We only need the gasket for MII and RMII connections on certain SoCs.
*/
switch (sc->fectype & FECTYPE_MASK)
{
case FECTYPE_IMX53:
break;
default:
return;
}
switch (sc->phy_conn_type)
{
case PHY_CONN_MII:
ifmode = 0;
break;
case PHY_CONN_RMII:
ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII;
break;
default:
return;
}
/*
* Disable the gasket, configure for either MII or RMII, then enable.
*/
WR2(sc, FEC_MIIGSK_ENR, 0);
while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)
continue;
WR2(sc, FEC_MIIGSK_CFGR, ifmode);
WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN);
while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY))
continue;
}
