nsresult nsZipHeader::WriteFileHeader(nsIOutputStream *aStream)
{
NS_ASSERTION(mInited, "Not initalised");
PRUint8 buf[ZIP_FILE_HEADER_SIZE];
PRUint32 pos = 0;
WRITE32(buf, &pos, ZIP_FILE_HEADER_SIGNATURE);
WRITE16(buf, &pos, mVersionNeeded);
WRITE16(buf, &pos, mFlags);
WRITE16(buf, &pos, mMethod);
WRITE16(buf, &pos, mTime);
WRITE16(buf, &pos, mDate);
WRITE32(buf, &pos, mCRC);
WRITE32(buf, &pos, mCSize);
WRITE32(buf, &pos, mUSize);
WRITE16(buf, &pos, mName.Length());
WRITE16(buf, &pos, mLocalFieldLength);
nsresult rv = ZW_WriteData(aStream, (const char *)buf, pos);
NS_ENSURE_SUCCESS(rv, rv);
rv = ZW_WriteData(aStream, mName.get(), mName.Length());
NS_ENSURE_SUCCESS(rv, rv);
if (mLocalFieldLength)
{
rv = ZW_WriteData(aStream, (const char *)mLocalExtraField.get(), mLocalFieldLength);
NS_ENSURE_SUCCESS(rv, rv);
}
return NS_OK;
}
void threadFunc_RTcore_DivideB(void *param)
{
ST_RTcore *pRTcore = (ST_RTcore*) param;;
epicsThreadId pthreadInfo;
#if USE_CPU_AFFINITY_RT
pthreadInfo = epicsThreadGetIdSelf();
/* printf("%s: EPICS ID %p, pthreadID %lu\n", pthreadInfo->name, (void *)pthreadInfo, (unsigned long)pthreadInfo->tid); */
epicsThreadSetCPUAffinity( pthreadInfo, AFFINITY_RTCORE_DivB);
epicsThreadSetPosixPriority(pthreadInfo, PRIOTY_RTCORE_DivB, "SCHED_FIFO");
#endif
epicsThreadSleep(1.0);
while(TRUE) {
epicsEventWait( pRTcore->ST_DivThreadB.threadEventId);
#if USE_RTCORE_DivB_HIGH
WRITE32(pRTcore->base0 + 0x4, 0x1);
#endif
#if USE_RTCORE_DivB_LOW
WRITE32(pRTcore->base0 + 0x4, 0x0);
#endif
}
}
static int _hsmci_shutdown (SIM_HBA *hba)
{
CONFIG_INFO *cfg;
SIM_MMC_EXT *ext;
hsmci_ext_t *hsmci;
uintptr_t base;
ext = (SIM_MMC_EXT *)hba->ext;
cfg = (CONFIG_INFO *)&hba->cfg;
hsmci = (hsmci_ext_t *)ext->handle;
base = hsmci->base;
/* Reset and disable controller */
WRITE32 (MCI_CR, SWRST|PWSDIS);
delay (100);
WRITE32 (MCI_CR, MCIDIS | PWSDIS);
/* Indicate we are done with DMA lib */
dmac_fini(hsmci->dmac_dev);
munmap_device_memory ((void *)pioa_pdsr, 4);
munmap_device_memory ((void *)hsmci->base, cfg->MemLength[0]);
munmap_device_io (hsmci->pio_base, AT91SAM9G45_PIO_SIZE);
munmap_device_io (hsmci->pmc_base, PMC_SIZE);
free(hsmci);
return (MMC_SUCCESS);
}
void
evgEvtClk::setFracSynFreq(epicsFloat64 freq) {
epicsUInt32 controlWord, oldControlWord;
epicsFloat64 error;
controlWord = FracSynthControlWord (freq, MRF_FRAC_SYNTH_REF, 0, &error);
if ((!controlWord) || (error > 100.0)) {
char err[80];
sprintf(err, "Cannot set event clock speed to %f MHz.\n", freq);
std::string strErr(err);
throw std::runtime_error(strErr);
}
oldControlWord=READ32(m_pReg, FracSynthWord);
/* Changing the control word disturbes the phase of the synthesiser
which will cause a glitch. Don't change the control word unless needed.*/
if(controlWord != oldControlWord){
WRITE32(m_pReg, FracSynthWord, controlWord);
epicsUInt32 uSecDivider = (epicsUInt16)freq;
WRITE32(m_pReg, uSecDiv, uSecDivider);
}
m_fracSynFreq = FracSynthAnalyze(READ32(m_pReg, FracSynthWord), 24.0, 0);
}
/* void close (); */
NS_IMETHODIMP nsZipWriter::Close()
{
if (!mStream)
return NS_ERROR_NOT_INITIALIZED;
if (mInQueue)
return NS_ERROR_IN_PROGRESS;
if (mCDSDirty) {
PRUint32 size = 0;
for (PRInt32 i = 0; i < mHeaders.Count(); i++) {
nsresult rv = mHeaders[i]->WriteCDSHeader(mStream);
if (NS_FAILED(rv)) {
Cleanup();
return rv;
}
size += mHeaders[i]->GetCDSHeaderLength();
}
char buf[ZIP_EOCDR_HEADER_SIZE];
PRUint32 pos = 0;
WRITE32(buf, &pos, ZIP_EOCDR_HEADER_SIGNATURE);
WRITE16(buf, &pos, 0);
WRITE16(buf, &pos, 0);
WRITE16(buf, &pos, mHeaders.Count());
WRITE16(buf, &pos, mHeaders.Count());
WRITE32(buf, &pos, size);
WRITE32(buf, &pos, mCDSOffset);
WRITE16(buf, &pos, mComment.Length());
nsresult rv = ZW_WriteData(mStream, buf, pos);
if (NS_FAILED(rv)) {
Cleanup();
return rv;
}
rv = ZW_WriteData(mStream, mComment.get(), mComment.Length());
if (NS_FAILED(rv)) {
Cleanup();
return rv;
}
nsCOMPtr<nsISeekableStream> seekable = do_QueryInterface(mStream);
rv = seekable->SetEOF();
if (NS_FAILED(rv)) {
Cleanup();
return rv;
}
}
nsresult rv = mStream->Close();
mStream = nsnull;
mHeaders.Clear();
mEntryHash.Clear();
mQueue.Clear();
return rv;
}
static int
encode_cb_compound_hdr(struct xdr_stream *xdr, struct nfs4_cb_compound_hdr *hdr)
{
__be32 * p;
RESERVE_SPACE(16);
WRITE32(0); /* tag length is always 0 */
WRITE32(NFS4_MINOR_VERSION);
WRITE32(hdr->ident);
WRITE32(hdr->nops);
return 0;
}
static void
encode_cb_compound_hdr(struct xdr_stream *xdr, struct nfs4_cb_compound_hdr *hdr)
{
__be32 * p;
RESERVE_SPACE(16);
WRITE32(0); /* tag length is always 0 */
WRITE32(hdr->minorversion);
WRITE32(hdr->ident);
hdr->nops_p = p;
WRITE32(hdr->nops);
}
static int
encode_cb_recall(struct xdr_stream *xdr, struct nfs4_cb_recall *cb_rec)
{
__be32 *p;
int len = cb_rec->cbr_fhlen;
RESERVE_SPACE(12+sizeof(cb_rec->cbr_stateid) + len);
WRITE32(OP_CB_RECALL);
WRITEMEM(&cb_rec->cbr_stateid, sizeof(stateid_t));
WRITE32(cb_rec->cbr_trunc);
WRITE32(len);
WRITEMEM(cb_rec->cbr_fhval, len);
return 0;
}
void Interrupt::Init()
{
this->baseRegAddr = (PBYTE)REALVIEW_PBA8_GIC_CPU_BASE;
CpuInterfaceRegs* gicc = (CpuInterfaceRegs *)this->baseRegAddr;
DistributorRegs* gicd = (DistributorRegs *)(this->baseRegAddr + (REALVIEW_PBA8_GIC_DIST_BASE - REALVIEW_PBA8_GIC_CPU_BASE));
WRITE32(GICC_ENABLE_CPU_INTERRUPT, &gicc->CpuControl);
WRITE32(GICC_PRIORITY_MASK_NONE, &gicc->PriorityMask);
WRITE32(GICD_ENABLE_INTERRUPT, &gicd->DistControl);
for(UINT i = 0 ; i < INTERRUPT_HANDLER_NUM ; i++){
this->handlers[i] = NULL;
}
}
void StartWatchdog(uint32 timeout_in_ms)
{
#if defined(CFG_MPC5567)
(void)timeout_in_ms;
ECSM.SWTCR.R = 0x00D8;
#elif defined(CFG_MPC560X)|| defined(CFG_MPC563XM)
(void)timeout_in_ms;
SWT.CR.R = 0x8000011B;
#elif defined(CFG_MPC5668)
/* Clocked by 16 MHz IRC clock */
/* Clear softlock */
WRITE32(SWT_BASE + SWT_SR, 0x0000c520);
WRITE32(SWT_BASE + SWT_SR, 0x0000d928);
/* Write TMO */
WRITE32(SWT_BASE + SWT_TO, timeout_in_ms * 16000 );
/* Enable Watchdog */
WRITE32(SWT_BASE + SWT_CR,0x80000000UL + CR_RIA + CR_SLK + CR_CSL + CR_FRZ + CR_WEN);
#elif defined(CFG_MPC5516)
/* We running on system clock, ie SIU_SYSCLK.SWTCLKSEL, so get the value */
/* The timeout is 2^x, so get best possible value
* Table for 80Mhz
* ------------------
* 2^9 = 512 = 6.4 uS
* 2^15 = 400 uS
* 2^20 = 13 mS
* 2^28 = 3.3 S
* 2^31 = 26,84 S
*
* Formula:
* 1/clock * 2^n = tmo_in_s
* 2^n = tmo_in_s * clock -> n = log2(tmo_in_s * clock) = log2(tmo_in_ms * clock / 1000 )
* */
uint32 swtVal = ilog2( McuE_GetSystemClock()/1000 * timeout_in_ms );
#if defined(CFG_WDG_TEST)
MCM.SWTCR.R = (SWTCR_SWE + SWTCR_SWRI(WDG_SWRI_VAL) + swtVal);
#else
MCM.SWTCR.R = (SWTCR_SWE + SWTCR_SWRI(2) + swtVal);
#endif
#else
MCM.SWTCR.R = 0x00D8;
#endif
}
static void
encode_cb_recall(struct xdr_stream *xdr, struct nfs4_delegation *dp,
struct nfs4_cb_compound_hdr *hdr)
{
__be32 *p;
int len = dp->dl_fh.fh_size;
RESERVE_SPACE(12+sizeof(dp->dl_stateid) + len);
WRITE32(OP_CB_RECALL);
WRITE32(dp->dl_stateid.si_generation);
WRITEMEM(&dp->dl_stateid.si_opaque, sizeof(stateid_opaque_t));
WRITE32(0); /* truncate optimization not implemented */
WRITE32(len);
WRITEMEM(&dp->dl_fh.fh_base, len);
hdr->nops++;
}
static bool
enableIRQ(mrf::Object* obj, void*) {
evgMrm *evg=dynamic_cast<evgMrm*>(obj);
if(!evg)
return true;
/**
* Enable PCIe interrputs (1<<30)
*
* Change by: tslejko
* Reason: Support for cPCI EVG
*/
WRITE32(evg->getRegAddr(), IrqEnable,
EVG_IRQ_PCIIE | //PCIe interrupt enable,
EVG_IRQ_ENABLE |
EVG_IRQ_EXT_INP |
EVG_IRQ_STOP_RAM(0) |
EVG_IRQ_STOP_RAM(1) |
EVG_IRQ_START_RAM(0) |
EVG_IRQ_START_RAM(1)
);
// WRITE32(pReg, IrqEnable,
// EVG_IRQ_ENABLE |
// EVG_IRQ_STOP_RAM1 |
// EVG_IRQ_STOP_RAM0 |
// EVG_IRQ_START_RAM1 |
// EVG_IRQ_START_RAM0 |
// EVG_IRQ_EXT_INP |
// EVG_IRQ_DBUFF |
// EVG_IRQ_FIFO |
// EVG_IRQ_RXVIO
// );
return true;
}
static void I486OP(cmpxchg_rm32_r32)(i386_state *cpustate) // Opcode 0x0f b1
{
UINT8 modrm = FETCH(cpustate);
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
UINT32 src = LOAD_REG32(modrm);
if( REG32(EAX) == dst ) {
STORE_RM32(modrm, src);
cpustate->ZF = 1;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_T);
} else {
REG32(EAX) = dst;
cpustate->ZF = 0;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_F);
}
} else {
UINT32 ea = GetEA(cpustate,modrm);
UINT32 dst = READ32(cpustate,ea);
UINT32 src = LOAD_REG32(modrm);
if( REG32(EAX) == dst ) {
WRITE32(cpustate,ea, src);
cpustate->ZF = 1;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_T);
} else {
REG32(EAX) = dst;
cpustate->ZF = 0;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_F);
}
}
}
int VerifyAddingMsgPacket::putBody( unsigned char * buf )
{
int pos=0;
buf[pos++] = 0x03; /// might be sub-command
buf[pos++] = 0x01; /// might be sub of subcommand,
//*((unsigned int *)(buf+pos)) = htonl(m_BuddyTQQNum);
WRITE32(buf+pos, m_BuddyTQQNum);
pos+=4;
if(!m_CodeLen || !m_Code){
fprintf(stderr, "VerifyAddingMsgPacket: no verification code set!\n");
return 0;
}
WRITE16(buf+pos, m_CodeLen);
pos+=2;
memcpy(buf+pos, m_Code, m_CodeLen);
pos += m_CodeLen;
return pos;
}
static void
encode_cb_recall(struct xdr_stream *xdr, struct nfs4_delegation *dp,
struct nfs4_cb_compound_hdr *hdr)
{
__be32 *p;
int len = dp->dl_fh.fh_size;
RESERVE_SPACE(4);
WRITE32(OP_CB_RECALL);
encode_stateid(xdr, &dp->dl_stateid);
RESERVE_SPACE(8 + (XDR_QUADLEN(len) << 2));
WRITE32(0); /* truncate optimization not implemented */
WRITE32(len);
WRITEMEM(&dp->dl_fh.fh_base, len);
hdr->nops++;
}
void
evgMxc::setPrescaler(epicsUInt32 preScaler) {
if(preScaler == 0 || preScaler == 1)
throw std::runtime_error("Invalid preScaler value in Multiplexed Counter. Value should not be 0 or 1.");
WRITE32(m_pReg, MuxPrescaler(m_id), preScaler);
}
void i386_device::i486_cmpxchg_rm32_r32() // Opcode 0x0f b1
{
UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
UINT32 src = LOAD_REG32(modrm);
if( REG32(EAX) == dst ) {
STORE_RM32(modrm, src);
m_ZF = 1;
CYCLES(CYCLES_CMPXCHG_REG_REG_T);
} else {
REG32(EAX) = dst;
m_ZF = 0;
CYCLES(CYCLES_CMPXCHG_REG_REG_F);
}
} else {
UINT32 ea = GetEA(modrm,0);
UINT32 dst = READ32(ea);
UINT32 src = LOAD_REG32(modrm);
if( REG32(EAX) == dst ) {
WRITE32(ea, src);
m_ZF = 1;
CYCLES(CYCLES_CMPXCHG_REG_MEM_T);
} else {
REG32(EAX) = dst;
m_ZF = 0;
CYCLES(CYCLES_CMPXCHG_REG_MEM_F);
}
}
}
static void _hsmci_reset(SIM_HBA *hba)
{
SIM_MMC_EXT *ext;
hsmci_ext_t *hsmci;
uintptr_t base;
ext = (SIM_MMC_EXT *)hba->ext;
hsmci = (hsmci_ext_t *)ext->handle;
base = hsmci->base;
int dtor = READ32(MCI_DTOR);
int mr = READ32(MCI_MR);
int sdcr = READ32(MCI_SDCR);
/* Reset and disable controller */
WRITE32 (MCI_CR, SWRST|PWSDIS);
delay (100);
WRITE32 (MCI_CR, MCIDIS | PWSDIS | MCIEN);
WRITE32(MCI_DMA, (READ32(MCI_DMA) & (~(DMAEN))));
WRITE32 (MCI_IDR, 0xffffffff);
WRITE32(MCI_DTOR, dtor);
WRITE32(MCI_MR, mr);
WRITE32(MCI_SDCR, sdcr);
}
void
evgMrm::isr(void* arg) {
evgMrm *evg = (evgMrm*)(arg);
epicsUInt32 flags = READ32(evg->m_pReg, IrqFlag);
epicsUInt32 enable = READ32(evg->m_pReg, IrqEnable);
epicsUInt32 active = flags & enable;
if(!active)
return;
if(active & EVG_IRQ_STOP_RAM(0)) {
if(evg->irqStop0_queued==0) {
callbackRequest(&evg->irqStop0_cb);
evg->irqStop0_queued=1;
} else if(evg->irqStop0_queued==1) {
WRITE32(evg->getRegAddr(), IrqEnable, enable & ~EVG_IRQ_STOP_RAM(0));
evg->irqStop0_queued=2;
}
}
if(active & EVG_IRQ_STOP_RAM(1)) {
if(evg->irqStop1_queued==0) {
callbackRequest(&evg->irqStop1_cb);
evg->irqStop1_queued=1;
} else if(evg->irqStop1_queued==1) {
WRITE32(evg->getRegAddr(), IrqEnable, enable & ~EVG_IRQ_STOP_RAM(1));
evg->irqStop1_queued=2;
}
}
if(active & EVG_IRQ_EXT_INP) {
if(evg->irqExtInp_queued==0) {
callbackRequest(&evg->irqExtInp_cb);
evg->irqExtInp_queued=1;
} else if(evg->irqExtInp_queued==1) {
WRITE32(evg->getRegAddr(), IrqEnable, enable & ~EVG_IRQ_EXT_INP);
evg->irqExtInp_queued=2;
}
}
WRITE32(evg->m_pReg, IrqFlag, flags); // Clear the interrupt causes
READ32(evg->m_pReg, IrqFlag); // Make sure the clear completes before returning
return;
}
void
MRMCML::reset(bool s)
{
if(s)
shadowEnable |= OutputCMLEna_rst;
else
shadowEnable &= ~OutputCMLEna_rst;
WRITE32(base, OutputCMLEna(N), shadowEnable);
}
static void
encode_stateid(struct xdr_stream *xdr, stateid_t *sid)
{
__be32 *p;
RESERVE_SPACE(sizeof(stateid_t));
WRITE32(sid->si_generation);
WRITEMEM(&sid->si_opaque, sizeof(stateid_opaque_t));
}
void
MRMCML::setRecyclePat(bool s)
{
if(s)
shadowEnable |= OutputCMLEna_cycl;
else
shadowEnable &= ~OutputCMLEna_cycl;
WRITE32(base, OutputCMLEna(N), shadowEnable);
}
void
MRMCML::setFineDelay(double v)
{
if(v>1024.0){
printf("Delay will be set to 1024 instead of %f\n", v);
v=1024.0;
}
WRITE32(base, GTXDelay(N), roundToUInt(v*1024.0));
}
void
MRMCML::power(bool s)
{
if(!s)
shadowEnable |= OutputCMLEna_pow;
else
shadowEnable &= ~OutputCMLEna_pow;
WRITE32(base, OutputCMLEna(N), shadowEnable);
}
void
MRMCML::enable(bool s)
{
if(s)
shadowEnable |= OutputCMLEna_ena;
else
shadowEnable &= ~OutputCMLEna_ena;
WRITE32(base, OutputCMLEna(N), shadowEnable);
}
void
MRMCML::setPolarityInvert(bool s)
{
if(s)
shadowEnable |= OutputCMLEna_ftrg;
else
shadowEnable &= ~OutputCMLEna_ftrg;
WRITE32(base, OutputCMLEna(N), shadowEnable);
}
/*
2560
4 words per
4 *p
10240
4k bytes per page
4096/p
2.50
1700 lines
1700 * p
4250.00
PTEs
*/
static void
setgtt(int start, int end, unsigned long base, int inc)
{
int i;
for(i = start; i < end; i++){
u32 word = base + i*inc;
WRITE32(word|1,(i*4)|1);
}
}
void
MRMCML::setCountLow (epicsUInt32 v)
{
v = std::max(kind==typeTG300?40u:20u, std::min(v, 65535u));
epicsUInt32 val = READ32(base, OutputCMLCount(N));
val &= ~(OutputCMLCount_mask << OutputCMLCount_low_shft);
val |= v << OutputCMLCount_low_shft;
WRITE32(base, OutputCMLCount(N), val);
}
/*
* @brief Output a character to serial port
*
* @param dev UART device struct
* @param c character to output
*/
unsigned char uart_gnss_poll_out(struct device *dev, unsigned char c)
{
/* wait for transmitter to ready to accept a character */
uint32_t status = READ32(&__UART1->status);
while (status & UART_STATUS_TX_FULL) {
status = READ32(&__UART1->status);
}
WRITE32(&__UART1->data, c);
return c;
}
void
MRMCML::setCountInit (epicsUInt32 v)
{
v = std::min(v, 65535u);
v <<= OutputCMLEna_ftrig_shft;
shadowEnable &= ~OutputCMLEna_ftrig_mask;
shadowEnable |= v;
WRITE32(base, OutputCMLEna(N), shadowEnable);
}
