void clk_switch(int flag)
{
int i;
if (flag) {
for (i = CLK_COUNT - 1; i >= 0; i--) {
if (clk_flag[i]) {
if ((clks[i] == HHI_VID_CLK_CNTL)||(clks[i] == HHI_VIID_CLK_CNTL)) {
WRITE_CBUS_REG_BITS(clks[i], clk_flag[i], 19, 2);
} else if (clks[i] == HHI_MPEG_CLK_CNTL) {
udelay(1000);
SET_CBUS_REG_MASK(clks[i], (1 << 8)); // normal
CLEAR_CBUS_REG_MASK(UART0_CONTROL, (1 << 19) | 0xFFF);
SET_CBUS_REG_MASK(UART0_CONTROL, (((uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
CLEAR_CBUS_REG_MASK(UART1_CONTROL, (1 << 19) | 0xFFF);
SET_CBUS_REG_MASK(UART1_CONTROL, (((uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
CLEAR_AOBUS_REG_MASK(AO_UART_CONTROL, (1 << 19) | 0xFFF);
WRITE_AOBUS_REG_BITS(AO_UART_CONTROL, ((uart_rate_backup / (115200 * 4)) - 1) & 0xfff, 0, 12);
} else {
SET_CBUS_REG_MASK(clks[i], (1 << 8));
}
clk_flag[i] = 0;
printf("clk %s(%x) on\n", clks_name[i], clks[i]);
}
}
} else {
for (i = 0; i < CLK_COUNT; i++) {
if ((clks[i] == HHI_VID_CLK_CNTL)||(clks[i] == HHI_VIID_CLK_CNTL)) {
clk_flag[i] = READ_CBUS_REG_BITS(clks[i], 19, 2);
if (clk_flag[i]) {
CLEAR_CBUS_REG_MASK(clks[i], (1<<19)|(1<<20));
}
} else if (clks[i] == HHI_MPEG_CLK_CNTL) {
if (READ_CBUS_REG(clks[i]) & (1 << 8)) {
clk_flag[i] = 1;
udelay(1000);
CLEAR_CBUS_REG_MASK(clks[i], (1 << 8)); // 24M
CLEAR_CBUS_REG_MASK(UART0_CONTROL, (1 << 19) | 0xFFF);
SET_CBUS_REG_MASK(UART0_CONTROL, (((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
CLEAR_CBUS_REG_MASK(UART1_CONTROL, (1 << 19) | 0xFFF);
SET_CBUS_REG_MASK(UART1_CONTROL, (((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
CLEAR_AOBUS_REG_MASK(AO_UART_CONTROL, (1 << 19) | 0xFFF);
WRITE_AOBUS_REG_BITS(AO_UART_CONTROL, ((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff, 0, 12);
}
} else {
clk_flag[i] = READ_CBUS_REG_BITS(clks[i], 8, 1) ? 1 : 0;
if (clk_flag[i]) {
CLEAR_CBUS_REG_MASK(clks[i], (1 << 8));
}
}
if (clk_flag[i]) {
printf("clk %s(%x) off\n", clks_name[i], clks[i]);
}
}
}
}
void amvdec_stop(void)
{
ulong timeout = jiffies + HZ;
struct clk *sys_clk;
WRITE_MPEG_REG(MPSR, 0);
WRITE_MPEG_REG(CPSR, 0);
while (READ_MPEG_REG(IMEM_DMA_CTRL) & 0x8000) {
if (time_after(jiffies, timeout)) {
break;
}
}
WRITE_MPEG_REG(RESET0_REGISTER, RESET_VCPU | RESET_CCPU);
/* additional cbus dummy register reading for timing control */
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
#if 0
sys_clk = clk_get_sys("clk81", NULL);
if (sys_clk){
clk_set_rate(sys_clk, sys_clk_rate);
CLEAR_AOBUS_REG_MASK(AO_UART_CONTROL, (1 << 19) | 0xFFF);
WRITE_AOBUS_REG_BITS(AO_UART_CONTROL, ((sys_clk_rate / (115200 * 4)) - 1) & 0xfff, 0, 12);
}
#endif
#ifdef CONFIG_WAKELOCK
amvdec_wake_unlock();
#endif
}
void amvdec_start(void)
{
struct clk *sys_clk;
#ifdef CONFIG_WAKELOCK
amvdec_wake_lock();
#endif
#if 0
sys_clk = clk_get_sys("clk81", NULL);
if (sys_clk){
sys_clk_rate = clk_get_rate(sys_clk);
clk_set_rate(sys_clk, 192000000);
CLEAR_AOBUS_REG_MASK(AO_UART_CONTROL, (1 << 19) | 0xFFF);
WRITE_AOBUS_REG_BITS(AO_UART_CONTROL, ((192000000 / (115200 * 4)) - 1) & 0xfff, 0, 12);
}
#endif
/* additional cbus dummy register reading for timing control */
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
WRITE_MPEG_REG(RESET0_REGISTER, RESET_VCPU | RESET_CCPU);
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
WRITE_MPEG_REG(MPSR, 0x0001);
}
void early_clk_switch(int flag)
{
int i;
struct clk *sys_clk;
if (flag) {
for (i = EARLY_CLK_COUNT - 1; i >= 0; i--) {
if (early_clk_flag[i]) {
if ((early_clks[i] == HHI_VID_CLK_CNTL)||(early_clks[i] == HHI_VIID_CLK_CNTL)) {
WRITE_CBUS_REG_BITS(early_clks[i], early_clk_flag[i], 19, 2);
}
#ifdef EARLY_SUSPEND_USE_XTAL
else if (early_clks[i] == HHI_MPEG_CLK_CNTL) {
udelay(1000);
SET_CBUS_REG_MASK(early_clks[i], (1 << 8)); // clk81 back to normal
CLEAR_CBUS_REG_MASK(UART0_CONTROL, (1 << 19) | 0xFFF);
SET_CBUS_REG_MASK(UART0_CONTROL, (((uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
CLEAR_CBUS_REG_MASK(UART1_CONTROL, (1 << 19) | 0xFFF);
SET_CBUS_REG_MASK(UART1_CONTROL, (((uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
CLEAR_AOBUS_REG_MASK(AO_UART_CONTROL, (1 << 19) | 0xFFF);
WRITE_AOBUS_REG_BITS(AO_UART_CONTROL, ((uart_rate_backup / (115200 * 4)) - 1) & 0xfff, 0, 12);
}
#endif
else {
SET_CBUS_REG_MASK(early_clks[i], (1 << 8));
}
printf("late clk %s(%x) on\n", early_clks_name[i], early_clks[i]);
early_clk_flag[i] = 0;
}
}
} else {
//sys_clk = clk_get_sys("clk81", NULL);
uart_rate_backup = 200*1000*1000;//sys_clk->rate;
//sys_clk = clk_get_sys("clk_xtal", NULL);
xtal_uart_rate_backup = 24*1000*1000;//sys_clk->rate;
for (i = 0; i < EARLY_CLK_COUNT; i++) {
if ((early_clks[i] == HHI_VID_CLK_CNTL)||(early_clks[i] == HHI_VIID_CLK_CNTL)) {
early_clk_flag[i] = READ_CBUS_REG_BITS(early_clks[i], 19, 2);
if (early_clk_flag[i]) {
CLEAR_CBUS_REG_MASK(early_clks[i], (1<<19)|(1<<20));
}
}
#ifdef EARLY_SUSPEND_USE_XTAL
else if (early_clks[i] == HHI_MPEG_CLK_CNTL) {
early_clk_flag[i] = 1;
udelay(1000);
CLEAR_CBUS_REG_MASK(early_clks[i], (1 << 8)); // 24M
CLEAR_CBUS_REG_MASK(UART0_CONTROL, (1 << 19) | 0xFFF);
SET_CBUS_REG_MASK(UART0_CONTROL, (((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
CLEAR_CBUS_REG_MASK(UART1_CONTROL, (1 << 19) | 0xFFF);
SET_CBUS_REG_MASK(UART1_CONTROL, (((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
CLEAR_AOBUS_REG_MASK(AO_UART_CONTROL, (1 << 19) | 0xFFF);
WRITE_AOBUS_REG_BITS(AO_UART_CONTROL, ((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff, 0, 12);
}
#endif
else {
early_clk_flag[i] = READ_CBUS_REG_BITS(early_clks[i], 8, 1) ? 1 : 0;
if (early_clk_flag[i]) {
CLEAR_CBUS_REG_MASK(early_clks[i], (1 << 8));
}
}
if (early_clk_flag[i]) {
printf("early clk %s(%x) off\n", early_clks_name[i], early_clks[i]);
}
}
}
}
