// iec958 and i2s clock are separated after M6TV. Use PLL2 for i2s DAC & ADC clock
void audio_set_i2s_clk(unsigned freq, unsigned fs_config)
{
int i;
int xtal = 0;
int (*audio_clock_config)[2];
int index=0;
switch(freq)
{
case AUDIO_CLK_FREQ_192:
index=4;
break;
case AUDIO_CLK_FREQ_96:
index=3;
break;
case AUDIO_CLK_FREQ_48:
index=2;
break;
case AUDIO_CLK_FREQ_441:
index=1;
break;
case AUDIO_CLK_FREQ_32:
index=0;
break;
case AUDIO_CLK_FREQ_8:
index = 5;
break;
case AUDIO_CLK_FREQ_11:
index = 6;
break;
case AUDIO_CLK_FREQ_12:
index = 7;
break;
case AUDIO_CLK_FREQ_16:
index = 8;
break;
case AUDIO_CLK_FREQ_22:
index = 9;
break;
case AUDIO_CLK_FREQ_24:
index = 10;
break;
default:
index=0;
break;
};
if (fs_config == AUDIO_CLK_256FS) {
// divide 256
xtal = 0;
}
else if (fs_config == AUDIO_CLK_384FS) {
// divide 384
xtal = 1;
}
audio_clock_config = audio_clock_config_table[xtal];
// gate the clock off
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 8));
WRITE_MPEG_REG(AIU_CLK_CTRL_MORE, 0);
//Set filter register
//WRITE_MPEG_REG(HHI_MPLL_CNTL3, 0x26e1250);
/*--- DAC clock configuration--- */
// Disable mclk
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 0, 8, 1);
// Select clk source, 0=ddr_pll; 1=Multi-Phase PLL0; 2=Multi-Phase PLL1; 3=Multi-Phase PLL2.
WRITE_MPEG_REG_BITS( HHI_AUD_CLK_CNTL, 3, 9, 2);
// Configure Multi-Phase PLL2
WRITE_MPEG_REG(HHI_MPLL_CNTL9, audio_clock_config[index][0]);
// Set the XD value
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, audio_clock_config[index][1], 0, 8);
WRITE_MPEG_REG_BITS(AIU_CODEC_DAC_LRCLK_CTRL, 64-1, 0, 12);//set codec dac ratio---lrclk--64fs
// delay 5uS
//udelay(5);
for (i = 0; i < 500000; i++) ;
// gate the clock on
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1 << 8));
//Audio DAC Clock enable
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) |(1<<23));
/* ---ADC clock configuration--- */
// Disable mclk
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 0, 8, 1);
// Select clk source, 0=ddr_pll; 1=Multi-Phase PLL0; 2=Multi-Phase PLL1; 3=Multi-Phase PLL2.
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 3, 9, 2);
// Set pll over mclk ratio
//we want 256fs ADC MLCK,so for over clock mode,divide more 2 than I2S DAC CLOCK
#if OVERCLOCK == 0
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, audio_clock_config[index][1], 0, 8);
#else
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, (audio_clock_config[index][1]+1)*2-1, 0, 8);
#endif
// Set mclk over sclk ratio
WRITE_MPEG_REG_BITS(AIU_CLK_CTRL_MORE, 4-1, 8, 6);
// Set sclk over lrclk ratio
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12); //set codec adc ratio---lrclk--64fs
// Enable sclk
WRITE_MPEG_REG_BITS(AIU_CLK_CTRL_MORE, 1, 14, 1);
// Enable mclk
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 1, 8, 1);
// delay 2uS
//udelay(2);
for (i = 0; i < 200000; i++) ;
}
static irqreturn_t tsdemux_isr(int irq, void *dev_id)
{
#ifndef ENABLE_DEMUX_DRIVER
u32 int_status = READ_MPEG_REG(STB_INT_STATUS);
#else
int id = (int)dev_id;
u32 int_status = id ? READ_MPEG_REG(STB_INT_STATUS_2) : READ_MPEG_REG(STB_INT_STATUS);
#endif
if (int_status & (1 << NEW_PDTS_READY)) {
#ifndef ENABLE_DEMUX_DRIVER
u32 pdts_status = READ_MPEG_REG(STB_PTS_DTS_STATUS);
if (pdts_status & (1 << VIDEO_PTS_READY))
pts_checkin_wrptr(PTS_TYPE_VIDEO,
READ_MPEG_REG(VIDEO_PDTS_WR_PTR),
READ_MPEG_REG(VIDEO_PTS_DEMUX));
if (pdts_status & (1 << AUDIO_PTS_READY))
pts_checkin_wrptr(PTS_TYPE_AUDIO,
READ_MPEG_REG(AUDIO_PDTS_WR_PTR),
READ_MPEG_REG(AUDIO_PTS_DEMUX));
WRITE_MPEG_REG(STB_PTS_DTS_STATUS, pdts_status);
#else
#define DMX_READ_REG(i,r)\
((i)?((i==1)?READ_MPEG_REG(r##_2):READ_MPEG_REG(r##_3)):READ_MPEG_REG(r))
u32 pdts_status = DMX_READ_REG(id, STB_PTS_DTS_STATUS);
if (pdts_status & (1 << VIDEO_PTS_READY))
pts_checkin_wrptr(PTS_TYPE_VIDEO,
DMX_READ_REG(id, VIDEO_PDTS_WR_PTR),
DMX_READ_REG(id, VIDEO_PTS_DEMUX));
if (pdts_status & (1 << AUDIO_PTS_READY))
pts_checkin_wrptr(PTS_TYPE_AUDIO,
DMX_READ_REG(id, AUDIO_PDTS_WR_PTR),
DMX_READ_REG(id, AUDIO_PTS_DEMUX));
if (id == 1) {
WRITE_MPEG_REG(STB_PTS_DTS_STATUS_2, pdts_status);
} else if (id == 2){
WRITE_MPEG_REG(STB_PTS_DTS_STATUS_3, pdts_status);
} else {
WRITE_MPEG_REG(STB_PTS_DTS_STATUS, pdts_status);
}
#endif
}
if (int_status & (1 << DIS_CONTINUITY_PACKET)) {
discontinued_counter++;
//printk("discontinued counter=%d\n",discontinued_counter);
}
if (int_status & (1 << SUB_PES_READY)) {
/* TODO: put data to somewhere */
//printk("subtitle pes ready\n");
wakeup_sub_poll();
}
#ifndef ENABLE_DEMUX_DRIVER
WRITE_MPEG_REG(STB_INT_STATUS, int_status);
#endif
return IRQ_HANDLED;
}
static s32 amvdec_loadmc(const u32 *p)
{
ulong timeout;
s32 ret = 0;
#ifdef AMVDEC_USE_STATIC_MEMORY
if (mc_addr == NULL) {
#else
{
#endif
mc_addr = kmalloc(MC_SIZE, GFP_KERNEL);
}
if (!mc_addr)
return -ENOMEM;
memcpy(mc_addr, p, MC_SIZE);
mc_addr_map = dma_map_single(amports_get_dma_device(),
mc_addr, MC_SIZE, DMA_TO_DEVICE);
WRITE_VREG(MPSR, 0);
WRITE_VREG(CPSR, 0);
/* Read CBUS register for timing */
timeout = READ_VREG(MPSR);
timeout = READ_VREG(MPSR);
timeout = jiffies + HZ;
WRITE_VREG(IMEM_DMA_ADR, mc_addr_map);
WRITE_VREG(IMEM_DMA_COUNT, 0x1000);
WRITE_VREG(IMEM_DMA_CTRL, (0x8000 | (7 << 16)));
while (READ_VREG(IMEM_DMA_CTRL) & 0x8000) {
if (time_before(jiffies, timeout))
schedule();
else {
pr_err("vdec load mc error\n");
ret = -EBUSY;
break;
}
}
dma_unmap_single(amports_get_dma_device(),
mc_addr_map, MC_SIZE, DMA_TO_DEVICE);
#ifndef AMVDEC_USE_STATIC_MEMORY
kfree(mc_addr);
mc_addr = NULL;
#endif
return ret;
}
s32 amvdec_loadmc_ex(enum vformat_e type, const char *name, char *def)
{
return am_loadmc_ex(type, name, def, &amvdec_loadmc);
}
static s32 amvdec2_loadmc(const u32 *p)
{
if (has_vdec2()) {
ulong timeout;
s32 ret = 0;
#ifdef AMVDEC_USE_STATIC_MEMORY
if (mc_addr == NULL) {
#else
{
#endif
mc_addr = kmalloc(MC_SIZE, GFP_KERNEL);
}
if (!mc_addr)
return -ENOMEM;
memcpy(mc_addr, p, MC_SIZE);
mc_addr_map = dma_map_single(amports_get_dma_device(),
mc_addr, MC_SIZE, DMA_TO_DEVICE);
WRITE_VREG(VDEC2_MPSR, 0);
WRITE_VREG(VDEC2_CPSR, 0);
/* Read CBUS register for timing */
timeout = READ_VREG(VDEC2_MPSR);
timeout = READ_VREG(VDEC2_MPSR);
timeout = jiffies + HZ;
WRITE_VREG(VDEC2_IMEM_DMA_ADR, mc_addr_map);
WRITE_VREG(VDEC2_IMEM_DMA_COUNT, 0x1000);
WRITE_VREG(VDEC2_IMEM_DMA_CTRL, (0x8000 | (7 << 16)));
while (READ_VREG(VDEC2_IMEM_DMA_CTRL) & 0x8000) {
if (time_before(jiffies, timeout))
schedule();
else {
pr_err("vdec2 load mc error\n");
ret = -EBUSY;
break;
}
}
dma_unmap_single(amports_get_dma_device(),
mc_addr_map, MC_SIZE, DMA_TO_DEVICE);
#ifndef AMVDEC_USE_STATIC_MEMORY
kfree(mc_addr);
mc_addr = NULL;
#endif
return ret;
} else
return 0;
}
s32 amvdec2_loadmc_ex(enum vformat_e type, const char *name, char *def)
{
if (has_vdec2())
return am_loadmc_ex(type, name, def, &amvdec2_loadmc);
else
return 0;
}
s32 amhcodec_loadmc(const u32 *p)
{
#ifdef AMVDEC_USE_STATIC_MEMORY
if (mc_addr == NULL) {
#else
{
#endif
mc_addr = kmalloc(MC_SIZE, GFP_KERNEL);
}
if (!mc_addr)
return -ENOMEM;
memcpy(mc_addr, p, MC_SIZE);
mc_addr_map = dma_map_single(amports_get_dma_device(),
mc_addr, MC_SIZE, DMA_TO_DEVICE);
WRITE_VREG(HCODEC_IMEM_DMA_ADR, mc_addr_map);
WRITE_VREG(HCODEC_IMEM_DMA_COUNT, 0x100);
WRITE_VREG(HCODEC_IMEM_DMA_CTRL, (0x8000 | (7 << 16)));
while (READ_VREG(HCODEC_IMEM_DMA_CTRL) & 0x8000)
udelay(1000);
dma_unmap_single(amports_get_dma_device(),
mc_addr_map, MC_SIZE, DMA_TO_DEVICE);
#ifndef AMVDEC_USE_STATIC_MEMORY
kfree(mc_addr);
#endif
return 0;
}
s32 amhcodec_loadmc_ex(enum vformat_e type, const char *name, char *def)
{
return am_loadmc_ex(type, name, def, &amhcodec_loadmc);
}
static s32 amhevc_loadmc(const u32 *p)
{
ulong timeout;
s32 ret = 0;
if (has_hevc_vdec()) {
#ifdef AMVDEC_USE_STATIC_MEMORY
if (mc_addr == NULL) {
#else
{
#endif
mc_addr = kmalloc(MC_SIZE, GFP_KERNEL);
}
if (!mc_addr)
return -ENOMEM;
memcpy(mc_addr, p, MC_SIZE);
mc_addr_map =
dma_map_single(amports_get_dma_device(),
mc_addr, MC_SIZE, DMA_TO_DEVICE);
WRITE_VREG(HEVC_MPSR, 0);
WRITE_VREG(HEVC_CPSR, 0);
/* Read CBUS register for timing */
timeout = READ_VREG(HEVC_MPSR);
timeout = READ_VREG(HEVC_MPSR);
timeout = jiffies + HZ;
WRITE_VREG(HEVC_IMEM_DMA_ADR, mc_addr_map);
WRITE_VREG(HEVC_IMEM_DMA_COUNT, 0x1000);
WRITE_VREG(HEVC_IMEM_DMA_CTRL, (0x8000 | (7 << 16)));
while (READ_VREG(HEVC_IMEM_DMA_CTRL) & 0x8000) {
if (time_before(jiffies, timeout))
schedule();
else {
pr_err("vdec2 load mc error\n");
ret = -EBUSY;
break;
}
}
dma_unmap_single(amports_get_dma_device(),
mc_addr_map, MC_SIZE, DMA_TO_DEVICE);
#ifndef AMVDEC_USE_STATIC_MEMORY
kfree(mc_addr);
mc_addr = NULL;
#endif
}
return ret;
}
s32 amhevc_loadmc_ex(enum vformat_e type, const char *name, char *def)
{
if (has_hevc_vdec())
return am_loadmc_ex(type, name, def, &amhevc_loadmc);
else
return 0;
}
void amvdec_start(void)
{
#ifdef CONFIG_WAKELOCK
amvdec_wake_lock();
#endif
/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M6) {
READ_VREG(DOS_SW_RESET0);
READ_VREG(DOS_SW_RESET0);
READ_VREG(DOS_SW_RESET0);
WRITE_VREG(DOS_SW_RESET0, (1 << 12) | (1 << 11));
WRITE_VREG(DOS_SW_RESET0, 0);
READ_VREG(DOS_SW_RESET0);
READ_VREG(DOS_SW_RESET0);
READ_VREG(DOS_SW_RESET0);
} else {
/* #else */
/* additional cbus dummy register reading for timing control */
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
WRITE_MPEG_REG(RESET0_REGISTER, RESET_VCPU | RESET_CCPU);
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
}
/* #endif */
WRITE_VREG(MPSR, 0x0001);
}
void amvdec2_start(void)
{
if (has_vdec2()) {
#ifdef CONFIG_WAKELOCK
amvdec_wake_lock();
#endif
READ_VREG(DOS_SW_RESET2);
READ_VREG(DOS_SW_RESET2);
READ_VREG(DOS_SW_RESET2);
WRITE_VREG(DOS_SW_RESET2, (1 << 12) | (1 << 11));
WRITE_VREG(DOS_SW_RESET2, 0);
READ_VREG(DOS_SW_RESET2);
READ_VREG(DOS_SW_RESET2);
READ_VREG(DOS_SW_RESET2);
WRITE_VREG(VDEC2_MPSR, 0x0001);
}
}
void amhcodec_start(void)
{
WRITE_VREG(HCODEC_MPSR, 0x0001);
}
void amhevc_start(void)
{
if (has_hevc_vdec()) {
#ifdef CONFIG_WAKELOCK
amvdec_wake_lock();
#endif
READ_VREG(DOS_SW_RESET3);
READ_VREG(DOS_SW_RESET3);
READ_VREG(DOS_SW_RESET3);
WRITE_VREG(DOS_SW_RESET3, (1 << 12) | (1 << 11));
WRITE_VREG(DOS_SW_RESET3, 0);
READ_VREG(DOS_SW_RESET3);
READ_VREG(DOS_SW_RESET3);
READ_VREG(DOS_SW_RESET3);
WRITE_VREG(HEVC_MPSR, 0x0001);
}
}
void amvdec_stop(void)
{
ulong timeout = jiffies + HZ;
WRITE_VREG(MPSR, 0);
WRITE_VREG(CPSR, 0);
while (READ_VREG(IMEM_DMA_CTRL) & 0x8000) {
if (time_after(jiffies, timeout))
break;
}
/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M6) {
READ_VREG(DOS_SW_RESET0);
READ_VREG(DOS_SW_RESET0);
READ_VREG(DOS_SW_RESET0);
WRITE_VREG(DOS_SW_RESET0, (1 << 12) | (1 << 11));
WRITE_VREG(DOS_SW_RESET0, 0);
READ_VREG(DOS_SW_RESET0);
READ_VREG(DOS_SW_RESET0);
READ_VREG(DOS_SW_RESET0);
} else {
/* #else */
WRITE_MPEG_REG(RESET0_REGISTER, RESET_VCPU | RESET_CCPU);
/* additional cbus dummy register reading for timing control */
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
}
/* #endif */
#ifdef CONFIG_WAKELOCK
amvdec_wake_unlock();
#endif
}
s32 tsdemux_init(u32 vid, u32 aid, u32 sid)
{
s32 r;
u32 parser_sub_start_ptr;
u32 parser_sub_end_ptr;
u32 parser_sub_rp;
parser_sub_start_ptr = READ_MPEG_REG(PARSER_SUB_START_PTR);
parser_sub_end_ptr = READ_MPEG_REG(PARSER_SUB_END_PTR);
parser_sub_rp = READ_MPEG_REG(PARSER_SUB_RP);
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER);
#ifdef ENABLE_DEMUX_DRIVER
tsdemux_reset();
#else
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER | RESET_DEMUXSTB);
WRITE_MPEG_REG(STB_TOP_CONFIG, 0);
WRITE_MPEG_REG(DEMUX_CONTROL, 0);
#endif
/* set PID filter */
printk("tsdemux video_pid = 0x%x, audio_pid = 0x%x, sub_pid = 0x%x\n",
vid, aid, sid);
#ifndef ENABLE_DEMUX_DRIVER
WRITE_MPEG_REG(FM_WR_DATA,
(((vid & 0x1fff) | (VIDEO_PACKET << 13)) << 16) |
((aid & 0x1fff) | (AUDIO_PACKET << 13)));
WRITE_MPEG_REG(FM_WR_ADDR, 0x8000);
while (READ_MPEG_REG(FM_WR_ADDR) & 0x8000) {
;
}
WRITE_MPEG_REG(FM_WR_DATA,
(((sid & 0x1fff) | (SUB_PACKET << 13)) << 16) | 0xffff);
WRITE_MPEG_REG(FM_WR_ADDR, 0x8001);
while (READ_MPEG_REG(FM_WR_ADDR) & 0x8000) {
;
}
WRITE_MPEG_REG(MAX_FM_COMP_ADDR, 1);
WRITE_MPEG_REG(STB_INT_MASK, 0);
WRITE_MPEG_REG(STB_INT_STATUS, 0xffff);
/* TS data path */
WRITE_MPEG_REG(FEC_INPUT_CONTROL, 0x7000);
WRITE_MPEG_REG(DEMUX_MEM_REQ_EN,
(1 << VIDEO_PACKET) |
(1 << AUDIO_PACKET) |
(1 << SUB_PACKET));
WRITE_MPEG_REG(DEMUX_ENDIAN,
(7 << OTHER_ENDIAN) |
(7 << BYPASS_ENDIAN) |
(0 << SECTION_ENDIAN));
WRITE_MPEG_REG(TS_HIU_CTL, 1 << USE_HI_BSF_INTERFACE);
WRITE_MPEG_REG(TS_FILE_CONFIG,
(demux_skipbyte << 16) |
(6 << DES_OUT_DLY) |
(3 << TRANSPORT_SCRAMBLING_CONTROL_ODD) |
(1 << TS_HIU_ENABLE) |
(4 << FEC_FILE_CLK_DIV));
/* enable TS demux */
WRITE_MPEG_REG(DEMUX_CONTROL, (1 << STB_DEMUX_ENABLE) | (1 << KEEP_DUPLICATE_PACKAGE));
#endif
if (fetchbuf == 0) {
printk("%s: no fetchbuf\n", __FUNCTION__);
return -ENOMEM;
}
/* hook stream buffer with PARSER */
WRITE_MPEG_REG(PARSER_VIDEO_START_PTR,
READ_MPEG_REG(VLD_MEM_VIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_VIDEO_END_PTR,
READ_MPEG_REG(VLD_MEM_VIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
WRITE_MPEG_REG(PARSER_AUDIO_START_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_AUDIO_END_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR);
WRITE_MPEG_REG(PARSER_CONFIG,
(10 << PS_CFG_PFIFO_EMPTY_CNT_BIT) |
(1 << PS_CFG_MAX_ES_WR_CYCLE_BIT) |
(16 << PS_CFG_MAX_FETCH_CYCLE_BIT));
WRITE_MPEG_REG(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_MPEG_REG_MASK(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
WRITE_MPEG_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_MPEG_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
WRITE_MPEG_REG(PARSER_SUB_START_PTR, parser_sub_start_ptr);
WRITE_MPEG_REG(PARSER_SUB_END_PTR, parser_sub_end_ptr);
WRITE_MPEG_REG(PARSER_SUB_RP, parser_sub_rp);
SET_MPEG_REG_MASK(PARSER_ES_CONTROL, (7 << ES_SUB_WR_ENDIAN_BIT) | ES_SUB_MAN_RD_PTR);
if ((r = pts_start(PTS_TYPE_VIDEO)) < 0) {
printk("Video pts start failed.(%d)\n", r);
goto err1;
}
if ((r = pts_start(PTS_TYPE_AUDIO)) < 0) {
printk("Audio pts start failed.(%d)\n", r);
goto err2;
}
r = request_irq(INT_PARSER, parser_isr,
IRQF_SHARED, "tsdemux-fetch",
(void *)tsdemux_fetch_id);
if (r) {
goto err3;
}
WRITE_MPEG_REG(PARSER_INT_STATUS, 0xffff);
WRITE_MPEG_REG(PARSER_INT_ENABLE, PARSER_INTSTAT_FETCH_CMD << PARSER_INT_HOST_EN_BIT);
WRITE_MPEG_REG(PARSER_VIDEO_HOLE, 0x400);
WRITE_MPEG_REG(PARSER_AUDIO_HOLE, 0x400);
discontinued_counter = 0;
#ifndef ENABLE_DEMUX_DRIVER
r = request_irq(INT_DEMUX, tsdemux_isr,
IRQF_SHARED, "tsdemux-irq",
(void *)tsdemux_irq_id);
WRITE_MPEG_REG(STB_INT_MASK,
(1 << SUB_PES_READY)
| (1 << NEW_PDTS_READY)
| (1 << DIS_CONTINUITY_PACKET));
if (r) {
goto err4;
}
#else
tsdemux_config();
tsdemux_request_irq(tsdemux_isr, (void *)tsdemux_irq_id);
if (vid < 0x1FFF) {
tsdemux_set_vid(vid);
}
if (aid < 0x1FFF) {
tsdemux_set_aid(aid);
}
if (sid < 0x1FFF) {
tsdemux_set_sid(sid);
}
#endif
return 0;
#ifndef ENABLE_DEMUX_DRIVER
err4:
free_irq(INT_PARSER, (void *)tsdemux_fetch_id);
#endif
err3:
pts_stop(PTS_TYPE_AUDIO);
err2:
pts_stop(PTS_TYPE_VIDEO);
err1:
printk("TS Demux init failed.\n");
return -ENOENT;
}
static ssize_t _rmparser_write(const char __user *buf, size_t count)
{
size_t r = count;
const char __user *p = buf;
u32 len;
int ret;
static int halt_droped_len=0;
u32 vwp,awp;
if (r > 0) {
len = min(r, (size_t)FETCHBUF_SIZE);
if (copy_from_user(fetchbuf_remap, p, len)) {
return -EFAULT;
}
fetch_done = 0;
wmb();
vwp=buf_wp(BUF_TYPE_VIDEO);
awp=buf_wp(BUF_TYPE_AUDIO);
WRITE_MPEG_REG(PARSER_FETCH_ADDR, virt_to_phys((u8 *)fetchbuf));
WRITE_MPEG_REG(PARSER_FETCH_CMD,
(7 << FETCH_ENDIAN) | len);
ret = wait_event_interruptible_timeout(rm_wq, fetch_done != 0, HZ/10);
if (ret == 0) {
WRITE_MPEG_REG(PARSER_FETCH_CMD, 0);
parse_halt ++;
printk("write timeout, retry,halt_count=%d parse_control=%x \n",
parse_halt,READ_MPEG_REG(PARSER_CONTROL));
vreal_set_fatal_flag(1);
if(parse_halt > 10) {
WRITE_MPEG_REG(PARSER_CONTROL, (ES_SEARCH | ES_PARSER_START));
printk("reset parse_control=%x\n",READ_MPEG_REG(PARSER_CONTROL));
}
return -EAGAIN;
} else if (ret < 0) {
return -ERESTARTSYS;
}
if(vwp==buf_wp(BUF_TYPE_VIDEO) && awp==buf_wp(BUF_TYPE_AUDIO)){
if((parse_halt+1)%10==1)
printk("Video&Audio WP not changed after write,video %x->%x,Audio:%x-->%x,parse_halt=%d\n",
vwp,buf_wp(BUF_TYPE_VIDEO),awp,buf_wp(BUF_TYPE_AUDIO),parse_halt);
parse_halt ++;/*wp not changed ,we think have bugs on parser now.*/
if(parse_halt > 10 && (stbuf_level(get_buf_by_type(BUF_TYPE_VIDEO))< 1000 || stbuf_level(get_buf_by_type(BUF_TYPE_AUDIO))< 100))
{/*reset while at least one is underflow.*/
WRITE_MPEG_REG(PARSER_CONTROL, (ES_SEARCH | ES_PARSER_START));
printk("reset parse_control=%x\n",READ_MPEG_REG(PARSER_CONTROL));
}
if(parse_halt <= 10 || halt_droped_len <100*1024){/*drops first 10 pkt ,some times maybe no av data*/
printk("drop this pkt=%d,len=%d\n",parse_halt,len);
p += len;
r -= len;
halt_droped_len+=len;
}else{
return -EAGAIN;
}
}else{
halt_droped_len=0;
parse_halt = 0;
p += len;
r -= len;
}
}
return count - r;
}
static irqreturn_t vmpeg12_isr(int irq, void *dev_id)
{
u32 reg, info, seqinfo, offset, pts, pts_valid = 0;
vframe_t *vf;
ulong flags;
WRITE_MPEG_REG(ASSIST_MBOX1_CLR_REG, 1);
reg = READ_MPEG_REG(MREG_BUFFEROUT);
if (reg) {
info = READ_MPEG_REG(MREG_PIC_INFO);
offset = READ_MPEG_REG(MREG_FRAME_OFFSET);
if (((info & PICINFO_TYPE_MASK) == PICINFO_TYPE_I) &&
(pts_lookup_offset(PTS_TYPE_VIDEO, offset, &pts, 0) == 0)) {
pts_valid = 1;
}
/*if (frame_prog == 0)*/ {
frame_prog = info & PICINFO_PROG;
}
if (frame_prog & PICINFO_PROG) {
u32 index = ((reg & 7) - 1) & 3;
seqinfo = READ_MPEG_REG(MREG_SEQ_INFO);
vf = vfq_pop(&newframe_q);
set_frame_info(vf);
vf->index = index;
vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD;
if ((seqinfo & SEQINFO_EXT_AVAILABLE) && (seqinfo & SEQINFO_PROG)) {
if (info & PICINFO_RPT_FIRST) {
if (info & PICINFO_TOP_FIRST) {
vf->duration = vf->duration * 3; // repeat three times
} else {
vf->duration = vf->duration * 2; // repeat two times
}
}
vf->duration_pulldown = 0; // no pull down
} else {
vf->duration_pulldown = (info & PICINFO_RPT_FIRST) ?
vf->duration >> 1 : 0;
}
vf->duration += vf->duration_pulldown;
vf->canvas0Addr = vf->canvas1Addr = index2canvas(index);
vf->pts = (pts_valid) ? pts : 0;
vfbuf_use[index]++;
if (error_skip(info, vf)) {
spin_lock_irqsave(&lock, flags);
vfq_push(&recycle_q, vf);
spin_unlock_irqrestore(&lock, flags);
} else {
vfq_push(&display_q, vf);
}
vf_notify_receiver(PROVIDER_NAME,VFRAME_EVENT_PROVIDER_VFRAME_READY,NULL);
} else {
static void jpeglogo_prot_init(logo_object_t *plogo)
{
WRITE_MPEG_REG(RESET0_REGISTER, RESET_IQIDCT | RESET_MC);
jpeglogo_canvas_init(plogo);
WRITE_MPEG_REG(AV_SCRATCH_0, 12);
WRITE_MPEG_REG(AV_SCRATCH_1, 0x031a);
WRITE_MPEG_REG(AV_SCRATCH_4, 0x020100);
WRITE_MPEG_REG(AV_SCRATCH_5, 0x050403);
WRITE_MPEG_REG(AV_SCRATCH_6, 0x080706);
WRITE_MPEG_REG(AV_SCRATCH_7, 0x0b0a09);
init_scaler();
/* clear buffer IN/OUT registers */
WRITE_MPEG_REG(MREG_TO_AMRISC, 0);
WRITE_MPEG_REG(MREG_FROM_AMRISC, 0);
WRITE_MPEG_REG(MCPU_INTR_MSK, 0xffff);
WRITE_MPEG_REG(MREG_DECODE_PARAM, 0);
/* clear mailbox interrupt */
WRITE_MPEG_REG(VDEC_ASSIST_MBOX1_CLR_REG, 1);
/* enable mailbox interrupt */
WRITE_MPEG_REG(VDEC_ASSIST_MBOX1_MASK, 1);
}
int hdmirx_config_audio(void)
{
#define AUD_CLK_DELTA 2000
#define RX_8_CHANNEL 1 // 0=I2S 2-channel; 1=I2S 4 x 2-channel.
int err = 0;
unsigned long data32 = 0;
#if 1
data32 = 0;
data32 |= 0 << 9; // [9] force_afif_status:1=Use cntl_audfifo_status_cfg as fifo status; 0=Use detected afif_status.
data32 |= 1 << 8; // [8] afif_status_auto:1=Enable audio FIFO status auto-exit EMPTY/FULL, if FIFO level is back to LipSync; 0=Once enters EMPTY/FULL, never exits.
data32 |= 1 << 6; // [ 7: 6] Audio FIFO nominal level :0=s_total/4;1=s_total/8;2=s_total/16;3=s_total/32.
data32 |= 3 << 4; // [ 5: 4] Audio FIFO critical level:0=s_total/4;1=s_total/8;2=s_total/16;3=s_total/32.
data32 |= 0 << 3; // [3] afif_status_clr:1=Clear audio FIFO status to IDLE.
data32 |= rx.ctrl.acr_mode << 2; // [2] dig_acr_en
data32 |= 0 << 1; // [1] audmeas_clk_sel: 0=select aud_pll_clk; 1=select aud_acr_clk.
data32 |= rx.ctrl.acr_mode << 0; // [0] aud_clk_sel: 0=select aud_pll_clk; 1=select aud_acr_clk.
hdmirx_wr_top( HDMIRX_TOP_ACR_CNTL_STAT, data32);
//hdmirx_wr_dwc( RA_AUDPLL_GEN_CTS, manual_acr_cts);
//hdmirx_wr_dwc( RA_AUDPLL_GEN_N, manual_acr_n);
#if 0
// Force N&CTS to start with, will switch to received values later on, for simulation speed up.
data32 = 0;
data32 |= 1 << 4; // [4] cts_n_ref: 0=used decoded; 1=use manual N&CTS.
hdmirx_wr_dwc( RA_AUD_CLK_CTRL, data32);
#endif
data32 = 0;
data32 |= 0 << 28; // [28] pll_lock_filter_byp
data32 |= 0 << 24; // [27:24] pll_lock_toggle_div
hdmirx_wr_dwc( RA_AUD_PLL_CTRL, data32); // DEFAULT: {1'b0, 3'd0, 4'd6, 4'd3, 4'd8, 1'b0, 1'b0, 1'b1, 1'b0, 12'd0}
data32 = 0;
data32 |= 144 << 18; // [26:18] afif_th_start
data32 |= 32 << 9; // [17:9] afif_th_max
data32 |= 32 << 0; // [8:0] afif_th_min
hdmirx_wr_dwc( RA_AUD_FIFO_TH, data32);
data32 = 0;
data32 |= 1 << 16; // [16] afif_subpackets: 0=store all sp; 1=store only the ones' spX=1.
data32 |= 0 << 0; // [0] afif_init
hdmirx_wr_dwc( RA_AUD_FIFO_CTRL, data32); // DEFAULT: {13'd0, 2'd0, 1'b1, 15'd0, 1'b0}
data32 = 0;
data32 |= (RX_8_CHANNEL? 0x7 :0x0) << 8; // [10:8] ch_map[7:5]
data32 |= 1 << 7; // [7] ch_map_manual
data32 |= (RX_8_CHANNEL? 0x1f:0x3) << 2; // [6:2] ch_map[4:0]
data32 |= 1 << 0; // [1:0] aud_layout_ctrl:0/1=auto layout; 2=layout 0; 3=layout 1.
hdmirx_wr_dwc( RA_AUD_CHEXTRA_CTRL, data32); // DEFAULT: {24'd0, 1'b0, 5'd0, 2'd0}
#endif
/* amlogic HDMIRX audio module enable*/
WRITE_MPEG_REG(HHI_AUDCLK_PLL_CNTL, 0x60010000);
WRITE_MPEG_REG(HHI_AUDCLK_PLL_CNTL2, 0x814d3928);
WRITE_MPEG_REG(HHI_AUDCLK_PLL_CNTL3, 0x6b425012);
WRITE_MPEG_REG(HHI_AUDCLK_PLL_CNTL4, 0x101);
WRITE_MPEG_REG(HHI_AUDCLK_PLL_CNTL5, 0x8550d20);
if(rx.aud_info.audio_recovery_clock > (96000 + AUD_CLK_DELTA)){
if(rx.ctrl.tmds_clk2 <= 36000000) {
printk("tmds_clk2 <= 36000000\n");
WRITE_MPEG_REG(HHI_AUDCLK_PLL_CNTL6, 0x55013000);
} else if (rx.ctrl.tmds_clk2 <= 53000000) {
printk("tmds_clk2 <= 53000000\n");
WRITE_MPEG_REG(HHI_AUDCLK_PLL_CNTL6, 0x55053000);
} else {
printk("tmds_clk2 > 53000000\n");
WRITE_MPEG_REG(HHI_AUDCLK_PLL_CNTL6, 0x55153000);
}
} else {
printk("audio_recovery_clock < 98000\n");
WRITE_MPEG_REG(HHI_AUDCLK_PLL_CNTL6, 0x55153000);
}
WRITE_MPEG_REG(HHI_AUDCLK_PLL_CNTL, 0x00010000); //reset
/**/
#if 0
WRITE_MPEG_REG(AUDIN_SOURCE_SEL, (0 <<12) | // [14:12]cntl_hdmirx_chsts_sel: 0=Report chan1 status; 1=Report chan2 status; ...; 7=Report chan8 status.
(0xf<<8) | // [11:8] cntl_hdmirx_chsts_en
(1 <<4) | // [5:4] spdif_src_sel: 1=Select HDMIRX SPDIF output as AUDIN source
(2 << 0)); // [1:0] i2sin_src_sel: 2=Select HDMIRX I2S output as AUDIN source
#endif
return err;
}
void audio_hw_958_reset(unsigned slow_domain, unsigned fast_domain)
{
WRITE_MPEG_REG(AIU_958_DCU_FF_CTRL,0);
WRITE_MPEG_REG(AIU_RST_SOFT,
(slow_domain << 3) | (fast_domain << 2));
}
static ssize_t _esparser_write(const char __user *buf, size_t count, u32 type)
{
size_t r = count;
const char __user *p = buf;
u32 len = 0;
u32 parser_type;
int ret;
u32 wp;
if (type == BUF_TYPE_VIDEO) {
parser_type = PARSER_VIDEO;
} else if (type == BUF_TYPE_AUDIO) {
parser_type = PARSER_AUDIO;
} else {
parser_type = PARSER_SUBPIC;
}
wp = buf_rp(type);
if (r > 0) {
len = min(r, (size_t)FETCHBUF_SIZE);
if (copy_from_user(fetchbuf_remap, p, len)) {
return -EFAULT;
}
wmb();
// reset the Write and read pointer to zero again
WRITE_MPEG_REG(PFIFO_RD_PTR, 0);
WRITE_MPEG_REG(PFIFO_WR_PTR, 0);
WRITE_MPEG_REG_BITS(PARSER_CONTROL, len, ES_PACK_SIZE_BIT, ES_PACK_SIZE_WID);
WRITE_MPEG_REG_BITS(PARSER_CONTROL,
parser_type | PARSER_WRITE | PARSER_AUTOSEARCH,
ES_CTRL_BIT, ES_CTRL_WID);
WRITE_MPEG_REG(PARSER_FETCH_ADDR, virt_to_phys((u8 *)fetchbuf));
WRITE_MPEG_REG(PARSER_FETCH_CMD,
(7 << FETCH_ENDIAN) | len);
search_done = 0;
WRITE_MPEG_REG(PARSER_FETCH_ADDR, search_pattern_map);
WRITE_MPEG_REG(PARSER_FETCH_CMD,
(7 << FETCH_ENDIAN) | SEARCH_PATTERN_LEN);
ret = wait_event_interruptible_timeout(wq, search_done != 0, HZ/10);
if (ret == 0) {
WRITE_MPEG_REG(PARSER_FETCH_CMD, 0);
if (wp == buf_rp(type)) {
/*no data fetched*/
return -EAGAIN;
} else {
printk("write timeout, but fetched ok,len=%d,wpdiff=%d\n", len, wp - buf_rp(type));
}
} else if (ret < 0) {
return -ERESTARTSYS;
}
}
if (type == BUF_TYPE_VIDEO) {
video_data_parsed += len;
} else if (type == BUF_TYPE_AUDIO) {
audio_data_parsed += len;
}
return len;
}
s32 esparser_init(struct stream_buf_s *buf)
{
s32 r;
u32 pts_type;
u32 parser_sub_start_ptr;
u32 parser_sub_end_ptr;
u32 parser_sub_rp;
if (buf->type == BUF_TYPE_VIDEO) {
pts_type = PTS_TYPE_VIDEO;
} else if (buf->type & BUF_TYPE_AUDIO) {
pts_type = PTS_TYPE_AUDIO;
} else if (buf->type & BUF_TYPE_SUBTITLE) {
pts_type = PTS_TYPE_MAX;
} else {
return -EINVAL;
}
parser_sub_start_ptr = READ_MPEG_REG(PARSER_SUB_START_PTR);
parser_sub_end_ptr = READ_MPEG_REG(PARSER_SUB_END_PTR);
parser_sub_rp = READ_MPEG_REG(PARSER_SUB_RP);
buf->flag |= BUF_FLAG_PARSER;
if (atomic_add_return(1, &esparser_use_count) == 1) {
if (fetchbuf == 0) {
printk("%s: no fetchbuf\n", __FUNCTION__);
return -ENOMEM;
}
if (search_pattern == NULL) {
search_pattern = (unsigned char *)kcalloc(1, SEARCH_PATTERN_LEN, GFP_KERNEL);
if (search_pattern == NULL) {
printk("%s: no search_pattern\n", __FUNCTION__);
return -ENOMEM;
}
/* build a fake start code to get parser interrupt */
search_pattern[0] = 0x00;
search_pattern[1] = 0x00;
search_pattern[2] = 0x01;
search_pattern[3] = 0xff;
search_pattern_map = dma_map_single(NULL, search_pattern,
SEARCH_PATTERN_LEN, DMA_TO_DEVICE);
}
/* reset PARSER with first esparser_init() call */
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER);
/* TS data path */
#ifndef CONFIG_AM_DVB
WRITE_MPEG_REG(FEC_INPUT_CONTROL, 0);
#else
tsdemux_set_reset_flag();
#endif
CLEAR_MPEG_REG_MASK(TS_HIU_CTL, 1 << USE_HI_BSF_INTERFACE);
CLEAR_MPEG_REG_MASK(TS_HIU_CTL_2, 1 << USE_HI_BSF_INTERFACE);
CLEAR_MPEG_REG_MASK(TS_HIU_CTL_3, 1 << USE_HI_BSF_INTERFACE);
CLEAR_MPEG_REG_MASK(TS_FILE_CONFIG, (1 << TS_HIU_ENABLE));
WRITE_MPEG_REG(PARSER_CONFIG,
(10 << PS_CFG_PFIFO_EMPTY_CNT_BIT) |
(1 << PS_CFG_MAX_ES_WR_CYCLE_BIT) |
(16 << PS_CFG_MAX_FETCH_CYCLE_BIT));
WRITE_MPEG_REG(PFIFO_RD_PTR, 0);
WRITE_MPEG_REG(PFIFO_WR_PTR, 0);
WRITE_MPEG_REG(PARSER_SEARCH_PATTERN, ES_START_CODE_PATTERN);
WRITE_MPEG_REG(PARSER_SEARCH_MASK, ES_START_CODE_MASK);
WRITE_MPEG_REG(PARSER_CONFIG,
(10 << PS_CFG_PFIFO_EMPTY_CNT_BIT) |
(1 << PS_CFG_MAX_ES_WR_CYCLE_BIT) |
PS_CFG_STARTCODE_WID_24 |
PS_CFG_PFIFO_ACCESS_WID_8 | /* single byte pop */
(16 << PS_CFG_MAX_FETCH_CYCLE_BIT));
WRITE_MPEG_REG(PARSER_CONTROL, PARSER_AUTOSEARCH);
tasklet_init(&esparser_tasklet, parser_tasklet, 0);
}
/* hook stream buffer with PARSER */
if (pts_type == PTS_TYPE_VIDEO) {
WRITE_MPEG_REG(PARSER_VIDEO_START_PTR,
READ_VREG(VLD_MEM_VIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_VIDEO_END_PTR,
READ_VREG(VLD_MEM_VIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_VREG_MASK(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
video_data_parsed = 0;
} else if (pts_type == PTS_TYPE_AUDIO) {
WRITE_MPEG_REG(PARSER_AUDIO_START_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_AUDIO_END_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR);
WRITE_MPEG_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_MPEG_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
audio_data_parsed = 0;
} else if (buf->type & BUF_TYPE_SUBTITLE) {
WRITE_MPEG_REG(PARSER_SUB_START_PTR, parser_sub_start_ptr);
WRITE_MPEG_REG(PARSER_SUB_END_PTR, parser_sub_end_ptr);
WRITE_MPEG_REG(PARSER_SUB_RP, parser_sub_rp);
SET_MPEG_REG_MASK(PARSER_ES_CONTROL, (7 << ES_SUB_WR_ENDIAN_BIT) | ES_SUB_MAN_RD_PTR);
}
if (pts_type < PTS_TYPE_MAX) {
r = pts_start(pts_type);
if (r < 0) {
printk("esparser_init: pts_start failed\n");
goto Err_1;
}
}
#if 0
if (buf->flag & BUF_FLAG_FIRST_TSTAMP) {
if (buf->type == BUF_TYPE_VIDEO) {
es_vpts_checkin(buf, buf->first_tstamp);
} else if (buf->type == BUF_TYPE_AUDIO) {
es_apts_checkin(buf, buf->first_tstamp);
}
buf->flag &= ~BUF_FLAG_FIRST_TSTAMP;
}
#endif
if (atomic_read(&esparser_use_count) == 1) {
r = request_irq(INT_PARSER, parser_isr,
IRQF_SHARED, "esparser", (void *)esparser_id);
if (r) {
printk("esparser_init: irq register failed.\n");
goto Err_2;
}
WRITE_MPEG_REG(PARSER_INT_STATUS, 0xffff);
WRITE_MPEG_REG(PARSER_INT_ENABLE,
PARSER_INTSTAT_SC_FOUND << PARSER_INT_HOST_EN_BIT);
}
return 0;
Err_2:
pts_stop(pts_type);
Err_1:
buf->flag &= ~BUF_FLAG_PARSER;
return r;
}
static void lvds_port_disable(void)
{
//disable minilvds_data channel
WRITE_MPEG_REG(LVDS_PHY_CNTL4, READ_MPEG_REG(LVDS_PHY_CNTL4) & ~(0x7f<<0));
}
static void lvds_port_enable(void)
{
// printk("\n\nLVDS port enable.\n");
//enable minilvds_data channel
WRITE_MPEG_REG(LVDS_PHY_CNTL4, READ_MPEG_REG(LVDS_PHY_CNTL4) | (0x2f<<0));
}
static void power_off_lcd(void)
{
/*debug("%s\n", __FUNCTION__);
power_off_backlight();
mdelay(50);
//GPIOC2 -> VCCx3_EN: 0
set_gpio_val(GPIOC_bank_bit0_15(2), GPIOC_bit_bit0_15(2), 0);
set_gpio_mode(GPIOC_bank_bit0_15(2), GPIOC_bit_bit0_15(2), GPIO_OUTPUT_MODE);
mdelay(30);
//GPIOA27 -> LCD_PWR_EN#: 1 lcd 3.3v
set_gpio_val(GPIOA_bank_bit0_27(27), GPIOA_bit_bit0_27(27), 1);
set_gpio_mode(GPIOA_bank_bit0_27(27), GPIOA_bit_bit0_27(27), GPIO_OUTPUT_MODE);
mdelay(10);*/
//TCH_PWR_EN
WRITE_MPEG_REG(PERIPHS_PIN_MUX_3, READ_MPEG_REG(PERIPHS_PIN_MUX_3) & ~(1 << 1));
WRITE_MPEG_REG(PERIPHS_PIN_MUX_0, READ_MPEG_REG(PERIPHS_PIN_MUX_0) & ~(1 << 6));
WRITE_MPEG_REG(PREG_PAD_GPIO0_EN_N, READ_MPEG_REG(PREG_PAD_GPIO0_EN_N) & ~(1 << 9));
WRITE_MPEG_REG(PREG_PAD_GPIO0_O, READ_MPEG_REG(PREG_PAD_GPIO0_O) | (1 << 9));
mdelay(10);
//LCD_BL_PWM
WRITE_MPEG_REG(PERIPHS_PIN_MUX_2, READ_MPEG_REG(PERIPHS_PIN_MUX_2)&~(1 << 3));
WRITE_MPEG_REG(PERIPHS_PIN_MUX_1, READ_MPEG_REG(PERIPHS_PIN_MUX_1)&~(1 << 28));
WRITE_MPEG_REG(PREG_PAD_GPIO2_EN_N, READ_MPEG_REG(PREG_PAD_GPIO2_EN_N) & ~(1 << 17));
WRITE_MPEG_REG(PREG_PAD_GPIO2_O, READ_MPEG_REG(PREG_PAD_GPIO2_O) & ~(1 << 17));
mdelay(10);
//LCD_PWR_EN# LCD_3.0V
WRITE_MPEG_REG(PERIPHS_PIN_MUX_0, READ_MPEG_REG(PERIPHS_PIN_MUX_0) & ~(1 << 10));
WRITE_MPEG_REG(PERIPHS_PIN_MUX_7, READ_MPEG_REG(PERIPHS_PIN_MUX_7) & ~(1 << 15));
WRITE_MPEG_REG(PREG_PAD_GPIO0_EN_N, READ_MPEG_REG(PREG_PAD_GPIO0_EN_N) & ~(1 << 27));
WRITE_MPEG_REG(PREG_PAD_GPIO0_O, READ_MPEG_REG(PREG_PAD_GPIO0_O) | (1 << 27));
mdelay(10);
}
// iec958 and i2s clock are separated after M6TV. Use PLL1 for iec958 clock
void audio_set_958_clk(unsigned freq, unsigned fs_config)
{
int i;
int xtal = 0;
int (*audio_clock_config)[2];
int index=0;
switch(freq)
{
case AUDIO_CLK_FREQ_192:
index=4;
break;
case AUDIO_CLK_FREQ_96:
index=3;
break;
case AUDIO_CLK_FREQ_48:
index=2;
break;
case AUDIO_CLK_FREQ_441:
index=1;
break;
case AUDIO_CLK_FREQ_32:
index=0;
break;
case AUDIO_CLK_FREQ_8:
index = 5;
break;
case AUDIO_CLK_FREQ_11:
index = 6;
break;
case AUDIO_CLK_FREQ_12:
index = 7;
break;
case AUDIO_CLK_FREQ_16:
index = 8;
break;
case AUDIO_CLK_FREQ_22:
index = 9;
break;
case AUDIO_CLK_FREQ_24:
index = 10;
break;
default:
index=0;
break;
};
if (fs_config == AUDIO_CLK_256FS) {
// divide 256
xtal = 0;
}
else if (fs_config == AUDIO_CLK_384FS) {
// divide 384
xtal = 1;
}
audio_clock_config = audio_clock_config_table[xtal];
// gate the clock off
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 8));
//WRITE_MPEG_REG(AIU_CLK_CTRL_MORE, 0);
//Set filter register
//WRITE_MPEG_REG(HHI_MPLL_CNTL3, 0x26e1250);
/*--- IEC958 clock configuration, use MPLL1--- */
// Disable mclk
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL2, 0, 24, 1);
//IEC958_USE_CNTL
WRITE_MPEG_REG_BITS( HHI_AUD_CLK_CNTL2, 1, 27, 1);
// Select clk source, 0=ddr_pll; 1=Multi-Phase PLL0; 2=Multi-Phase PLL1; 3=Multi-Phase PLL2.
WRITE_MPEG_REG_BITS( HHI_AUD_CLK_CNTL2, 2, 25, 2);
// Configure Multi-Phase PLL1
WRITE_MPEG_REG(HHI_MPLL_CNTL8, audio_clock_config[index][0]);
// Set the XD value
#if IEC958_OVERCLOCK ==1
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL2, (audio_clock_config[index][1]+1)/2 -1, 16, 8);
#else
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL2, audio_clock_config[index][1], 16, 8);
#endif
// delay 5uS
//udelay(5);
for (i = 0; i < 500000; i++) ;
// gate the clock on
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1 << 8));
// Enable mclk
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL2, 1, 24, 1);
}
void audio_hw_958_raw()
{
if (ENABLE_IEC958) {
WRITE_MPEG_REG(AIU_958_MISC, 1);
WRITE_MPEG_REG_BITS(AIU_MEM_IEC958_CONTROL, 1, 8, 1); // raw
WRITE_MPEG_REG_BITS(AIU_MEM_IEC958_CONTROL, 0, 7, 1); // 8bit
WRITE_MPEG_REG_BITS(AIU_MEM_IEC958_CONTROL, 1, 3, 3); // endian
}
WRITE_MPEG_REG(AIU_958_BPF, IEC958_bpf);
WRITE_MPEG_REG(AIU_958_BRST, IEC958_brst);
WRITE_MPEG_REG(AIU_958_LENGTH, IEC958_length);
WRITE_MPEG_REG(AIU_958_PADDSIZE, IEC958_padsize);
WRITE_MPEG_REG_BITS(AIU_958_DCU_FF_CTRL, 0, 2, 2);// disable int
if(IEC958_mode == 1){ // search in byte
WRITE_MPEG_REG_BITS(AIU_958_DCU_FF_CTRL, 7, 4, 3);
}else if(IEC958_mode == 2) { // search in word
WRITE_MPEG_REG_BITS(AIU_958_DCU_FF_CTRL, 5, 4, 3);
}else{
WRITE_MPEG_REG_BITS(AIU_958_DCU_FF_CTRL, 0, 4, 3);
}
WRITE_MPEG_REG(AIU_958_CHSTAT_L0, IEC958_chstat0_l);
WRITE_MPEG_REG(AIU_958_CHSTAT_L1, IEC958_chstat1_l);
WRITE_MPEG_REG(AIU_958_CHSTAT_R0, IEC958_chstat0_r);
WRITE_MPEG_REG(AIU_958_CHSTAT_R1, IEC958_chstat1_r);
WRITE_MPEG_REG(AIU_958_SYNWORD1, IEC958_syncword1);
WRITE_MPEG_REG(AIU_958_SYNWORD2, IEC958_syncword2);
WRITE_MPEG_REG(AIU_958_SYNWORD3, IEC958_syncword3);
WRITE_MPEG_REG(AIU_958_SYNWORD1_MASK, IEC958_syncword1_mask);
WRITE_MPEG_REG(AIU_958_SYNWORD2_MASK, IEC958_syncword2_mask);
WRITE_MPEG_REG(AIU_958_SYNWORD3_MASK, IEC958_syncword3_mask);
printk("%s: %d\n", __func__, __LINE__);
printk("\tBPF: %x\n", IEC958_bpf);
printk("\tBRST: %x\n", IEC958_brst);
printk("\tLENGTH: %x\n", IEC958_length);
printk("\tPADDSIZE: %x\n", IEC958_length);
printk("\tsyncword: %x, %x, %x\n\n", IEC958_syncword1, IEC958_syncword2, IEC958_syncword3);
}
static int uVideoFmt_SetVideoType(control_t* cntl, cond_item_t* param)
{
int ret=0;
uvideofmt_t* uvideofmt = (uvideofmt_t*)(cntl->private_data);
int fmt = (int)(param[0]);
int outputmode = (int)(param[1]);
/* Add Method code here, Set ret to be -1 if fail */
int displayctl_fd, resolution_data;
video_appmode_t video_appmode =
{
DISPCTL_MODE_1080P,
0,
0,
0,
DISPCTL_MODE_1080P
};
page_t *page = af_find_page(SYSTEM_DEFAULT_PAGE);
if (this_curVideoFmt!=fmt || this_outputmode!= outputmode)
{
/* when NTSC/PAL CVBS output is enabled in first 3 video dacs,
* enable pedestal. Component 480i has pedestal disabled.
*/
#ifdef AML_NIKE
fmt = 6;
#endif
#ifndef EDGE_ADJUST
set_display_edge_adjust(0,0,0,0);
#endif
af_osd_layer_destroy(OSD_LAYER_HW_LAYER0);
switch(outputmode)
{
case 0://Analog
clear_mio_mux(5, (1<<0) | (1<<2) | (1<<3) | (1<<4) | (1<<7));
//disable RGB data
//clear_mio_mux(4, (1<<20) | (1<<22) | (1<<24));//6bits
clear_mio_mux(4, (0x3f<<20));//8bits
#ifdef APOLLO_PMP_TVOUT
clear_mio_mux(4, 0x7c000000); //disable hdmi output ,
#endif
resolution_data = set_analog_output(fmt, &video_appmode);
break;
case 2://HDMI
clear_mio_mux(5, (1<<0) | (1<<2) | (1<<3) | (1<<4) | (1<<7));
//disable RGB data
//clear_mio_mux(4, (1<<20) | (1<<22) | (1<<24));//6bits
clear_mio_mux(4, (0x3f<<20));//8bits
resolution_data = set_hdmi_output(fmt, &video_appmode);
set_mio_mux(4, 0x7c000000); //mux GPIOC_28 to hsync, mux GPIOC_29 to vsync, mux GPIOC_30 to DE, mux GPIOC_31 to pixel clock, mux GPIOC_32~GPIOC_55 to HDMI data lines,
Codec_PowerDown_Entile_Codec(0);
break;
#if (defined APOLLO_PMP_LCD) || (defined NIKE_PMP_LCD)
case 1://Panel
#ifdef EDGE_ADJUST
set_display_edge_adjust(0,0,0,0);
#endif
clear_mio_mux(4, 0x7c000000); //disable hdmi output ,
//enable Tcon
//set_mio_mux(5, (1<<0) | (1<<2) | (1<<3) | (1<<4) | (1<<7) | (1<<8) | (1<<9));
set_mio_mux(5, (1<<0) | (1<<2) | (1<<3) | (1<<4) | (1<<7));
//enable RGB data
//set_mio_mux(4, (1<<20) | (1<<22) | (1<<24));//6bits
set_mio_mux(4, (0x3f<<20));//8bits
resolution_data = set_lcd_output(fmt, &video_appmode);
power_off_USBb();
break;
#endif
default:
AVOS_printf("Please select the valid output mode!\n");
break;
}
GF_SetHdmode(cntl, &video_appmode.hdmode);
af_set_current_resolution(resolution_data);
af_init_osd(page);
}
this_curVideoFmt_Set(fmt);
if(outputmode<=2&&outputmode>=0)
{
this_outputmode_Set(outputmode);
}
///////////////////////////////////////////
int video_fd;
video_fd=open("/dev/video",O_RDONLY);
//video_appmode_t video_appmode = {DISPCTL_MODE_480P, VIDEO_APPVMODE_480_480, VIDEO_APPHMODE_720, 0, DISPCTL_MODE_VGA};
video_appmode_t video_appmode2 = {DISPCTL_MODE_480P, VIDEO_APPVMODE_480_480, VIDEO_APPHMODE_720, 0, DISPCTL_MODE_VGA};
ioctl(video_fd, VIDEOIO_SETAPPMODE, &video_appmode2);
WRITE_MPEG_REG(VENC_VDAC_SETTING,0);
power_on_vdac();
///////////////////////////////////////////
AVTimeDly(100);
/* end */
return ret;
}
static void audio_hw_set_958_pcm24(_aiu_958_raw_setting_t * set)
{
WRITE_MPEG_REG(AIU_958_BPF, 0x80); /* in pcm mode, set bpf to 128 */
set_958_channel_status(set->chan_stat);
}
static void init_scaler(void)
{
/* 4 point triangle */
const unsigned filt_coef[] = {
0x20402000, 0x20402000, 0x1f3f2101, 0x1f3f2101,
0x1e3e2202, 0x1e3e2202, 0x1d3d2303, 0x1d3d2303,
0x1c3c2404, 0x1c3c2404, 0x1b3b2505, 0x1b3b2505,
0x1a3a2606, 0x1a3a2606, 0x19392707, 0x19392707,
0x18382808, 0x18382808, 0x17372909, 0x17372909,
0x16362a0a, 0x16362a0a, 0x15352b0b, 0x15352b0b,
0x14342c0c, 0x14342c0c, 0x13332d0d, 0x13332d0d,
0x12322e0e, 0x12322e0e, 0x11312f0f, 0x11312f0f,
0x10303010
};
int i;
/* pscale enable, PSCALE cbus bmem enable */
WRITE_MPEG_REG(PSCALE_CTRL, 0xc000);
/* write filter coefs */
WRITE_MPEG_REG(PSCALE_BMEM_ADDR, 0);
for (i = 0; i < 33; i++) {
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0);
WRITE_MPEG_REG(PSCALE_BMEM_DAT, filt_coef[i]);
}
/* Y horizontal initial info */
WRITE_MPEG_REG(PSCALE_BMEM_ADDR, 37*2);
/* [35]: buf repeat pix0,
* [34:29] => buf receive num,
* [28:16] => buf blk x,
* [15:0] => buf phase
*/
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x0008);
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x60000000);
/* C horizontal initial info */
WRITE_MPEG_REG(PSCALE_BMEM_ADDR, 41*2);
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x0008);
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x60000000);
/* Y vertical initial info */
WRITE_MPEG_REG(PSCALE_BMEM_ADDR, 39*2);
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x0008);
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x60000000);
/* C vertical initial info */
WRITE_MPEG_REG(PSCALE_BMEM_ADDR, 43*2);
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x0008);
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x60000000);
/* Y horizontal phase step */
WRITE_MPEG_REG(PSCALE_BMEM_ADDR, 36*2 + 1);
/* [19:0] => Y horizontal phase step */
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x10000);
/* C horizontal phase step */
WRITE_MPEG_REG(PSCALE_BMEM_ADDR, 40*2 + 1);
/* [19:0] => C horizontal phase step */
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x10000);
/* Y vertical phase step */
WRITE_MPEG_REG(PSCALE_BMEM_ADDR, 38*2+1);
/* [19:0] => Y vertical phase step */
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x10000);
/* C vertical phase step */
WRITE_MPEG_REG(PSCALE_BMEM_ADDR, 42*2+1);
/* [19:0] => C horizontal phase step */
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x10000);
/* reset pscaler */
WRITE_MPEG_REG(RESET2_REGISTER, RESET_PSCALE);
READ_MPEG_REG(RESET2_REGISTER);
READ_MPEG_REG(RESET2_REGISTER);
READ_MPEG_REG(RESET2_REGISTER);
WRITE_MPEG_REG(PSCALE_RST, 0x7);
WRITE_MPEG_REG(PSCALE_RST, 0x0);
}
void audio_set_aiubuf(u32 addr, u32 size, unsigned int channel)
{
WRITE_MPEG_REG(AIU_MEM_I2S_START_PTR, addr & 0xffffffc0);
WRITE_MPEG_REG(AIU_MEM_I2S_RD_PTR, addr & 0xffffffc0);
if(channel == 8)
WRITE_MPEG_REG(AIU_MEM_I2S_END_PTR, (addr & 0xffffffc0) + (size & 0xffffffc0) - 256);
else
WRITE_MPEG_REG(AIU_MEM_I2S_END_PTR, (addr & 0xffffffc0) + (size & 0xffffffc0) - 64); //this is for 16bit 2 channel
WRITE_MPEG_REG(AIU_I2S_MISC, 0x0004); // Hold I2S
WRITE_MPEG_REG(AIU_I2S_MUTE_SWAP, 0x0000); // No mute, no swap
// As the default amclk is 24.576MHz, set i2s and iec958 divisor appropriately so as not to exceed the maximum sample rate.
WRITE_MPEG_REG(AIU_I2S_MISC, 0x0010 ); // Release hold and force audio data to left or right
if(channel == 8){
printk(" %s channel == 8\n",__FUNCTION__);
WRITE_MPEG_REG(AIU_MEM_I2S_MASKS, (24 << 16) | // [31:16] IRQ block.
(0xff << 8) | // [15: 8] chan_mem_mask. Each bit indicates which channels exist in memory
(0xff << 0)); // [ 7: 0] chan_rd_mask. Each bit indicates which channels are READ from memory
}
else
WRITE_MPEG_REG(AIU_MEM_I2S_MASKS, (24 << 16) | // [31:16] IRQ block.
(0x3 << 8) | // [15: 8] chan_mem_mask. Each bit indicates which channels exist in memory
(0x3 << 0)); // [ 7: 0] chan_rd_mask. Each bit indicates which channels are READ from memory
// 16 bit PCM mode
// WRITE_MPEG_REG_BITS(AIU_MEM_I2S_CONTROL, 1, 6, 1);
// Set init high then low to initilize the I2S memory logic
WRITE_MPEG_REG_BITS(AIU_MEM_I2S_CONTROL, 1, 0, 1 );
WRITE_MPEG_REG_BITS(AIU_MEM_I2S_CONTROL, 0, 0, 1 );
WRITE_MPEG_REG(AIU_MEM_I2S_BUF_CNTL, 1 | (0 << 1));
WRITE_MPEG_REG(AIU_MEM_I2S_BUF_CNTL, 0 | (0 << 1));
audio_out_buf_ready = 1;
}
static inline void feed_vb(s32 s)
{
u32 addr = READ_MPEG_REG(VLD_MEM_VIFIFO_START_PTR);
amlog_mask_level(LOG_MASK_PARSER,LOG_LEVEL_LOW,"feed start addr:0x%x\n",addr);
WRITE_MPEG_REG(VLD_MEM_VIFIFO_WP, (addr + s + PADDINGSIZE + 7) & ~7);
}
void audio_in_i2s_set_wrptr(unsigned int val)
{
WRITE_MPEG_REG(AUDIN_FIFO0_RDPTR, val);
}
static void lvds_port_disable(void)
{
unsigned pinmux = 0;
printk("\n\nminiLVDS port disable.\n");
//disable minilvds_data channel
WRITE_MPEG_REG(LVDS_PHY_CNTL4, READ_MPEG_REG(LVDS_PHY_CNTL4) & ~(0x7f<<0));
WRITE_MPEG_REG( LVDS_GEN_CNTL, (READ_MPEG_REG(LVDS_GEN_CNTL) & ~(1 << 3))); // disable fifo
pinmux = lcd_config.mlvds_config->set_mlvds_pinmux;
WRITE_MPEG_REG(0x202c, READ_MPEG_REG(0x202c) & ~(0xff<<12));
WRITE_MPEG_REG(0x202d, READ_MPEG_REG(0x202d) & ~(0x3ff<<2));
WRITE_MPEG_REG(0x202f, READ_MPEG_REG(0x202f) & ~(0x7<<23));
WRITE_MPEG_REG(0x2033, READ_MPEG_REG(0x2033) & ~(1<<17));
WRITE_MPEG_REG(0x202c, READ_MPEG_REG(0x202c) & ~(pinmux<<12)); //clear tcon pinmux
WRITE_MPEG_REG(0x2013, READ_MPEG_REG(0x2013) & ~(pinmux<<2)); //set tcon pin output low
WRITE_MPEG_REG(0x2012, READ_MPEG_REG(0x2012) & ~(pinmux<<2)); //set tcon pin as output
WRITE_MPEG_REG(0x202c, READ_MPEG_REG(0x202c) & ~(1<<12));
WRITE_MPEG_REG(0x202d, READ_MPEG_REG(0x202d) & ~(1<<9));
WRITE_MPEG_REG(0x2013, READ_MPEG_REG(0x2013) & ~(1<<2)); //set sth output low
WRITE_MPEG_REG(0x2012, READ_MPEG_REG(0x2012) & ~(1<<2)); //set sth output
}
void audio_in_spdif_set_wrptr(unsigned int val)
{
WRITE_MPEG_REG(AUDIN_FIFO1_RDPTR, val);
}
s32 rmparser_init(void)
{
s32 r;
parse_halt = 0;
if (fetchbuf == 0) {
printk("%s: no fetchbuf\n", __FUNCTION__);
return -ENOMEM;
}
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER);
/* TS data path */
#ifndef CONFIG_AM_DVB
WRITE_MPEG_REG(FEC_INPUT_CONTROL, 0);
#else
tsdemux_set_reset_flag();
#endif
CLEAR_MPEG_REG_MASK(TS_HIU_CTL, 1 << USE_HI_BSF_INTERFACE);
CLEAR_MPEG_REG_MASK(TS_HIU_CTL_2, 1 << USE_HI_BSF_INTERFACE);
CLEAR_MPEG_REG_MASK(TS_HIU_CTL_3, 1 << USE_HI_BSF_INTERFACE);
CLEAR_MPEG_REG_MASK(TS_FILE_CONFIG, (1 << TS_HIU_ENABLE));
/* hook stream buffer with PARSER */
WRITE_MPEG_REG(PARSER_VIDEO_START_PTR,
READ_VREG(VLD_MEM_VIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_VIDEO_END_PTR,
READ_VREG(VLD_MEM_VIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
WRITE_MPEG_REG(PARSER_AUDIO_START_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_AUDIO_END_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR);
WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_VREG_MASK(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
WRITE_MPEG_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_MPEG_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
WRITE_MPEG_REG(PFIFO_RD_PTR, 0);
WRITE_MPEG_REG(PFIFO_WR_PTR, 0);
WRITE_MPEG_REG(PARSER_SEARCH_MASK, 0);
WRITE_MPEG_REG(PARSER_CONTROL, (ES_SEARCH | ES_PARSER_START));
#ifdef MANAGE_PTS
if (pts_start(PTS_TYPE_VIDEO) < 0) {
goto Err_1;
}
if (pts_start(PTS_TYPE_AUDIO) < 0) {
goto Err_2;
}
#endif
/* enable interrupt */
r = request_irq(INT_PARSER, rm_parser_isr,
IRQF_SHARED, "rmparser", (void *)rmparser_id);
if (r) {
printk("RM parser irq register failed.\n");
goto Err_3;
}
WRITE_MPEG_REG(PARSER_INT_STATUS, 0xffff);
WRITE_MPEG_REG(PARSER_INT_ENABLE,
((PARSER_INT_ALL & (~PARSER_INTSTAT_FETCH_CMD)) << PARSER_INT_AMRISC_EN_BIT)
| (PARSER_INTSTAT_FETCH_CMD << PARSER_INT_HOST_EN_BIT));
return 0;
Err_3:
pts_stop(PTS_TYPE_AUDIO);
Err_2:
pts_stop(PTS_TYPE_VIDEO);
Err_1:
return -ENOENT;
}
void audio_set_clk(unsigned freq, unsigned fs_config)
{
int i;
int xtal = 0;
int (*audio_clock_config)[2];
// if (fs_config == AUDIO_CLK_256FS) {
if(1){
int index=0;
switch(freq)
{
case AUDIO_CLK_FREQ_192:
index=4;
break;
case AUDIO_CLK_FREQ_96:
index=3;
break;
case AUDIO_CLK_FREQ_48:
index=2;
break;
case AUDIO_CLK_FREQ_441:
index=1;
break;
case AUDIO_CLK_FREQ_32:
index=0;
break;
case AUDIO_CLK_FREQ_8:
index = 5;
break;
case AUDIO_CLK_FREQ_11:
index = 6;
break;
case AUDIO_CLK_FREQ_12:
index = 7;
break;
case AUDIO_CLK_FREQ_16:
index = 8;
break;
case AUDIO_CLK_FREQ_22:
index = 9;
break;
case AUDIO_CLK_FREQ_24:
index = 10;
break;
default:
index=0;
break;
};
#if MESON_CPU_TYPE < MESON_CPU_TYPE_MESON6
// get system crystal freq
clk=clk_get_sys("clk_xtal", NULL);
if(!clk)
{
printk(KERN_ERR "can't find clk %s for AUDIO PLL SETTING!\n\n","clk_xtal");
//return -1;
}
else
{
xtal=clk_get_rate(clk);
xtal=xtal/1000000;
if(xtal>=24 && xtal <=25)/*current only support 24,25*/
{
xtal-=24;
}
else
{
printk(KERN_WARNING "UNsupport xtal setting for audio xtal=%d,default to 24M\n",xtal);
xtal=0;
}
}
audio_clock_config = audio_clock_config_table[xtal];
#endif
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
if (fs_config == AUDIO_CLK_256FS) {
// divide 256
xtal = 0;
}
else if (fs_config == AUDIO_CLK_384FS) {
// divide 384
xtal = 1;
}
audio_clock_config = audio_clock_config_table[xtal];
#endif
#ifdef CONFIG_SND_AML_M3
if (((clk_get_rate(clk)==24000000)&&(get_ddr_pll_clk()==516000000)&&(index=2))) // 48k
{
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 8)); // audio clock off
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) | (1 << 15)); // audio pll off
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 4, 9, 3); // select ddr
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 42-1, 0, 8); // 516/42
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);//set codec adc ratio---lrclk
WRITE_MPEG_REG_BITS(AIU_CODEC_DAC_LRCLK_CTRL, 64-1, 0, 12);//set codec dac ratio---lrclk
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1<<23));// gate audac_clkpi
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1 << 8));
printk(KERN_INFO "audio 48k clock from ddr pll %dM\n", 516);
return;
}
else if (((clk_get_rate(clk)==24000000)&&(get_ddr_pll_clk()==508000000)&&(index=1))) // 44.1k
{
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 8)); // audio clock off
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) | (1 << 15)); // audio pll off
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 4, 9, 3); // select ddr
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 45-1, 0, 8); // 508/45
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);//set codec adc ratio---lrclk
WRITE_MPEG_REG_BITS(AIU_CODEC_DAC_LRCLK_CTRL, 64-1, 0, 12);//set codec dac ratio---lrclk
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1<<23));// gate audac_clkpi
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1 << 8));
printk(KERN_INFO "audio 44.1k clock from ddr pll %dM\n", 508);
return;
}
else if (((clk_get_rate(clk)==24000000)&&(get_ddr_pll_clk()==486000000)&&(index=1))) // 44.1k
{
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 8)); // audio clock off
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) | (1 << 15)); // audio pll off
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 4, 9, 3); // select ddr
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 43-1, 0, 8); // 486/42
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);//set codec adc ratio---lrclk
WRITE_MPEG_REG_BITS(AIU_CODEC_DAC_LRCLK_CTRL, 64-1, 0, 12);//set codec dac ratio---lrclk
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1<<23));// gate audac_clkpi
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1 << 8));
printk(KERN_INFO "audio 44.1k clock from ddr pll %dM\n", 486);
return;
}
else if (((clk_get_rate(clk)==24000000)&&(get_ddr_pll_clk()==474000000)&&(index=1))) // 44.1k
{
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 8)); // audio clock off
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) | (1 << 15)); // audio pll off
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 4, 9, 3); // select ddr
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 42-1, 0, 8); // 474/42
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);//set codec adc ratio---lrclk
WRITE_MPEG_REG_BITS(AIU_CODEC_DAC_LRCLK_CTRL, 64-1, 0, 12);//set codec dac ratio---lrclk
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1<<23));// gate audac_clkpi
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1 << 8));
printk(KERN_INFO "audio 44.1k clock from ddr pll %dM\n", 474);
return;
}
#endif
// gate the clock off
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 8));
//#ifdef CONFIG_SND_AML_M3
#ifdef CONFIG_ARCH_MESON3
WRITE_MPEG_REG(HHI_AUD_PLL_CNTL2, 0x065e31ff);
WRITE_MPEG_REG(HHI_AUD_PLL_CNTL3, 0x9649a941);
// select Audio PLL as MCLK source
//WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 9));
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 0, 9, 3);
//WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 25-1, 0, 8);
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 13-1, 0, 8);
#endif
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
WRITE_MPEG_REG(HHI_MPLL_CNTL3, 0x26e1250);
#endif
#if MESON_CPU_TYPE < MESON_CPU_TYPE_MESON6
// Put the PLL to sleep
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) | (1 << 15));//found
//#ifdef CONFIG_SND_AML_M3
#if MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON3
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);//set codec adc ratio---lrclk
WRITE_MPEG_REG_BITS(AIU_CODEC_DAC_LRCLK_CTRL, 64-1, 0, 12);//set codec dac ratio---lrclk
#endif
// Bring out of reset but keep bypassed to allow to stablize
//Wr( HHI_AUD_PLL_CNTL, (1 << 15) | (0 << 14) | (hiu_reg & 0x3FFF) );
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, (1 << 15) | (audio_clock_config[index][0] & 0x7FFF) );//found
// Set the XD value
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, (READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(0xff << 0)) | audio_clock_config[index][1]);//found
// delay 5uS
//udelay(5);
for (i = 0; i < 500000; i++) ;
// Bring the PLL out of sleep
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) & ~(1 << 15));//found
// gate the clock on
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1 << 8));//found
#if MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON3
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) |(1<<23));// gate audac_clkpi
#endif
#else // endif CONFIG_ARCH_MESON6
WRITE_MPEG_REG(AIU_CLK_CTRL_MORE, 0);
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);//set codec adc ratio---lrclk
WRITE_MPEG_REG_BITS(AIU_CODEC_DAC_LRCLK_CTRL, 64-1, 0, 12);//set codec dac ratio---lrclk
// Select Multi-Phase PLL2 as clock source
WRITE_MPEG_REG_BITS( HHI_AUD_CLK_CNTL, 3, 9, 3);
// Configure Multi-Phase PLL2
WRITE_MPEG_REG(HHI_MPLL_CNTL9, audio_clock_config[index][0]);
// Set the XD value
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, audio_clock_config[index][1], 0, 8);
// delay 5uS
//udelay(5);
for (i = 0; i < 500000; i++) ;
// gate the clock on
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1 << 8));
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6TV
//Audio DAC Clock enable
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) |(1<<23));
/* ADC clock configuration */
// Disable mclk
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL2, 0, 8, 1);
// Select clk source, 0=ddr_pll; 1=Multi-Phase PLL0; 2=Multi-Phase PLL1; 3=Multi-Phase PLL2.
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL2, 3, 9, 2);
// Set pll over mclk ratio
//we want 256fs ADC MLCK,so for over clock mode,divide more 2 than I2S DAC CLOCK
#if OVERCLOCK == 0
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL2, audio_clock_config[index][1], 0, 8);
#else
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL2, (audio_clock_config[index][1]+1)*2-1, 0, 8);
#endif
// Set mclk over sclk ratio
WRITE_MPEG_REG_BITS(AIU_CLK_CTRL_MORE, 4-1, 8, 6);
// Set sclk over lrclk ratio
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);
// Enable sclk
WRITE_MPEG_REG_BITS(AIU_CLK_CTRL_MORE, 1, 14, 1);
// Enable mclk
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL2, 1, 8, 1);
#endif
#endif // endif CONFIG_ARCH_MESON6
// delay 2uS
//udelay(2);
for (i = 0; i < 200000; i++) ;
} else if (fs_config == AUDIO_CLK_384FS) {
}
}
s32 tsdemux_init(u32 vid, u32 aid, u32 sid, u32 pcrid)
#endif
{
s32 r;
u32 parser_sub_start_ptr;
u32 parser_sub_end_ptr;
u32 parser_sub_rp;
u32 pcr_num;
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
switch_mod_gate_by_type(MOD_DEMUX, 1);
#endif
parser_sub_start_ptr = READ_MPEG_REG(PARSER_SUB_START_PTR);
parser_sub_end_ptr = READ_MPEG_REG(PARSER_SUB_END_PTR);
parser_sub_rp = READ_MPEG_REG(PARSER_SUB_RP);
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER);
#ifdef ENABLE_DEMUX_DRIVER
tsdemux_reset();
#else
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER | RESET_DEMUXSTB);
WRITE_MPEG_REG(STB_TOP_CONFIG, 0);
WRITE_MPEG_REG(DEMUX_CONTROL, 0);
#endif
/* set PID filter */
printk("tsdemux video_pid = 0x%x, audio_pid = 0x%x, sub_pid = 0x%x, pcrid = 0x%x\n",
vid, aid, sid, pcrid);
#ifndef ENABLE_DEMUX_DRIVER
WRITE_MPEG_REG(FM_WR_DATA,
(((vid & 0x1fff) | (VIDEO_PACKET << 13)) << 16) |
((aid & 0x1fff) | (AUDIO_PACKET << 13)));
WRITE_MPEG_REG(FM_WR_ADDR, 0x8000);
while (READ_MPEG_REG(FM_WR_ADDR) & 0x8000) {
;
}
WRITE_MPEG_REG(FM_WR_DATA,
(((sid & 0x1fff) | (SUB_PACKET << 13)) << 16) | 0xffff);
WRITE_MPEG_REG(FM_WR_ADDR, 0x8001);
while (READ_MPEG_REG(FM_WR_ADDR) & 0x8000) {
;
}
WRITE_MPEG_REG(MAX_FM_COMP_ADDR, 1);
WRITE_MPEG_REG(STB_INT_MASK, 0);
WRITE_MPEG_REG(STB_INT_STATUS, 0xffff);
/* TS data path */
WRITE_MPEG_REG(FEC_INPUT_CONTROL, 0x7000);
WRITE_MPEG_REG(DEMUX_MEM_REQ_EN,
(1 << VIDEO_PACKET) |
(1 << AUDIO_PACKET) |
(1 << SUB_PACKET));
WRITE_MPEG_REG(DEMUX_ENDIAN,
(7 << OTHER_ENDIAN) |
(7 << BYPASS_ENDIAN) |
(0 << SECTION_ENDIAN));
WRITE_MPEG_REG(TS_HIU_CTL, 1 << USE_HI_BSF_INTERFACE);
WRITE_MPEG_REG(TS_FILE_CONFIG,
(demux_skipbyte << 16) |
(6 << DES_OUT_DLY) |
(3 << TRANSPORT_SCRAMBLING_CONTROL_ODD) |
(1 << TS_HIU_ENABLE) |
(4 << FEC_FILE_CLK_DIV));
/* enable TS demux */
WRITE_MPEG_REG(DEMUX_CONTROL, (1 << STB_DEMUX_ENABLE) | (1 << KEEP_DUPLICATE_PACKAGE));
#endif
if (fetchbuf == 0) {
printk("%s: no fetchbuf\n", __FUNCTION__);
return -ENOMEM;
}
/* hook stream buffer with PARSER */
#if HAS_HEVC_VDEC
if (is_hevc) {
WRITE_MPEG_REG(PARSER_VIDEO_START_PTR,
READ_VREG(HEVC_STREAM_START_ADDR));
WRITE_MPEG_REG(PARSER_VIDEO_END_PTR,
READ_VREG(HEVC_STREAM_END_ADDR) - 8);
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
WRITE_VREG(DOS_GEN_CTRL0, 3<<1); // set vififo_vbuf_rp_sel=>hevc
SET_VREG_MASK(HEVC_STREAM_CONTROL, (1<<3)|(0<<4)); // set use_parser_vbuf_wp
SET_VREG_MASK(HEVC_STREAM_CONTROL, 1); // set stream_fetch_enable
SET_VREG_MASK(HEVC_STREAM_FIFO_CTL, (1<<29)); // set stream_buffer_hole with 256 bytes
} else {
#endif
WRITE_MPEG_REG(PARSER_VIDEO_START_PTR,
READ_VREG(VLD_MEM_VIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_VIDEO_END_PTR,
READ_VREG(VLD_MEM_VIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_VREG_MASK(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
#if HAS_HEVC_VDEC
WRITE_VREG(DOS_GEN_CTRL0, 0); // set vififo_vbuf_rp_sel=>vdec
}
#endif
WRITE_MPEG_REG(PARSER_AUDIO_START_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_AUDIO_END_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR);
WRITE_MPEG_REG(PARSER_CONFIG,
(10 << PS_CFG_PFIFO_EMPTY_CNT_BIT) |
(1 << PS_CFG_MAX_ES_WR_CYCLE_BIT) |
(16 << PS_CFG_MAX_FETCH_CYCLE_BIT));
WRITE_MPEG_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_MPEG_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
WRITE_MPEG_REG(PARSER_SUB_START_PTR, parser_sub_start_ptr);
WRITE_MPEG_REG(PARSER_SUB_END_PTR, parser_sub_end_ptr);
WRITE_MPEG_REG(PARSER_SUB_RP, parser_sub_rp);
SET_MPEG_REG_MASK(PARSER_ES_CONTROL, (7 << ES_SUB_WR_ENDIAN_BIT) | ES_SUB_MAN_RD_PTR);
#if HAS_HEVC_VDEC
if ((r = pts_start((is_hevc) ? PTS_TYPE_HEVC : PTS_TYPE_VIDEO)) < 0) {
#else
if ((r = pts_start(PTS_TYPE_VIDEO)) < 0) {
#endif
printk("Video pts start failed.(%d)\n", r);
goto err1;
}
if ((r = pts_start(PTS_TYPE_AUDIO)) < 0) {
printk("Audio pts start failed.(%d)\n", r);
goto err2;
}
r = request_irq(INT_PARSER, parser_isr,
IRQF_SHARED, "tsdemux-fetch",
(void *)tsdemux_fetch_id);
if (r) {
goto err3;
}
WRITE_MPEG_REG(PARSER_INT_STATUS, 0xffff);
WRITE_MPEG_REG(PARSER_INT_ENABLE, PARSER_INTSTAT_FETCH_CMD << PARSER_INT_HOST_EN_BIT);
WRITE_MPEG_REG(PARSER_VIDEO_HOLE, 0x400);
WRITE_MPEG_REG(PARSER_AUDIO_HOLE, 0x400);
discontinued_counter = 0;
#ifndef ENABLE_DEMUX_DRIVER
r = request_irq(INT_DEMUX, tsdemux_isr,
IRQF_SHARED, "tsdemux-irq",
(void *)tsdemux_irq_id);
WRITE_MPEG_REG(STB_INT_MASK,
(1 << SUB_PES_READY)
| (1 << NEW_PDTS_READY)
| (1 << DIS_CONTINUITY_PACKET));
if (r) {
goto err4;
}
#else
tsdemux_config();
tsdemux_request_irq(tsdemux_isr, (void *)tsdemux_irq_id);
if (vid < 0x1FFF) {
tsdemux_set_vid(vid);
}
if (aid < 0x1FFF) {
tsdemux_set_aid(aid);
}
if (sid < 0x1FFF) {
tsdemux_set_sid(sid);
}
if ((pcrid < 0x1FFF) && (pcrid != vid) && (pcrid != aid) && (pcrid != sid)) {
tsdemux_set_pcrid(pcrid);
}
#endif
/* set paramater to fetch pcr */
pcr_num=0;
if(pcrid == vid)
pcr_num=0;
else if(pcrid == aid)
pcr_num=1;
else
pcr_num=3;
if(READ_MPEG_REG(TS_HIU_CTL_2) & 0x40){
WRITE_MPEG_REG(PCR90K_CTL_2, 12 << 1);
WRITE_MPEG_REG(ASSIGN_PID_NUMBER_2, pcr_num);
printk("[tsdemux_init] To use device 2,pcr_num=%d \n",pcr_num);
}
else if(READ_MPEG_REG(TS_HIU_CTL_3) & 0x40){
WRITE_MPEG_REG(PCR90K_CTL_3, 12 << 1);
WRITE_MPEG_REG(ASSIGN_PID_NUMBER_3, pcr_num);
printk("[tsdemux_init] To use device 3,pcr_num=%d \n",pcr_num);
}
else{
WRITE_MPEG_REG(PCR90K_CTL, 12 << 1);
WRITE_MPEG_REG(ASSIGN_PID_NUMBER, pcr_num);
printk("[tsdemux_init] To use device 1,pcr_num=%d \n",pcr_num);
}
pcrscr_valid=1;
return 0;
#ifndef ENABLE_DEMUX_DRIVER
err4:
free_irq(INT_PARSER, (void *)tsdemux_fetch_id);
#endif
err3:
pts_stop(PTS_TYPE_AUDIO);
err2:
#if HAS_HEVC_VDEC
pts_stop((is_hevc) ? PTS_TYPE_HEVC : PTS_TYPE_VIDEO);
#else
pts_stop(PTS_TYPE_VIDEO);
#endif
err1:
printk("TS Demux init failed.\n");
return -ENOENT;
}
void tsdemux_release(void)
{
pcrscr_valid=0;
WRITE_MPEG_REG(PARSER_INT_ENABLE, 0);
WRITE_MPEG_REG(PARSER_VIDEO_HOLE, 0);
WRITE_MPEG_REG(PARSER_AUDIO_HOLE, 0);
free_irq(INT_PARSER, (void *)tsdemux_fetch_id);
#ifndef ENABLE_DEMUX_DRIVER
WRITE_MPEG_REG(STB_INT_MASK, 0);
free_irq(INT_DEMUX, (void *)tsdemux_irq_id);
#else
tsdemux_set_aid(0xffff);
tsdemux_set_vid(0xffff);
tsdemux_set_sid(0xffff);
tsdemux_set_pcrid(0xffff);
tsdemux_free_irq();
#endif
pts_stop(PTS_TYPE_VIDEO);
pts_stop(PTS_TYPE_AUDIO);
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
switch_mod_gate_by_type(MOD_DEMUX, 0);
#endif
}
int tvoutc_setmode2(tvmode_t mode)
{
const reg_t *s;
if (mode >= TVMODE_MAX) {
printk(KERN_ERR "Invalid video output modes.\n");
return -ENODEV;
}
printk(KERN_DEBUG "TV mode %s selected.\n", tvinfoTab[mode].id);
s = tvregsTab[mode];
while (MREG_END_MARKER != s->reg)
setreg(s++);
//tvoutc_setclk2(mode);
//enable_vsync_interrupt();
switch(mode)
{
case TVMODE_480I:
case TVMODE_480CVBS:
case TVMODE_480P:
case TVMODE_576I:
case TVMODE_576CVBS:
case TVMODE_576P:
//WRITE_MPEG_REG(HHI_VIID_CLK_DIV, (READ_MPEG_REG(HHI_VIID_CLK_DIV)&(~(0xff)))|0x3); // reg 0x104a
break;
case TVMODE_720P:
case TVMODE_720P_50HZ:
case TVMODE_1080I:
case TVMODE_1080I_50HZ:
//WRITE_MPEG_REG(HHI_VIID_CLK_DIV, (READ_MPEG_REG(HHI_VIID_CLK_DIV)&(~(0xff)))|0x0); // reg 0x104a
break;
case TVMODE_1080P:
case TVMODE_1080P_50HZ:
//WRITE_MPEG_REG(HHI_VIID_CLK_DIV, (READ_MPEG_REG(HHI_VIID_CLK_DIV)&(~(0xff)))|0x1); // reg 0x104a
break;
default:
printk(KERN_ERR "unsupport tv mode,video clk is not set!!\n");
}
//WRITE_MPEG_REG(HHI_VIID_CLK_CNTL, 0x8001f); //reg 0x104b, select vid_pll_clk as source of v2_clk_divN
//WRITE_MPEG_REG(HHI_VID_CLK_DIV, (READ_MPEG_REG(HHI_VID_CLK_DIV)&(~(0xff<<24)))|(0x88<<24)); // reg 0x1059, select cts_encp_clk and cts_enci_clk from v2_clk_div1
WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 2, 2, 2); //reg0x271a, select ENCP to VIU2
WRITE_MPEG_REG(VPP2_POSTBLEND_H_SIZE, tvinfoTab[mode].xres);
// For debug only
#if 0
printk(" clk_util_clk_msr 6 = %d\n", clk_util_clk_msr(6));
printk(" clk_util_clk_msr 7 = %d\n", clk_util_clk_msr(7));
printk(" clk_util_clk_msr 8 = %d\n", clk_util_clk_msr(8));
printk(" clk_util_clk_msr 9 = %d\n", clk_util_clk_msr(9));
printk(" clk_util_clk_msr 10 = %d\n", clk_util_clk_msr(10));
printk(" clk_util_clk_msr 27 = %d\n", clk_util_clk_msr(27));
printk(" clk_util_clk_msr 29 = %d\n", clk_util_clk_msr(29));
#endif
//while(1);
return 0;
}