static int
sbwdog_setmode(struct sysmon_wdog *smw)
{
struct sbwdog_softc *sc = smw->smw_cookie;
if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
if (sc->sc_wdog_armed)
WRITE_REG(sc->sc_addr + R_SCD_WDOG_CFG, 0);
} else {
if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
sc->sc_wdog_period = SBWDOG_DEFAULT_PERIOD;
smw->smw_period = SBWDOG_DEFAULT_PERIOD; /* XXX needed?? */
} else if (smw->smw_period > 8) {
/* Maximum of 2^23 usec watchdog period. */
return (EINVAL);
}
sc->sc_wdog_period = smw->smw_period;
sc->sc_wdog_armed = 1;
WRITE_REG(sc->sc_addr + R_SCD_WDOG_INIT,
sc->sc_wdog_period * V_SCD_WDOG_FREQ);
/* Watchdog is armed by tickling it. */
sbwdog_tickle(smw);
}
return (0);
}
int rgu_dram_reserved(int enable)
{
volatile unsigned int tmp, ret = 0;
if(1 == enable)
{
/* enable ddr reserved mode */
tmp = READ_REG(MTK_WDT_MODE);
tmp |= (MTK_WDT_MODE_DDR_RESERVE|MTK_WDT_MODE_KEY);
WRITE_REG(tmp, MTK_WDT_MODE);
} else if(0 == enable)
{
/* disable ddr reserved mode, set reset mode,
disable watchdog output reset signal */
tmp = READ_REG(MTK_WDT_MODE);
tmp &= (~MTK_WDT_MODE_DDR_RESERVE);
tmp |= MTK_WDT_MODE_KEY;
WRITE_REG(tmp, MTK_WDT_MODE);
} else
{
print("Wrong input %d, should be 1(enable) or 0(disable) in %s\n", enable, __func__);
ret = -1;
}
print("RGU %s:MTK_WDT_MODE(%x)\n", __func__,tmp);
return ret;
}
/**
* @brief Initialize the WWDG according to the specified.
* parameters in the WWDG_InitTypeDef of associated handle.
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
* the configuration information for the specified WWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
{
/* Check the WWDG handle allocation */
if(hwwdg == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
/* Init the low level hardware */
HAL_WWDG_MspInit(hwwdg);
/* Set WWDG Counter */
WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
/* Set WWDG Prescaler and Window */
WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
/* Return function status */
return HAL_OK;
}
// Instruct the ad7877 to sense new values.
static int
sense(struct device *dev, struct adc_request *req)
{
struct ad7877 *ad = platform_get_drvdata(to_platform_device(dev));
int bitmap = 0;
int i;
int pin;
down(&dev->sem);
for (i=0; i < req->num_senses; i++)
bitmap |= 1 << (AD7877_NR_SENSE - req->senses[i].pin_id);
// Set pins to sense
ssp_putget(ad, WRITE_REG(REG_SEQREG0, bitmap));
// Start sense
ssp_putget(ad, WRITE_REG(REG_CR1, CR1_SLAVEMODE));
// Wait for IRQ, it will tell when sampling complete
wait_for_completion(&ad->comp);
pin = (REG_SENSORS + req->senses[0].pin_id) << CR1_OFF_READADDR;
ssp_putget(ad, WRITE_REG(REG_CR1, pin));
for (i = 0; i < req->num_senses - 1; i++) {
pin = (REG_SENSORS + req->senses[i+1].pin_id) <<
CR1_OFF_READADDR;
req->senses[i].value = ssp_putget(ad, WRITE_REG(REG_CR1, pin));
}
req->senses[i].value = ssp_putget(ad, 0);
up(&dev->sem);
return 0;
}
/**
* @brief Initializes the CRC according to the specified
* parameters in the CRC_InitTypeDef and creates the associated handle.
* @param hcrc: CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
{
/* Check the CRC handle allocation */
if(hcrc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
if(hcrc->State == HAL_CRC_STATE_RESET)
{
/* Init the low level hardware */
HAL_CRC_MspInit(hcrc);
}
hcrc->State = HAL_CRC_STATE_BUSY;
/* Extended initialization: if programmable polynomial feature is
applicable to device, set default or non-default generating
polynomial according to hcrc->Init parameters.
If feature is non-applicable to device in use, HAL_CRCEx_Init straight
away reports HAL_OK. */
if (HAL_CRCEx_Init(hcrc) != HAL_OK)
{
return HAL_ERROR;
}
/* check whether or not non-default CRC initial value has been
* picked up by user */
assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
{
WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
}
else
{
WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
}
/* set input data inversion mode */
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
/* set output data inversion mode */
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
/* makes sure the input data format (bytes, halfwords or words stream)
* is properly specified by user */
assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return function status */
return HAL_OK;
}
static int
txp_reset_adapter(struct txp_softc *sc)
{
u_int32_t r;
int i;
WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL);
DELAY(1000);
WRITE_REG(sc, TXP_SRR, 0);
/* Should wait max 6 seconds */
for (i = 0; i < 6000; i++) {
r = READ_REG(sc, TXP_A2H_0);
if (r == STAT_WAITING_FOR_HOST_REQUEST)
break;
DELAY(1000);
}
if (r != STAT_WAITING_FOR_HOST_REQUEST) {
if_printf(&sc->sc_arpcom.ac_if, "reset hung\n");
return (-1);
}
return (0);
}
// Setup the ad7877 with sensing values.
static void
initChip(struct ad7877 *ad)
{
// TMR=0, REF=0, POL=1, FCD=1, PM=2, ACQ=0, AVG=2
ssp_putget(ad, WRITE_REG(REG_CR2, 0x898));
// Power down DAC
ssp_putget(ad, WRITE_REG(REG_DAC, 0x8));
}
static void
time_smbus_init(int chan)
{
uint32_t reg;
reg = A_SMB_REGISTER(chan, R_SMB_FREQ);
WRITE_REG(reg, K_SMB_FREQ_100KHZ);
reg = A_SMB_REGISTER(chan, R_SMB_CONTROL);
WRITE_REG(reg, 0); /* not in direct mode, no interrupts, will poll */
}
/**
* Set the memory area to use for receiving packets.
*/
void enc_set_rx_area(uint16_t start, uint16_t end) {
WRITE_REG(ENC_ERXSTL, start & 0xFF);
WRITE_REG(ENC_ERXSTH, (start >> 8) & 0xFFF);
WRITE_REG(ENC_ERXNDL, end & 0xFF);
WRITE_REG(ENC_ERXNDH, (end >> 8) & 0xFFF);
WRITE_REG(ENC_ERXRDPTL, start & 0xFF);
WRITE_REG(ENC_ERXRDPTH, (start >> 8) & 0xFFF);
}
void ULCD::SET_SCALE(byte min, byte max, byte pos) {
WRITE_REG(72, min);
digitalPortWrite(56);
WRITE_REG(72, max);
digitalPortWrite(58);
WRITE_REG(72, 1);
digitalPortWrite(60);
WRITE_REG(72, pos);
digitalPortWrite(54);
}
static void
sbwdog_intr(void *v, uint32_t cause, vaddr_t pc)
{
struct sbwdog_softc *sc = v;
WRITE_REG(sc->sc_addr + R_SCD_WDOG_CFG, M_SCD_WDOG_ENABLE);
WRITE_REG(sc->sc_addr + R_SCD_WDOG_CFG, 0);
WRITE_REG(sc->sc_addr + R_SCD_WDOG_INIT,
sc->sc_wdog_period * V_SCD_WDOG_FREQ);
WRITE_REG(sc->sc_addr + R_SCD_WDOG_CFG, M_SCD_WDOG_ENABLE);
}
/**
* @brief Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.
* @param hswpmi: SWPMI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the SWPMI handle allocation */
if(hswpmi == NULL)
{
status = HAL_ERROR;
}
else
{
/* Check the parameters */
assert_param(IS_SWPMI_VOLTAGE_CLASS(hswpmi->Init.VoltageClass));
assert_param(IS_SWPMI_BITRATE_VALUE(hswpmi->Init.BitRate));
assert_param(IS_SWPMI_TX_BUFFERING_MODE(hswpmi->Init.TxBufferingMode));
assert_param(IS_SWPMI_RX_BUFFERING_MODE(hswpmi->Init.RxBufferingMode));
if(hswpmi->State == HAL_SWPMI_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hswpmi->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, CORTEX */
HAL_SWPMI_MspInit(hswpmi);
}
hswpmi->State = HAL_SWPMI_STATE_BUSY;
/* Disable SWPMI interface */
CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
/* Clear all SWPMI interface flags */
WRITE_REG(hswpmi->Instance->ICR, 0x019F);
/* Apply Voltage class selection */
MODIFY_REG(hswpmi->Instance->OR, SWPMI_OR_CLASS, hswpmi->Init.VoltageClass);
/* Configure the BRR register (Bitrate) */
WRITE_REG(hswpmi->Instance->BRR, hswpmi->Init.BitRate);
/* Apply SWPMI CR configuration */
MODIFY_REG(hswpmi->Instance->CR, \
SWPMI_CR_RXDMA | SWPMI_CR_TXDMA | SWPMI_CR_RXMODE | SWPMI_CR_TXMODE, \
hswpmi->Init.TxBufferingMode | hswpmi->Init.RxBufferingMode);
hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
hswpmi->State = HAL_SWPMI_STATE_READY;
/* Enable SWPMI peripheral if not */
SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
}
return status;
}
void ULCD::LOAD_TEXT(byte R, String Text) {
digitalPortWrite(8);
WRITE_REG(72, Text.length());
digitalPortWrite(10); //Устанавливаем длину контейнера
WRITE_REG(66, 0);
for (int i = 0; i < Text.length(); i++) {
WRITE_REG(72, Text[i]);
digitalPortWrite(17); //Помещаем байт в буффер
}
SEND_REG(R, 65);
}
void ULCD::LOAD_SCRIPT(byte R, byte Number) {
byte script[] = {2, 48, Number, 0, 0, 0};
digitalPortWrite(8);
WRITE_REG(72, 6);
digitalPortWrite(10); //Устанавливаем длину контейнера
WRITE_REG(66, 0);
for (int i = 0; i < 6; i++) {
WRITE_REG(72, script[i]);
digitalPortWrite(17); //Помещаем байт в буффер
}
SEND_REG(R, 65);
}
static void ar7_wdt_prescale(u32 value)
{
WRITE_REG(ar7_wdt->prescale_lock, 0x5a5a);
if ((READ_REG(ar7_wdt->prescale_lock) & 3) == 1) {
WRITE_REG(ar7_wdt->prescale_lock, 0xa5a5);
if ((READ_REG(ar7_wdt->prescale_lock) & 3) == 3) {
WRITE_REG(ar7_wdt->prescale, value);
return;
}
}
pr_err("failed to unlock WDT prescale reg\n");
}
static void ar7_wdt_kick(u32 value)
{
WRITE_REG(ar7_wdt->kick_lock, 0x5555);
if ((READ_REG(ar7_wdt->kick_lock) & 3) == 1) {
WRITE_REG(ar7_wdt->kick_lock, 0xaaaa);
if ((READ_REG(ar7_wdt->kick_lock) & 3) == 3) {
WRITE_REG(ar7_wdt->kick, value);
return;
}
}
pr_err("failed to unlock WDT kick reg\n");
}
static void ar7_wdt_change(u32 value)
{
WRITE_REG(ar7_wdt->change_lock, 0x6666);
if ((READ_REG(ar7_wdt->change_lock) & 3) == 1) {
WRITE_REG(ar7_wdt->change_lock, 0xbbbb);
if ((READ_REG(ar7_wdt->change_lock) & 3) == 3) {
WRITE_REG(ar7_wdt->change, value);
return;
}
}
pr_err("failed to unlock WDT change reg\n");
}
static void ar7_wdt_kick(u32 value)
{
WRITE_REG(ar7_wdt->kick_lock, 0x5555);
if ((READ_REG(ar7_wdt->kick_lock) & 3) == 1) {
WRITE_REG(ar7_wdt->kick_lock, 0xaaaa);
if ((READ_REG(ar7_wdt->kick_lock) & 3) == 3) {
WRITE_REG(ar7_wdt->kick, value);
return;
}
}
printk(KERN_ERR DRVNAME ": failed to unlock WDT kick reg\n");
}
/**
* Write value to PHY address.
* Reading procedure is described in ENC28J60 datasheet
* section 3.3.
*/
void enc_phy_write(uint8_t addr, uint16_t value) {
WRITE_REG(ENC_MIREGADR, addr);
WRITE_REG(ENC_MIWRL, value & 0xFF);
WRITE_REG(ENC_MIWRH, value >> 8);
MAP_SysCtlDelay(((MAP_SysCtlClockGet()/3)/1000));
uint8_t stat;
do {
stat = READ_MREG(ENC_MISTAT);
} while (stat & ENC_MISTAT_BUSY);
}
int rf69_set_antenna_impedance(struct spi_device *spi, enum antennaImpedance antennaImpedance)
{
#ifdef DEBUG
dev_dbg(&spi->dev, "set: antenna impedance");
#endif
switch (antennaImpedance) {
case fiftyOhm: return WRITE_REG(REG_LNA, (READ_REG(REG_LNA) & ~MASK_LNA_ZIN));
case twohundretOhm: return WRITE_REG(REG_LNA, (READ_REG(REG_LNA) | MASK_LNA_ZIN));
default:
dev_dbg(&spi->dev, "set: illegal input param");
return -EINVAL;
}
}
int rf69_set_tx_start_condition(struct spi_device *spi, enum txStartCondition txStartCondition)
{
#ifdef DEBUG
dev_dbg(&spi->dev, "set: start condition");
#endif
switch (txStartCondition) {
case fifoLevel: return WRITE_REG(REG_FIFO_THRESH, (READ_REG(REG_FIFO_THRESH) & ~MASK_FIFO_THRESH_TXSTART));
case fifoNotEmpty: return WRITE_REG(REG_FIFO_THRESH, (READ_REG(REG_FIFO_THRESH) | MASK_FIFO_THRESH_TXSTART));
default:
dev_dbg(&spi->dev, "set: illegal input param");
return -EINVAL;
}
}
int rf69_set_crc_enable(struct spi_device *spi, enum optionOnOff optionOnOff)
{
#ifdef DEBUG
dev_dbg(&spi->dev, "set: crc enable");
#endif
switch (optionOnOff) {
case optionOn: return WRITE_REG(REG_PACKETCONFIG1, (READ_REG(REG_PACKETCONFIG1) | MASK_PACKETCONFIG1_CRC_ON));
case optionOff: return WRITE_REG(REG_PACKETCONFIG1, (READ_REG(REG_PACKETCONFIG1) & ~MASK_PACKETCONFIG1_CRC_ON));
default:
dev_dbg(&spi->dev, "set: illegal input param");
return -EINVAL;
}
}
int rf69_set_packet_format(struct spi_device *spi, enum packetFormat packetFormat)
{
#ifdef DEBUG
dev_dbg(&spi->dev, "set: packet format");
#endif
switch (packetFormat) {
case packetLengthVar: return WRITE_REG(REG_PACKETCONFIG1, (READ_REG(REG_PACKETCONFIG1) | MASK_PACKETCONFIG1_PAKET_FORMAT_VARIABLE));
case packetLengthFix: return WRITE_REG(REG_PACKETCONFIG1, (READ_REG(REG_PACKETCONFIG1) & ~MASK_PACKETCONFIG1_PAKET_FORMAT_VARIABLE));
default:
dev_dbg(&spi->dev, "set: illegal input param");
return -EINVAL;
}
}
/**
* @brief DeInitializes the FSMC_NAND device
* @param Device: Pointer to NAND device instance
* @param Bank: NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FSMC_NAND_DEVICE(Device));
assert_param(IS_FSMC_NAND_BANK(Bank));
/* Disable the NAND Bank */
__FSMC_NAND_DISABLE(Device, Bank);
/* De-initialize the NAND Bank */
if(Bank == FSMC_NAND_BANK2)
{
/* Set the FSMC_NAND_BANK2 registers to their reset values */
WRITE_REG(Device->PCR2, 0x00000018);
WRITE_REG(Device->SR2, 0x00000040);
WRITE_REG(Device->PMEM2, 0xFCFCFCFC);
WRITE_REG(Device->PATT2, 0xFCFCFCFC);
}
/* FSMC_Bank3_NAND */
else
{
/* Set the FSMC_NAND_BANK3 registers to their reset values */
WRITE_REG(Device->PCR3, 0x00000018);
WRITE_REG(Device->SR3, 0x00000040);
WRITE_REG(Device->PMEM3, 0xFCFCFCFC);
WRITE_REG(Device->PATT3, 0xFCFCFCFC);
}
return HAL_OK;
}
int vfc_i2c_xmit_addr(struct vfc_dev *dev, unsigned char addr, char mode)
{
int ret, raddr;
#if 1
WRITE_S1(SEND_I2C_STOP | ACK);
WRITE_S1(SELECT(S0) | ENABLE_SERIAL);
vfc_i2c_delay(dev);
#endif
switch(mode) {
case VFC_I2C_READ:
raddr = SHIFT(((unsigned int)addr | 0x1));
WRITE_REG(raddr);
VFC_I2C_DEBUG_PRINTK(("vfc%d: receiving from i2c addr 0x%x\n",
dev->instance, addr | 0x1));
break;
case VFC_I2C_WRITE:
raddr = SHIFT((unsigned int)addr & ~0x1);
WRITE_REG(raddr);
VFC_I2C_DEBUG_PRINTK(("vfc%d: sending to i2c addr 0x%x\n",
dev->instance, addr & ~0x1));
break;
default:
return -EINVAL;
};
WRITE_S1(SEND_I2C_START);
vfc_i2c_delay(dev);
ret = vfc_i2c_wait_for_pin(dev,VFC_I2C_ACK_CHECK); /* We wait
for the
i2c send
to finish
here but
Sun
doesn't,
hmm */
if (ret) {
printk(KERN_ERR "vfc%d: VFC xmit addr timed out or no ack\n",
dev->instance);
return ret;
} else if (mode == VFC_I2C_READ) {
if ((ret = sbus_readl(&dev->regs->i2c_reg) & 0xff000000) != raddr) {
printk(KERN_WARNING
"vfc%d: returned slave address "
"mismatch(%x,%x)\n",
dev->instance, raddr, ret);
}
}
return 0;
}
int rf69_set_amplifier_2(struct spi_device *spi, enum optionOnOff optionOnOff)
{
#ifdef DEBUG
dev_dbg(&spi->dev, "set: amp #2");
#endif
switch (optionOnOff) {
case optionOn: return WRITE_REG(REG_PALEVEL, (READ_REG(REG_PALEVEL) | MASK_PALEVEL_PA2));
case optionOff: return WRITE_REG(REG_PALEVEL, (READ_REG(REG_PALEVEL) & ~MASK_PALEVEL_PA2));
default:
dev_dbg(&spi->dev, "set: illegal input param");
return -EINVAL;
}
}
void dqsi_gw_dly_coarse_factor_handler(char *factor_value)
{
int curr_val = atoi(factor_value);
WRITE_REG((READ_REG(DRAMC_DQSCTL0/* 0xDC */) & 0xFF000000) /* Reserve original values for DRAMC_DQSCTL0[24:31] */
| ((curr_val & 0xFFF) << 0) /* DQS0CTL: DRAMC_DQSCTL0[0:11], 12 bits */
| ((curr_val & 0xFFF) << 12), /* DQS1CTL: DRAMC_DQSCTL0[12:23], 12 bits */
DRAMC_DQSCTL0/* 0xDC */);
WRITE_REG((READ_REG(DRAMC_DQSCTL1/* 0xE0 */) & 0xFF000000) /* Reserve original values for DRAMC_DQSCTL1[24:31] */
| ((curr_val & 0xFFF) << 0) /* DQS2CTL: DRAMC_DQSCTL1[0:11], 12 bits */
| ((curr_val & 0xFFF) << 12), /* DQS3CTL: DRAMC_DQSCTL1[12:23], 12 bits */
DRAMC_DQSCTL1/* 0xE0 */);
}
int rf69_set_fifo_fill_condition(struct spi_device *spi, enum fifoFillCondition fifoFillCondition)
{
#ifdef DEBUG
dev_dbg(&spi->dev, "set: fifo fill condition");
#endif
switch (fifoFillCondition) {
case always: return WRITE_REG(REG_SYNC_CONFIG, (READ_REG(REG_SYNC_CONFIG) | MASK_SYNC_CONFIG_FIFO_FILL_CONDITION));
case afterSyncInterrupt: return WRITE_REG(REG_SYNC_CONFIG, (READ_REG(REG_SYNC_CONFIG) & ~MASK_SYNC_CONFIG_FIFO_FILL_CONDITION));
default:
dev_dbg(&spi->dev, "set: illegal input param");
return -EINVAL;
}
}
int rf69_set_modulation(struct spi_device *spi, enum modulation modulation)
{
#ifdef DEBUG
dev_dbg(&spi->dev, "set: modulation");
#endif
switch (modulation) {
case OOK: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_TYPE) | DATAMODUL_MODULATION_TYPE_OOK);
case FSK: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_TYPE) | DATAMODUL_MODULATION_TYPE_FSK);
default:
dev_dbg(&spi->dev, "set: illegal input param");
return -EINVAL;
}
}
static void hiir_config(void)
{
int value = 0;
/* TODO: ASIC config pin share */
#if 0
value = READ_REG(IOCONFIG);
value = 0;
WRITE_REG(IOCONFIG, value);
#endif
WRITE_REG(IR_ENABLE, 0x01);
while(READ_REG(IR_BUSY))
{
hiir_dbg("IR_BUSY. Wait...\n");
//udelay(1);
}
value = (hiir_dev.dev_parm.codetype << 14);
value |= (hiir_dev.dev_parm.code_len - 1) << 8;
value |= (hiir_dev.dev_parm.frequence - 1);
WRITE_REG(IR_CONFIG, value);
value = hiir_dev.dev_parm.leads_min << 16;
value |= hiir_dev.dev_parm.leads_max;
WRITE_REG(CNT_LEADS, value);
value = hiir_dev.dev_parm.leade_min << 16;
value |= hiir_dev.dev_parm.leade_max;
WRITE_REG(CNT_LEADE, value);
value = hiir_dev.dev_parm.sleade_min << 16;
value |= hiir_dev.dev_parm.sleade_max;
WRITE_REG(CNT_SLEADE, value);
value = hiir_dev.dev_parm.cnt0_b_min << 16;
value |= hiir_dev.dev_parm.cnt0_b_max;
WRITE_REG(CNT0_B, value);
value = hiir_dev.dev_parm.cnt1_b_min << 16;
value |= hiir_dev.dev_parm.cnt1_b_max;
WRITE_REG(CNT1_B, value);
WRITE_REG(IR_INTM, 0x00);
WRITE_REG(IR_START, 0x00);
//hiir_dbg("current config is...\n");
//hiir_show_reg();
}