void display_crtc_fb_set(uint8 crtcID, display_mode* mode) { radeon_shared_info &info = *gInfo->shared_info; register_info* regs = gDisplay[crtcID]->regs; uint16* r = info.color_data; uint16* g = r + 256; uint16* b = r + 512; uint32 fbSwap; if (info.dceMajor >= 4) fbSwap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); else fbSwap = R600_D1GRPH_SWAP_ENDIAN_NONE; uint32 fbFormat; uint32 bytesPerPixel; uint32 bitsPerPixel; switch (mode->space) { case B_CMAP8: bytesPerPixel = 1; bitsPerPixel = 8; if (info.dceMajor >= 4) { fbFormat = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); } else { fbFormat = AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; } // TODO: copy system color map into shared info break; case B_RGB15_LITTLE: bytesPerPixel = 2; bitsPerPixel = 15; if (info.dceMajor >= 4) { fbFormat = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); } else { fbFormat = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; } break; case B_RGB16_LITTLE: bytesPerPixel = 2; bitsPerPixel = 16; if (info.dceMajor >= 4) { fbFormat = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); #ifdef __POWERPC__ fbSwap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); #endif } else { fbFormat = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; #ifdef __POWERPC__ fbSwap = R600_D1GRPH_SWAP_ENDIAN_16BIT; #endif } { // default gamma table uint16 gamma = 0; for (int i = 0; i < 256; i++) { r[i] = gamma; g[i] = gamma; b[i] = gamma; gamma += 4; } } break; case B_RGB24_LITTLE: case B_RGB32_LITTLE: default: bytesPerPixel = 4; bitsPerPixel = 32; if (info.dceMajor >= 4) { fbFormat = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); #ifdef __POWERPC__ fbSwap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); #endif } else { fbFormat = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; #ifdef __POWERPC__ fbSwap = R600_D1GRPH_SWAP_ENDIAN_32BIT; #endif } { // default gamma table uint16 gamma = 0; for (int i = 0; i < 256; i++) { r[i] = gamma; g[i] = gamma; b[i] = gamma; gamma += 4; } } break; } Write32(OUT, regs->vgaControl, 0); uint64 fbAddress = gInfo->fb.vramStart; TRACE("%s: Framebuffer at: 0x%" B_PRIX64 "\n", __func__, fbAddress); if (info.chipsetID >= RADEON_RV770) { TRACE("%s: Set SurfaceAddress High: 0x%" B_PRIX32 "\n", __func__, (fbAddress >> 32) & 0xf); Write32(OUT, regs->grphPrimarySurfaceAddrHigh, (fbAddress >> 32) & 0xf); Write32(OUT, regs->grphSecondarySurfaceAddrHigh, (fbAddress >> 32) & 0xf); }
void display_avivo_crtc_load_lut(uint8 crtcID) { radeon_shared_info &info = *gInfo->shared_info; register_info* regs = gDisplay[crtcID]->regs; TRACE("%s: crtcID %" B_PRIu8 "\n", __func__, crtcID); uint16* r = info.color_data; uint16* g = r + 256; uint16* b = r + 512; Write32(OUT, AVIVO_DC_LUTA_CONTROL + regs->crtcOffset, 0); Write32(OUT, AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + regs->crtcOffset, 0); Write32(OUT, AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + regs->crtcOffset, 0); Write32(OUT, AVIVO_DC_LUTA_BLACK_OFFSET_RED + regs->crtcOffset, 0); Write32(OUT, AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + regs->crtcOffset, 0xffff); Write32(OUT, AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + regs->crtcOffset, 0xffff); Write32(OUT, AVIVO_DC_LUTA_WHITE_OFFSET_RED + regs->crtcOffset, 0xffff); Write32(OUT, AVIVO_DC_LUT_RW_SELECT, crtcID); Write32(OUT, AVIVO_DC_LUT_RW_MODE, 0); Write32(OUT, AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); Write32(OUT, AVIVO_DC_LUT_RW_INDEX, 0); for (int i = 0; i < 256; i++) { Write32(OUT, AVIVO_DC_LUT_30_COLOR, (r[i] << 20) | (g[i] << 10) | (b[i] << 0)); } Write32(OUT, AVIVO_D1GRPH_LUT_SEL + regs->crtcOffset, crtcID); }
bool Memory::LoadELF(const char *filename, u32 &entry) { Elf32_Ehdr ehdr; Elf32_Phdr *phdr; ifstream File; u32 phoff; u16 phnum, shnum; bool ret; /* Open file */ File.open(filename); /* Check if open */ ret = File.is_open(); if (!ret) return false; /* Read ELF header */ File.read((char *)&ehdr, sizeof(ehdr)); /* Header parameters */ phnum = Swap16(ehdr.e_phnum); phoff = Swap32(ehdr.e_phoff); shnum = Swap16(ehdr.e_shnum); entry = Swap32(ehdr.e_entry); printf("Entry point: 0x%08X\n", entry); /* Allocate array */ phdr = new Elf32_Phdr[phnum]; if (!phdr) { ret = false; goto out; } /* Read program headers */ File.seekg(phoff, ios::beg); File.read ((char *)phdr, sizeof(*phdr) * phnum); printf("\n"); printf("Program headers:\n"); printf("================\n"); for (u32 i = 0; i < phnum; i++) { u32 filesz = Swap32(phdr[i].p_filesz); u32 memsz = Swap32(phdr[i].p_memsz); u32 offset = Swap32(phdr[i].p_offset); u32 paddr = Swap32(phdr[i].p_paddr); u32 vaddr = Swap32(phdr[i].p_vaddr); u32 flags = Swap32(phdr[i].p_flags); printf("[%d] off 0x%08X vaddr 0x%08X paddr 0x%08X\n", i, offset, vaddr, paddr); printf(" filesz 0x%08X memsz 0x%08X flags %06X\n", filesz, memsz, flags); /* Create virtual space */ ret = Create(vaddr, memsz); if (!ret) goto out; /* Read data from file */ if (filesz) { /* Move to offset */ File.seekg(offset, ios::beg); for(u32 j = 0; j < filesz; j += 4) { u32 value; /* Read word */ File.read((char *)&value, sizeof(value)); /* Write word */ Write32(vaddr + j, Swap32(value)); } } } printf("\n"); out: /* Free array */ delete[] phdr; /* Close file */ File.close(); return ret; }
void display_dce45_crtc_load_lut(uint8 crtcID) { radeon_shared_info &info = *gInfo->shared_info; register_info* regs = gDisplay[crtcID]->regs; TRACE("%s: crtcID %" B_PRIu8 "\n", __func__, crtcID); uint16* r = info.color_data; uint16* g = r + 256; uint16* b = r + 512; if (info.dceMajor >= 5) { Write32(OUT, NI_INPUT_CSC_CONTROL + regs->crtcOffset, (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); Write32(OUT, NI_PRESCALE_GRPH_CONTROL + regs->crtcOffset, NI_GRPH_PRESCALE_BYPASS); Write32(OUT, NI_PRESCALE_OVL_CONTROL + regs->crtcOffset, NI_OVL_PRESCALE_BYPASS); Write32(OUT, NI_INPUT_GAMMA_CONTROL + regs->crtcOffset, (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); } Write32(OUT, EVERGREEN_DC_LUT_CONTROL + regs->crtcOffset, 0); Write32(OUT, EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + regs->crtcOffset, 0); Write32(OUT, EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + regs->crtcOffset, 0); Write32(OUT, EVERGREEN_DC_LUT_BLACK_OFFSET_RED + regs->crtcOffset, 0); Write32(OUT, EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + regs->crtcOffset, 0xffff); Write32(OUT, EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + regs->crtcOffset, 0xffff); Write32(OUT, EVERGREEN_DC_LUT_WHITE_OFFSET_RED + regs->crtcOffset, 0xffff); Write32(OUT, EVERGREEN_DC_LUT_RW_MODE, 0); Write32(OUT, EVERGREEN_DC_LUT_WRITE_EN_MASK, 0x00000007); Write32(OUT, EVERGREEN_DC_LUT_RW_INDEX, 0); for (int i = 0; i < 256; i++) { Write32(OUT, EVERGREEN_DC_LUT_30_COLOR + regs->crtcOffset, (r[i] << 20) | (g[i] << 10) | (b[i] << 0)); } if (info.dceMajor >= 5) { Write32(OUT, NI_DEGAMMA_CONTROL + regs->crtcOffset, (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); Write32(OUT, NI_GAMUT_REMAP_CONTROL + regs->crtcOffset, (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); Write32(OUT, NI_REGAMMA_CONTROL + regs->crtcOffset, (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); Write32(OUT, NI_OUTPUT_CSC_CONTROL + regs->crtcOffset, (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) | NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); /* XXX match this to the depth of the crtc fmt block, move to modeset? */ Write32(OUT, 0x6940 + regs->crtcOffset, 0); } }
bool MemoryBase::Write32NN(u64 addr, const u32 data) { if(!IsGoodAddr(addr, 4)) return false; Write32(addr, data); return true; }