int DMA_init(u16 DeviceId) {
XAxiDma_Config *CfgPtr;
int Status;
CfgPtr = XAxiDma_LookupConfig(DeviceId);
if (!CfgPtr) {
xil_printf("No config found for %d\r\n", DeviceId);
return XST_FAILURE;
}
Status = XAxiDma_CfgInitialize(&AxiDma, CfgPtr);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed %d\r\n", Status);
return XST_FAILURE;
}
if(XAxiDma_HasSg(&AxiDma)){
xil_printf("Device configured as SG mode\r\n");
return XST_FAILURE;
}
/* Disable interrupts, we use polling mode
*/
//XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DEVICE_TO_DMA);
XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DMA_TO_DEVICE);
return XST_SUCCESS;
}
/////////////////////////////////////////////////
//
// initialize first DMA function
//
/////////////////////////////////////////////////
int init_dma(){
XAxiDma_Config *CfgPtr;
int status;
CfgPtr = XAxiDma_LookupConfig(XPAR_AXI_DMA_0_DEVICE_ID);
if(!CfgPtr){
print("Error looking for AXI DMA config\n\r");
return XST_FAILURE;
}
status = XAxiDma_CfgInitialize(&AxiDma,CfgPtr);
if(status != XST_SUCCESS){
print("Error initializing DMA 0\n\r");
return XST_FAILURE;
}
//check for scatter gather mode
if(XAxiDma_HasSg(&AxiDma)){
print("Error DMA configured in SG mode\n\r");
return XST_FAILURE;
}
/* Disable interrupts, we use polling mode */
XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,XAXIDMA_DEVICE_TO_DMA);
XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,XAXIDMA_DMA_TO_DEVICE);
return XST_SUCCESS;
}
// A function that wraps all AXI DMA initialization related API calls
int init_dma(XAxiDma *axiDmaPtr){
XAxiDma_Config *CfgPtr;
int status;
// Get pointer to DMA configuration
CfgPtr = XAxiDma_LookupConfig(XPAR_AXIDMA_0_DEVICE_ID);
if(!CfgPtr){
print("Error looking for AXI DMA config\n\r");
return XST_FAILURE;
}
// Initialize the DMA handle
status = XAxiDma_CfgInitialize(axiDmaPtr,CfgPtr);
if(status != XST_SUCCESS){
print("Error initializing DMA\n\r");
return XST_FAILURE;
}
//check for scatter gather mode - this example must have simple mode only
if(XAxiDma_HasSg(axiDmaPtr)){
print("Error DMA configured in SG mode\n\r");
return XST_FAILURE;
}
//disable the interrupts
XAxiDma_IntrDisable(axiDmaPtr, XAXIDMA_IRQ_ALL_MASK,XAXIDMA_DEVICE_TO_DMA);
XAxiDma_IntrDisable(axiDmaPtr, XAXIDMA_IRQ_ALL_MASK,XAXIDMA_DMA_TO_DEVICE);
return XST_SUCCESS;
}
int Init_Zycap(XScuGic * InterruptController)
{
int Status;
fatfs=malloc(sizeof(FATFS));
Status = SD_Init(fatfs);
if (Status != XST_SUCCESS) {
print("file system init failed\n\r");
exit(XST_FAILURE);
}
XDcfg_0 = XDcfg_Initialize(XPAR_XDCFG_0_DEVICE_ID);
CdmaCfgPtr = XAxiDma_LookupConfig(XPAR_AXI_DMA_0_DEVICE_ID);
if (!CdmaCfgPtr) {
xil_printf("DMA pointer failed\r\n");
return XST_FAILURE;
}
Status = XAxiDma_CfgInitialize(&xcdma , CdmaCfgPtr);
if (Status != XST_SUCCESS) {
xil_printf("DMA initialization failed\r\n",Status);
return XST_FAILURE;
}
//print("DMA init done\n\r");
Status = SetupIntrSystem(InterruptController, &xcdma, TX_INTR_ID);
if (Status != XST_SUCCESS) {
xil_printf("Failed intr setup\r\n");
return XST_FAILURE;
}
//Enable all interrupts
XAxiDma_IntrEnable(&xcdma, XAXIDMA_IRQ_ALL_MASK,XAXIDMA_DMA_TO_DEVICE);
bs_list = init_bs_list(MAX_BS_NUM);
return XST_SUCCESS;
}
/**
*
* Main function
*
* This function is the main entry of the tests on DMA core. It sets up
* DMA engine to be ready to receive and send packets, then a packet is
* transmitted and will be verified after it is received via the DMA loopback
* widget.
*
* @param None
*
* @return
* - XST_SUCCESS if test passes
* - XST_FAILURE if test fails.
*
* @note None.
*
******************************************************************************/
int main(void)
{
int Status;
XAxiDma_Config *Config;
init_platform();
xil_printf("\r\n--- Entering main() --- \r\n");
Config = XAxiDma_LookupConfig(DMA_DEV_ID);
if (!Config) {
xil_printf("No config found for %d\r\n", DMA_DEV_ID);
return XST_FAILURE;
}
/* Initialize DMA engine */
Status = XAxiDma_CfgInitialize(&AxiDma, Config);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed %d\r\n", Status);
return XST_FAILURE;
}
if(!XAxiDma_HasSg(&AxiDma)) {
xil_printf("Device configured as Simple mode \r\n");
return XST_FAILURE;
}
Status = TxSetup(&AxiDma);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
Status = RxSetup(&AxiDma);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Send a packet */
Status = SendPacket(&AxiDma);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Check DMA transfer result */
Status = CheckDmaResult(&AxiDma);
xil_printf("AXI DMA SG Polling Test %s\r\n",
(Status == XST_SUCCESS)? "passed":"failed");
xil_printf("--- Exiting main() --- \r\n");
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
return XST_SUCCESS;
}
/**
*
* Main function
*
* This function is the main entry of the tests on DMA core. It sets up
* DMA engine to be ready to receive and send packets, then a packet is
* transmitted and will be verified after it is received via the loopback on the
* Local Link interface of the DMA.
*
* @return 0 if tests pass, 1 otherwise.
*
* @note None.
*
******************************************************************************/
int main(void)
{
int Status;
XAxiDma_Config *Config;
#if defined(XPAR_UARTNS550_0_BASEADDR)
Uart550_Setup();
#endif
xil_printf("\r\n--- Entering main() --- \r\n");
Config = XAxiDma_LookupConfig(DMA_DEV_ID);
if (!Config) {
xdbg_printf(XDBG_DEBUG_ERROR,
"No config found for %d\r\n", DMA_DEV_ID);
return 1;
}
/* Initialize DMA engine */
Status = XAxiDma_CfgInitialize(&AxiDma, Config);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed %d\r\n", Status);
return 1;
}
Status = TxSetup(&AxiDma);
if (Status != XST_SUCCESS) {
return 1;
}
Status = RxSetup(&AxiDma);
if (Status != XST_SUCCESS) {
return 1;
}
/* Send a packet */
Status = SendPacket(&AxiDma);
if (Status != XST_SUCCESS) {
return 1;
}
/* Check DMA transfer result */
Status = CheckDmaResult(&AxiDma);
xil_printf("Test %s\r\n",
(Status == XST_SUCCESS)? "passed":"failed");
xil_printf("--- Exiting main() --- \r\n");
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
return 0;
}
int wlan_eth_dma_init() {
int status;
int bd_count;
int i;
u32 buf_addr;
XAxiDma_Config *ETH_A_DMA_CFG_ptr;
XAxiDma_Bd ETH_DMA_BD_Template;
XAxiDma_BdRing *ETH_A_TxRing_ptr;
XAxiDma_BdRing *ETH_A_RxRing_ptr;
XAxiDma_Bd *first_bd_ptr;
XAxiDma_Bd *cur_bd_ptr;
packet_bd_list checkout;
packet_bd* tx_queue;
ETH_A_DMA_CFG_ptr = XAxiDma_LookupConfig(ETH_A_DMA_DEV_ID);
status = XAxiDma_CfgInitialize(Ð_A_DMA_Instance, ETH_A_DMA_CFG_ptr);
if(status != XST_SUCCESS) {xil_printf("Error in XAxiDma_CfgInitialize! Err = %d\n", status); return -1;}
//Zero-out the template buffer descriptor
XAxiDma_BdClear(Ð_DMA_BD_Template);
//Fetch handles to the Tx and Rx BD rings
ETH_A_TxRing_ptr = XAxiDma_GetTxRing(Ð_A_DMA_Instance);
ETH_A_RxRing_ptr = XAxiDma_GetRxRing(Ð_A_DMA_Instance);
//Disable all Tx/Rx DMA interrupts
XAxiDma_BdRingIntDisable(ETH_A_TxRing_ptr, XAXIDMA_IRQ_ALL_MASK);
XAxiDma_BdRingIntDisable(ETH_A_RxRing_ptr, XAXIDMA_IRQ_ALL_MASK);
//Disable delays and coalescing (for now - these will be useful when we transition to interrupts)
XAxiDma_BdRingSetCoalesce(ETH_A_TxRing_ptr, 1, 0);
XAxiDma_BdRingSetCoalesce(ETH_A_RxRing_ptr, 1, 0);
//Setup Tx/Rx buffer descriptor rings in memory
status = XAxiDma_BdRingCreate(ETH_A_TxRing_ptr, ETH_A_TX_BD_SPACE_BASE, ETH_A_TX_BD_SPACE_BASE, XAXIDMA_BD_MINIMUM_ALIGNMENT, ETH_A_NUM_TX_BD);
status |= XAxiDma_BdRingCreate(ETH_A_RxRing_ptr, ETH_A_RX_BD_SPACE_BASE, ETH_A_RX_BD_SPACE_BASE, XAXIDMA_BD_MINIMUM_ALIGNMENT, ETH_A_NUM_RX_BD);
if(status != XST_SUCCESS) {xil_printf("Error creating DMA BD Rings! Err = %d\n", status); return -1;}
//Populate each ring with empty buffer descriptors
status = XAxiDma_BdRingClone(ETH_A_TxRing_ptr, Ð_DMA_BD_Template);
status |= XAxiDma_BdRingClone(ETH_A_RxRing_ptr, Ð_DMA_BD_Template);
if(status != XST_SUCCESS) {xil_printf("Error in XAxiDma_BdRingClone()! Err = %d\n", status); return -1;}
//Start the DMA Tx channel
// No Eth packets are transmitted until actual Tx BD's are pushed to the DMA hardware
status = XAxiDma_BdRingStart(ETH_A_TxRing_ptr);
//Initialize the Rx buffer descriptors
bd_count = XAxiDma_BdRingGetFreeCnt(ETH_A_RxRing_ptr);
if(bd_count != ETH_A_NUM_RX_BD) {xil_printf("Error in Eth Rx DMA init - not all Rx BDs were free at boot\n");}
status = XAxiDma_BdRingAlloc(ETH_A_RxRing_ptr, bd_count, &first_bd_ptr);
if(status != XST_SUCCESS) {xil_printf("Error in XAxiDma_BdRingAlloc()! Err = %d\n", status); return -1;}
//Checkout ETH_A_NUM_RX_BD packet_bds
queue_checkout(&checkout, ETH_A_NUM_RX_BD);
if(checkout.length == ETH_A_NUM_RX_BD){
tx_queue = checkout.first;
} else {
xil_printf("Error during wlan_eth_dma_init: able to check out %d of %d packet_bds\n", checkout.length, ETH_A_NUM_RX_BD);
return -1;
}
//Iterate over each Rx buffer descriptor
cur_bd_ptr = first_bd_ptr;
for(i = 0; i < bd_count; i++) {
//Set the memory address for this BD's buffer
buf_addr = (u32)((void*)((tx_packet_buffer*)(tx_queue->buf_ptr))->frame + sizeof(mac_header_80211) + sizeof(llc_header) - sizeof(ethernet_header));
status = XAxiDma_BdSetBufAddr(cur_bd_ptr, buf_addr);
if(status != XST_SUCCESS) {xil_printf("XAxiDma_BdSetBufAddr failed (bd %d, addr 0x08x)! Err = %d\n", i, buf_addr, status); return -1;}
//Set every Rx BD to max length (this assures 1 BD per Rx pkt)
status = XAxiDma_BdSetLength(cur_bd_ptr, ETH_A_PKT_BUF_SIZE, ETH_A_RxRing_ptr->MaxTransferLen);
if(status != XST_SUCCESS) {xil_printf("XAxiDma_BdSetLength failed (bd %d, addr 0x08x)! Err = %d\n", i, buf_addr, status); return -1;}
//Rx BD's don't need control flags before use; DMA populates these post-Rx
XAxiDma_BdSetCtrl(cur_bd_ptr, 0);
//BD ID is arbitrary; use pointer to the packet_bd associated with this BD
XAxiDma_BdSetId(cur_bd_ptr, (u32)tx_queue);
//Update cur_bd_ptr to the next BD in the chain for the next iteration
cur_bd_ptr = XAxiDma_BdRingNext(ETH_A_RxRing_ptr, cur_bd_ptr);
//Traverse forward in the checked-out packet_bd list
tx_queue = tx_queue->next;
}
//Push the Rx BD ring to hardware and start receiving
status = XAxiDma_BdRingToHw(ETH_A_RxRing_ptr, bd_count, first_bd_ptr);
//Enable Interrupts
XAxiDma_BdRingIntEnable(ETH_A_RxRing_ptr, XAXIDMA_IRQ_ALL_MASK);
status |= XAxiDma_BdRingStart(ETH_A_RxRing_ptr);
if(status != XST_SUCCESS) {xil_printf("Error in XAxiDma_BdRingToHw/XAxiDma_BdRingStart(ETH_A_RxRing_ptr)! Err = %d\n", status); return -1;}
return 0;
}
/**
*
* Main function
*
* This function is the main entry of the interrupt test. It does the following:
* - Set up the output terminal if UART16550 is in the hardware build
* - Initialize the DMA engine
* - Set up Tx and Rx channels
* - Set up the interrupt system for the Tx and Rx interrupts
* - Submit a transfer
* - Wait for the transfer to finish
* - Check transfer status
* - Disable Tx and Rx interrupts
* - Print test status and exit
*
* @param None
*
* @return - XST_SUCCESS if tests pass
* - XST_FAILURE if fails.
*
* @note None.
*
******************************************************************************/
int main(void)
{
int Status;
XAxiDma_Config *Config;
/* Initial setup for Uart16550 */
#ifdef XPAR_UARTNS550_0_BASEADDR
Uart550_Setup();
#endif
xil_printf("\r\n--- Entering main() --- \r\n");
Config = XAxiDma_LookupConfig(DMA_DEV_ID);
if (!Config) {
xil_printf("No config found for %d\r\n", DMA_DEV_ID);
return XST_FAILURE;
}
/* Initialize DMA engine */
XAxiDma_CfgInitialize(&AxiDma, Config);
if(!XAxiDma_HasSg(&AxiDma)) {
xil_printf("Device configured as Simple mode \r\n");
return XST_FAILURE;
}
/* Set up TX/RX channels to be ready to transmit and receive packets */
Status = TxSetup(&AxiDma);
if (Status != XST_SUCCESS) {
xil_printf("Failed TX setup\r\n");
return XST_FAILURE;
}
Status = RxSetup(&AxiDma);
if (Status != XST_SUCCESS) {
xil_printf("Failed RX setup\r\n");
return XST_FAILURE;
}
/* Set up Interrupt system */
Status = SetupIntrSystem(&Intc, &AxiDma, TX_INTR_ID,
RX_INTR_ID, 1);
if (Status != XST_SUCCESS) {
xil_printf("Failed intr setup\r\n");
return XST_FAILURE;
}
/* Initialize flags before start transfer test */
TxDone = 0;
RxDone = 0;
Error = 0;
/* Send a packet */
Status = SendPacket(&AxiDma, TDEST0, TID0, PACKET0_DATA);
if (Status != XST_SUCCESS) {
xil_printf("Failed send packet\r\n");
return XST_FAILURE;
}
/*
* Wait TX done and RX done
*/
while (((TxDone < NUMBER_OF_BDS_TO_TRANSFER) ||
(RxDone < NUMBER_OF_BDS_TO_TRANSFER)) && !Error) {
/* NOP */
}
if (Error) {
xil_printf("Failed test transmit%s done, "
"receive%s done\r\n", TxDone? "":" not",
RxDone? "":" not");
goto Done;
}else {
/*
* Test finished, check data
*/
Status = CheckData(MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER,
RxPacket1, PACKET0_DATA);
if (Status != XST_SUCCESS) {
xil_printf("Data check failed\r\n");
goto Done;
}
}
xil_printf("Sent Packet with Tdest 0 Successfully\n\r");
/* Initialize flags before start transfer test */
TxDone = 0;
RxDone = 0;
Error = 0;
/* Send a packet */
Status = SendPacket(&AxiDma, TDEST1, TID1, PACKET1_DATA);
if (Status != XST_SUCCESS) {
xil_printf("Failed send packet\r\n");
return XST_FAILURE;
}
/*
* Wait TX done and RX done
*/
while (((TxDone < NUMBER_OF_BDS_TO_TRANSFER) ||
(RxDone < NUMBER_OF_BDS_TO_TRANSFER)) && !Error) {
/* NOP */
}
if (Error) {
xil_printf("Failed test transmit%s done, "
"receive%s done\r\n", TxDone? "":" not",
RxDone? "":" not");
goto Done;
}else {
/*
* Test finished, check data
*/
Status = CheckData(MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER,
RxPacket0, PACKET1_DATA);
if (Status != XST_SUCCESS) {
xil_printf("Data check failed\r\n");
goto Done;
}
}
/* Disable TX and RX Ring interrupts and return success */
DisableIntrSystem(&Intc, TX_INTR_ID, RX_INTR_ID);
xil_printf("Sent Packet with Tdest 1 Successfully\n\r");
xil_printf("AXI DMA SG interrupt Test passed\r\n");
Done:
xil_printf("--- Exiting main() --- \r\n");
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
return XST_SUCCESS;
}
int
init_platform()
{
enable_caches();
/* if we have a uart 16550, then that needs to be initialized */
#ifdef STDOUT_IS_16550
XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, 9600);
XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
#endif
/* Get DMA configs */
ddc_dma_attr.AxiDmaConfig = XAxiDma_LookupConfig(BPM_DDC_DMA_DEV_ID);
fmc150_adc_dma_attr.AxiDmaConfig = XAxiDma_LookupConfig(BPM_ADC_DMA_DEV_ID);
// Initialize DMA engine
if(XAxiDma_CfgInitialize(&ddc_dma_attr.AxiDma, ddc_dma_attr.AxiDmaConfig) != XST_SUCCESS){
xil_printf("init_platform: Error initializing BPM DDC DMA\n");
return -1;
}
if(XAxiDma_CfgInitialize(&fmc150_adc_dma_attr.AxiDma, fmc150_adc_dma_attr.AxiDmaConfig) != XST_SUCCESS){
xil_printf("init_platform: Error initializing FMC150 ADC DMA\n");
return -1;
}
/* Enable DMA interrupts */
/*XAxiDma_IntrEnable(&ddc_dma_attr.AxiDma, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DEVICE_TO_DMA);
XAxiDma_IntrEnable(&fmc150_adc_dma_attr.AxiDma, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DEVICE_TO_DMA);
XAxiDma_Reset(&ddc_dma_attr.AxiDma);
XAxiDma_Reset(&fmc150_adc_dma_attr.AxiDma);*/
/*if(enable_ext_clk() < 0){
xil_printf("Error enabling ext_clk!\n");
return -1;
}*/
/* Init cdce72010 to FMC150 registers */
init_cdce72010();
/* Update delay accordingly to PLL output frequency */
//init_fmc150_delay();
/* Enable low (< 80MSPS)/hi(>80MSPS) speed for the ADS62P49
* depending on cdce72010 register values*/
init_ads62p49();
//write_fmc150_register(CHIPSELECT_ADS62P49, 0x020, 0x04);
/* Adjust ADC delay */
// For ADC sampling clock = 145.76 MHz
//if(update_fmc150_adc_delay(0x00, 0x18, 0x18) < 0){
// For ADC sampling clock = 122.88 MHz
//update_fmc150_adc_delay(0x00, 0x5, 0x5);
init_fmc150_delay();
if(check_mmcm_lock() < 0){
xil_printf("init_platform: Error trying to lock MMCM\n");
return -1;
}
xil_printf("init_platform: MMCM Locked!\n");
if(check_ext_lock() < 0){
xil_printf("init_platform: Error trying to lock PLL\n");
return -1;
}
xil_printf("init_platform: cdce72010 PLL Locked!\n");
//dump_cdce72010_regs();
#ifdef INIT_DEBUG
//calibrate_adc_delay();
#endif
return 0;
}
int main()
{
static XIntc intc;
Xil_ICacheEnable();
Xil_DCacheEnable();
xil_printf("Testing UART output.\r\n");
// Camera DMA Configuration
XAxiDma_Config *dmaconf = XAxiDma_LookupConfig(XPAR_AXI_DMA_0_DEVICE_ID);
XAxiDma dma;
XAxiDma_CfgInitialize(&dma, dmaconf);
XAxiDma_Resume(&dma);
XAxiDma_Reset(&dma);
while(!XAxiDma_ResetIsDone(&dma));
// Initialize Video
InitVideo();
// Example camera DMA read
// Note - transfer MUST be 4096B
// Data format is 20-bit pixel number (stored in a 32 bit integer) followed by 16-bit RGB values
// This will not work until you implement camera_stream.v.
// (or at least, until you have it barely working)
//int resdde = XAxiDma_SimpleTransfer(&dma, (u32)((unsigned char*)&camera), 4096, XAXIDMA_DEVICE_TO_DMA);
//while(XAxiDma_Busy(&dma,XAXIDMA_DEVICE_TO_DMA));
int Status;
XEmacLite *EmacLiteInstPtr = &EmacLiteInstance;
u32 PhyAddress = 0;
RecvFrameLength = 0;
XEmacLite_Config *ConfigPtr;
/*
* Initialize the EmacLite device.
*/
ConfigPtr = XEmacLite_LookupConfig(XPAR_ETHERNET_LITE_DEVICE_ID);
if (ConfigPtr == NULL) {
return XST_FAILURE;
}
Status = XEmacLite_CfgInitialize(EmacLiteInstPtr,
ConfigPtr,
ConfigPtr->BaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Set the MAC address.
*/
XEmacLite_SetMacAddress(EmacLiteInstPtr, LocalAddress);
/*
* Empty any existing receive frames.
*/
XEmacLite_FlushReceive(EmacLiteInstPtr);
/*
* Check if there is a TX buffer available, if there isn't it is an
* error.
*/
if (XEmacLite_TxBufferAvailable(EmacLiteInstPtr) != TRUE) {
return XST_FAILURE;
}
/*
* Reset the receive frame length to zero.
*/
RecvFrameLength = 0;
// Example program that sends packets and changes the color of an on-screen box upon receiving a packet.
unsigned char c = 0;
unsigned char r=0xFF, g=0x0, b=0x0;
while(1) {
c++;
if(XEmacLite_IsTxDone(ConfigPtr->BaseAddress)) {
Status = EmacLiteSendFrame(EmacLiteInstPtr, EMACLITE_TEST_FRAME_SIZE);
if (Status != XST_SUCCESS) {
if (XEmacLite_IsMdioConfigured(EmacLiteInstPtr)) {
return XST_FAILURE;
}
}
}
else {
RecvFrameLength = XEmacLite_Recv(EmacLiteInstPtr, (u8 *)RxFrame);
if (RecvFrameLength > 0) {
xil_printf("Received a packet!\r\n");
unsigned char oldr = r;
r=g;
g=b;
b=oldr;
}
// Example of writing data to the screen
int x, y;
for (x = 0; x < 20; x++)
for (y = 0; y < 20; y++)
if (t[y*20 + x]) {
fptr[y*640*4 + x*4] = b;
fptr[y*640*4 + x*4 + 1] = g;
fptr[y*640*4 + x*4 + 2] = r;
}
}
}
Xil_DCacheDisable();
Xil_ICacheDisable();
return 0;
}
/**
*
* Main function
*
* This function is the main entry of the interrupt test. It does the following:
* Set up the output terminal if UART16550 is in the hardware build
* Initialize the DMA engine
* Set up Tx and Rx channels
* Set up the interrupt system for the Tx and Rx interrupts
* Submit a transfer
* Wait for the transfer to finish
* Check transfer status
* Disable Tx and Rx interrupts
* Print test status and exit
*
* @param None
*
* @return
* - XST_SUCCESS if example finishes successfully
* - XST_FAILURE if example fails.
*
* @note None.
*
******************************************************************************/
int main(void)
{
int Status;
XAxiDma_Config *Config;
int Tries = NUMBER_OF_TRANSFERS;
int Index;
u8 *TxBufferPtr;
u8 *RxBufferPtr;
u8 Value;
TxBufferPtr = (u8 *)TX_BUFFER_BASE ;
RxBufferPtr = (u8 *)RX_BUFFER_BASE;
/* Initial setup for Uart16550 */
#ifdef XPAR_UARTNS550_0_BASEADDR
Uart550_Setup();
#endif
xil_printf("\r\n--- Entering main() --- \r\n");
Config = XAxiDma_LookupConfig(DMA_DEV_ID);
if (!Config) {
xil_printf("No config found for %d\r\n", DMA_DEV_ID);
return XST_FAILURE;
}
/* Initialize DMA engine */
Status = XAxiDma_CfgInitialize(&AxiDma, Config);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed %d\r\n", Status);
return XST_FAILURE;
}
if(XAxiDma_HasSg(&AxiDma)){
xil_printf("Device configured as SG mode \r\n");
return XST_FAILURE;
}
/* Set up Interrupt system */
Status = SetupIntrSystem(&Intc, &AxiDma, TX_INTR_ID, RX_INTR_ID);
if (Status != XST_SUCCESS) {
xil_printf("Failed intr setup\r\n");
return XST_FAILURE;
}
/* Disable all interrupts before setup */
XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DMA_TO_DEVICE);
XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DEVICE_TO_DMA);
/* Enable all interrupts */
XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DMA_TO_DEVICE);
XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DEVICE_TO_DMA);
/* Initialize flags before start transfer test */
TxDone = 0;
RxDone = 0;
Error = 0;
Value = TEST_START_VALUE;
for(Index = 0; Index < MAX_PKT_LEN; Index ++) {
TxBufferPtr[Index] = Value;
Value = (Value + 1) & 0xFF;
}
/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
* is enabled
*/
Xil_DCacheFlushRange((u32)TxBufferPtr, MAX_PKT_LEN);
#ifdef __aarch64__
Xil_DCacheFlushRange((UINTPTR)RxBufferPtr, MAX_PKT_LEN);
#endif
/* Send a packet */
for(Index = 0; Index < Tries; Index ++) {
Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) RxBufferPtr,
MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) TxBufferPtr,
MAX_PKT_LEN, XAXIDMA_DMA_TO_DEVICE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Wait TX done and RX done
*/
while (!TxDone && !RxDone && !Error) {
/* NOP */
}
if (Error) {
xil_printf("Failed test transmit%s done, "
"receive%s done\r\n", TxDone? "":" not",
RxDone? "":" not");
goto Done;
}
/*
* Test finished, check data
*/
Status = CheckData(MAX_PKT_LEN, 0xC);
if (Status != XST_SUCCESS) {
xil_printf("Data check failed\r\n");
goto Done;
}
}
xil_printf("AXI DMA interrupt example test passed\r\n");
/* Disable TX and RX Ring interrupts and return success */
DisableIntrSystem(&Intc, TX_INTR_ID, RX_INTR_ID);
Done:
xil_printf("--- Exiting main() --- \r\n");
return XST_SUCCESS;
}
/**
*
* Main function
*
* This function is the main entry of the tests on DMA core. It sets up
* DMA engine to be ready to receive and send packets, then a packet is
* transmitted and will be verified after it is received via the DMA loopback
* widget.
*
* @param None
*
* @return
* - XST_SUCCESS if test passes
* - XST_FAILURE if test fails.
*
* @note None.
*
******************************************************************************/
int main(void)
{
xil_printf("Roundsss %d\n",count);
count++;
//cplx_data_t* stim_buf;// Array
//cplx_data_t* result_buf;
int Status;
XAxiDma_Config *Config;
init_platform();
// stim_bguf = (cplx_data_t*) malloc(sizeof(cplx_data_t)*FFT_MAX_NUM_PTS);
// if (stim_buf == NULL)
// {
// xil_printf("ERROR! Failed to allocate memory for the stimulus buffer.\n\r");
// return -1;
// }
//
// result_buf = (cplx_data_t*) malloc(sizeof(cplx_data_t)*FFT_MAX_NUM_PTS);
// if (result_buf == NULL)
// {
// xil_printf("ERROR! Failed to allocate memory for the result buffer.\n\r");
// return -1;
// }
// Fill stimulus buffer with some signal
memcpy(stim_buf, sig_two_sine_waves, sizeof(cplx_data_t)*FFT_MAX_NUM_PTS);
xil_printf("\r\n--- Entering main() --- \r\n");
Config = XAxiDma_LookupConfig(DMA_DEV_ID);
if (!Config) {
xil_printf("No config found for %d\r\n", DMA_DEV_ID);
return XST_FAILURE;
}
/* Initialize DMA engine */
Status = XAxiDma_CfgInitialize(&AxiDma, Config);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed %d\r\n", Status);
return XST_FAILURE;
}
if(!XAxiDma_HasSg(&AxiDma)) {
xil_printf("Device configured as Simple mode \r\n");
return XST_FAILURE;
}
Status = TxSetup(&AxiDma);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
Status = RxSetup(&AxiDma);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
//xil_printf("checkpoint 1");
/* Send a packet */
int sendC =0;
for (sendC = 0; sendC < 1; sendC++) {
SendPacket(&AxiDma,sendC);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
}
// xil_printf("checkpoint 2 %d",XPAR_AXI_GPIO_0_DEVICE_ID);
// XGpio_Initialize(gpio_inst, 2);
// if (Status != XST_SUCCESS)
// {
// xil_printf("ERROR! Initialization of AXI GPIO instance failed.\n\r");
//
// }
// int reg= 1;
// xil_printf("checkpoint 3");
// XGpio_DiscreteWrite(gpio_inst, 1, reg);
// //XGpio_DiscreteWrite()
xil_printf("\nfinish!!!!!!!");
//Status = SendPacket(&AxiDma);
/* Check DMA transfer result */
Status = CheckDmaResult(&AxiDma);
xil_printf("AXI DMA SG Polling Test %s\r\n",
(Status == XST_SUCCESS)? "passed":"failed");
xil_printf("--- Exiting main() --- \r\n");
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
return XST_SUCCESS;
}
/**
*
* This function demonstrates the usage usage of the Axi Ethernet by sending
* and receiving frames in interrupt driven SGDMA mode.
*
*
* @param IntcInstancePtr is a pointer to the instance of the Intc
* component.
* @param AxiEthernetInstancePtr is a pointer to the instance of the
* AxiEthernet component.
* @param DmaInstancePtr is a pointer to the instance of the AXIDMA
* component.
* @param AxiEthernetDeviceId is Device ID of the Axi Ethernet Device ,
* typically XPAR_<AXIETHERNET_instance>_DEVICE_ID value from
* xparameters.h.
* @param AxiDmaDeviceId is Device ID of the Axi DMAA Device ,
* typically XPAR_<AXIDMA_instance>_DEVICE_ID value from
* xparameters.h.
* @param AxiEthernetIntrId is the Interrupt ID and is typically
* XPAR_<INTC_instance>_<AXIETHERNET_instance>_VEC_ID
* value from xparameters.h.
* @param DmaRxIntrId is the interrupt id for DMA Rx and is typically
* taken from XPAR_<AXIETHERNET_instance>_CONNECTED_DMARX_INTR
* @param DmaTxIntrId is the interrupt id for DMA Tx and is typically
* taken from XPAR_<AXIETHERNET_instance>_CONNECTED_DMATX_INTR
*
* @return -XST_SUCCESS to indicate success.
* -XST_FAILURE to indicate failure.
*
* @note AxiDma hardware must be initialized before initializing
* AxiEthernet. Since AxiDma reset line is connected to the
* AxiEthernet reset line, a reset of AxiDma hardware during its
* initialization would reset AxiEthernet.
*
******************************************************************************/
int AxiEthernetExtVlanExample(INTC *IntcInstancePtr,
XAxiEthernet *AxiEthernetInstancePtr,
XAxiDma *DmaInstancePtr,
u16 AxiEthernetDeviceId,
u16 AxiDmaDeviceId,
u16 AxiEthernetIntrId,
u16 DmaRxIntrId,
u16 DmaTxIntrId)
{
int Status;
int LoopbackSpeed;
XAxiEthernet_Config *MacCfgPtr;
XAxiDma_BdRing *RxRingPtr = XAxiDma_GetRxRing(DmaInstancePtr);
XAxiDma_BdRing *TxRingPtr = XAxiDma_GetTxRing(DmaInstancePtr);
XAxiDma_Bd BdTemplate;
XAxiDma_Config* DmaConfig;
/*************************************/
/* Setup device for first-time usage */
/*************************************/
/*
* Get the configuration of AxiEthernet hardware.
*/
MacCfgPtr = XAxiEthernet_LookupConfig(AxiEthernetDeviceId);
/*
* Check if DMA is present or not.
*/
if(MacCfgPtr->AxiDevType != XPAR_AXI_DMA) {
AxiEthernetUtilErrorTrap
("Device HW not configured for SGDMA mode\r\n");
return XST_FAILURE;
}
DmaConfig = XAxiDma_LookupConfig(AxiDmaDeviceId);
/*
* Initialize AXIDMA engine. AXIDMA engine must be initialized before
* AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
* reset, and since AXIDMA reset line is connected to AxiEthernet, this
* would ensure a reset of AxiEthernet.
*/
Status = XAxiDma_CfgInitialize(DmaInstancePtr, DmaConfig);
if(Status != XST_SUCCESS) {
AxiEthernetUtilErrorTrap("Error initializing DMA\r\n");
return XST_FAILURE;
}
/*
* Initialize AxiEthernet hardware.
*/
Status = XAxiEthernet_CfgInitialize(AxiEthernetInstancePtr, MacCfgPtr,
MacCfgPtr->BaseAddress);
if (Status != XST_SUCCESS) {
AxiEthernetUtilErrorTrap("Error in initialize");
return XST_FAILURE;
}
/*
* Set the MAC address
*/
Status = XAxiEthernet_SetMacAddress(AxiEthernetInstancePtr,
AxiEthernetMAC);
if (Status != XST_SUCCESS) {
AxiEthernetUtilErrorTrap("Error setting MAC address");
return XST_FAILURE;
}
/*
* Setup RxBD space.
*
* We have already defined a properly aligned area of memory to store
* RxBDs at the beginning of this source code file so just pass its
* address into the function. No MMU is being used so the physical and
* virtual addresses are the same.
*
* Setup a BD template for the Rx channel. This template will be copied
* to every RxBD. We will not have to explicitly set these again.
*/
/*
* Create the RxBD ring
*/
Status = XAxiDma_BdRingCreate(RxRingPtr, (u32) &RxBdSpace,
(u32) &RxBdSpace, BD_ALIGNMENT, RXBD_CNT);
if (Status != XST_SUCCESS) {
AxiEthernetUtilErrorTrap("Error setting up RxBD space");
return XST_FAILURE;
}
XAxiDma_BdClear(&BdTemplate);
Status = XAxiDma_BdRingClone(RxRingPtr, &BdTemplate);
if (Status != XST_SUCCESS) {
AxiEthernetUtilErrorTrap("Error initializing RxBD space");
return XST_FAILURE;
}
/*
* Setup TxBD space.
*
* Like RxBD space, we have already defined a properly aligned area of
* memory to use.
*/
/*
* Create the TxBD ring
*/
Status = XAxiDma_BdRingCreate(TxRingPtr, (u32) &TxBdSpace,
(u32) &TxBdSpace, BD_ALIGNMENT, TXBD_CNT);
if (Status != XST_SUCCESS) {
AxiEthernetUtilErrorTrap("Error setting up TxBD space");
return XST_FAILURE;
}
/*
* We reuse the bd template, as the same one will work for both rx and
* tx.
*/
Status = XAxiDma_BdRingClone(TxRingPtr, &BdTemplate);
if (Status != XST_SUCCESS) {
AxiEthernetUtilErrorTrap("Error initializing TxBD space");
return XST_FAILURE;
}
/*
* Set PHY to loopback, speed depends on phy type.
* MII is 100 and all others are 1000.
*/
if (XAxiEthernet_GetPhysicalInterface(AxiEthernetInstancePtr)
== XAE_PHY_TYPE_MII){
LoopbackSpeed = AXIETHERNET_LOOPBACK_SPEED;
} else {
LoopbackSpeed = AXIETHERNET_LOOPBACK_SPEED_1G;
}
AxiEthernetUtilEnterLoopback(AxiEthernetInstancePtr, LoopbackSpeed);
/*
* Set PHY<-->MAC data clock
*/
Status = XAxiEthernet_SetOperatingSpeed(AxiEthernetInstancePtr,
(u16)LoopbackSpeed);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Setting the operating speed of the MAC needs a delay. There
* doesn't seem to be register to poll, so please consider this
* during your application design.
*/
AxiEthernetUtilPhyDelay(2);
/*
* Connect to the interrupt controller and enable interrupts
*/
Status = AxiEthernetSetupIntrSystem(IntcInstancePtr,
AxiEthernetInstancePtr,
DmaInstancePtr,
AxiEthernetIntrId, DmaRxIntrId,
DmaTxIntrId);
/****************************/
/* Run the example */
/****************************/
/* Run the new VLAN feature. Make sure HW has the capability */
if (XAxiEthernet_IsTxVlanTran(AxiEthernetInstancePtr) &&
XAxiEthernet_IsTxVlanStrp(AxiEthernetInstancePtr) &&
XAxiEthernet_IsTxVlanTag(AxiEthernetInstancePtr) &&
XAxiEthernet_IsRxVlanTran(AxiEthernetInstancePtr) &&
XAxiEthernet_IsRxVlanStrp(AxiEthernetInstancePtr) &&
XAxiEthernet_IsRxVlanTag(AxiEthernetInstancePtr)) {
Status = AxiEthernetSgDmaIntrExtVlanExample
(AxiEthernetInstancePtr,DmaInstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
}
/*
* Disable the interrupts for the AxiEthernet device
*/
AxiEthernetDisableIntrSystem(IntcInstancePtr, AxiEthernetIntrId,
DmaRxIntrId, DmaTxIntrId);
/*
* Stop the device
*/
XAxiEthernet_Stop(AxiEthernetInstancePtr);
return XST_SUCCESS;
}