void load_ram()
{
int ram_addr = 0x4;
int read_out =0;
// u32 out;
ram_addr = 0x4;
read_out = 0;
for(read_out =0; read_out <numb_pixels; read_out++){
XBram_WriteReg(BRAM_BASE, ram_addr, pixel[read_out]);
// out = XBram_ReadReg(BRAM_BASE, ram_addr);
// printf("RAM %x %lx\n\r",ram_addr, out);
ram_addr = ram_addr +4;
}
//enable the data
XBram_WriteReg(BRAM_BASE, 0, (u32)numb_pixels);
}
/**
*
* This function ensures that ECC in the BRAM is initialized if no hardware
* initialization is available. The ECC bits are initialized by reading and
* writing data in the memory. This code is not optimized to only read data
* in initialized sections of the BRAM.
*
* @param ConfigPtr is a reference to a structure containing information
* about a specific BRAM device.
* @param EffectiveAddr is the device base address in the virtual memory
* address space.
*
* @return
* None
*
* @note None.
*
*****************************************************************************/
void InitializeECC(XBram_Config *ConfigPtr, u32 EffectiveAddr)
{
u32 Addr;
volatile u32 Data;
if (ConfigPtr->EccPresent &&
ConfigPtr->EccOnOffRegister &&
ConfigPtr->EccOnOffResetValue == 0 &&
ConfigPtr->WriteAccess != 0) {
for (Addr = ConfigPtr->MemBaseAddress;
Addr < ConfigPtr->MemHighAddress; Addr+=4) {
Data = XBram_In32(Addr);
XBram_Out32(Addr, Data);
}
XBram_WriteReg(EffectiveAddr, XBRAM_ECC_ON_OFF_OFFSET, 1);
}
}
/**
* Enable interrupts. This function will assert if the hardware device has not
* been built with interrupt capabilities.
*
* @param InstancePtr is the BRAM instance to operate on.
* @param Mask is the mask to enable. Bit positions of 1 are enabled.
* This mask is formed by OR'ing bits from XBRAM_IR*
* bits which are contained in xbram_hw.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask)
{
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
/*
* Read the interrupt enable register and only enable the specified
* interrupts without disabling or enabling any others.
*/
Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET);
XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET,
Register | Mask);
}
/**
* Clear pending interrupts with the provided mask. This function should be
* called after the software has serviced the interrupts that are pending.
* This function will assert if the hardware device has not been built with
* interrupt capabilities.
*
* @param InstancePtr is the BRAM instance to operate on.
* @param Mask is the mask to clear pending interrupts for. Bit positions
* of 1 are cleared. This mask is formed by OR'ing bits from
* XBRAM_IR* bits which are contained in
* xbram_hw.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XBram_InterruptClear(XBram *InstancePtr, u32 Mask)
{
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
/*
* Read the interrupt status register and only clear the interrupts
* that are specified without affecting any others. Since the register
* is a toggle on write, make sure any bits to be written are already
* set.
*/
Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_STATUS_OFFSET);
XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_STATUS_OFFSET,
Register & Mask);
}
